1 /*
2 * Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
3 *
4 * Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
5 * the the People's Republic of China and other countries.
6 * All Allwinner Technology Co.,Ltd. trademarks are used with permission.
7 *
8 * DISCLAIMER
9 * THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
10 * IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
11 * IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
12 * ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
13 * ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
14 * COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
15 * YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY.
16 *
17 *
18 * THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
19 * PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
20 * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
21 * THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
22 * OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
23 * IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
30 * OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32 
33 #ifndef __COMMON_GPADC_I_H__
34 #define __COMMON_GPADC_I_H__
35 
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39 
40 /* GPADC register offset */
41 #define GP_SR_REG       (0x00) /* Sample Rate config register */
42 #define GP_CTRL_REG     (0x04) /* control register */
43 #define GP_CS_EN_REG        (0x08) /* compare and select enable register */
44 #define GP_FIFO_INTC_REG    (0x0c) /* FIFO interrupt config register */
45 #define GP_FIFO_INTS_REG    (0x10) /* FIFO interrupt status register */
46 #define GP_FIFO_DATA_REG    (0X14) /* FIFO data register */
47 #define GP_CB_DATA_REG      (0X18) /* calibration data register */
48 #define GP_DATAL_INTC_REG   (0x20)
49 #define GP_DATAH_INTC_REG   (0x24)
50 #define GP_DATA_INTC_REG    (0x28)
51 #define GP_DATAL_INTS_REG   (0x30)
52 #define GP_DATAH_INTS_REG   (0x34)
53 #define GP_DATA_INTS_REG    (0x38)
54 #define GP_CH0_CMP_DATA_REG (0x40) /* channal 0 compare data register */
55 #define GP_CH1_CMP_DATA_REG (0x44) /* channal 1 compare data register */
56 #define GP_CH2_CMP_DATA_REG (0x48) /* channal 2 compare data register */
57 #define GP_CH3_CMP_DATA_REG (0x4c) /* channal 3 compare data register */
58 #define GP_CH4_CMP_DATA_REG (0x50) /* channal 4 compare data register */
59 #define GP_CH5_CMP_DATA_REG (0x54) /* channal 5 compare data register */
60 #define GP_CH6_CMP_DATA_REG (0x58) /* channal 6 compare data register */
61 #define GP_CH7_CMP_DATA_REG (0x5c) /* channal 7 compare data register */
62 #define GP_CH0_DATA_REG     (0x80) /* channal 0 data register */
63 #define GP_CH1_DATA_REG     (0x84) /* channal 1 data register */
64 #define GP_CH2_DATA_REG     (0x88) /* channal 2 data register */
65 #define GP_CH3_DATA_REG     (0x8c) /* channal 3 data register */
66 #define GP_CH4_DATA_REG     (0x90) /* channal 4 data register */
67 #define GP_CH5_DATA_REG     (0x94) /* channal 5 data register */
68 #define GP_CH6_DATA_REG     (0x98) /* channal 6 data register */
69 #define GP_CH7_DATA_REG     (0x9c) /* channal 7 data register */
70 
71 /*
72  * GP_SR_REG default value: 0x01df_002f 50KHZ
73  * sample_rate = clk_in/(n+1) = 24MHZ/(0x1df + 1) = 50KHZ
74  */
75 #define GP_SR_CON       (0xffff << 16)
76 
77 /* GP_CTRL_REG default value:0x0000_0000 */
78 #define GP_FIRST_CONCERT_DLY    (0xff<<24) /* delay time of the first time */
79 #define GP_CALI_EN      (1 << 17) /* enable calibration */
80 #define GP_ADC_EN       (1 << 16) /* GPADC function enable */
81 
82 /*
83  * 00:single conversion mode
84  * 01:single-cycle conversion mode
85  * 10:continuous mode, 11:burst mode
86  */
87 #define GP_MODE_SELECT      (3 << 18)
88 
89 /* 0:disable, 1:enable */
90 #define GP_CH7_CMP_EN       (1 << 23)
91 #define GP_CH6_CMP_EN       (1 << 22)
92 #define GP_CH5_CMP_EN       (1 << 21)
93 #define GP_CH4_CMP_EN       (1 << 20)
94 #define GP_CH3_CMP_EN       (1 << 19)
95 #define GP_CH2_CMP_EN       (1 << 18)
96 #define GP_CH1_CMP_EN       (1 << 17)
97 #define GP_CH0_CMP_EN       (1 << 16)
98 #define GP_CH7_SELECT       (1 << 7)
99 #define GP_CH6_SELECT       (1 << 6)
100 #define GP_CH5_SELECT       (1 << 5)
101 #define GP_CH4_SELECT       (1 << 4)
102 #define GP_CH3_SELECT       (1 << 3)
103 #define GP_CH2_SELECT       (1 << 2)
104 #define GP_CH1_SELECT       (1 << 1)
105 #define GP_CH0_SELECT       (1 << 0)
106 
107 /*
108  * GP_FIFO_INTC_REG default value: 0x0000_0f00
109  * 0:disable, 1:enable
110  */
111 #define FIFO_OVER_IRQ_EN    (1 << 17) /* fifo over run irq enable */
112 #define FIFO_DATA_IRQ_EN    (1 << 16) /* fifo data irq enable */
113 
114 /* write 1 to flush TX FIFO, self clear to 0 */
115 #define FIFO_FLUSH      (1 << 4)
116 
117 /*
118  * GP_FIFO_INTS_REG default value: 0x0000_0000
119  * 0:no pending irq, 1: over pending, need write 1 to clear flag
120  */
121 #define FIFO_OVER_PEND      (1 << 17) /* fifo over pending flag */
122 #define FIFO_DATA_PEND      (1 << 16) /* fifo data pending flag */
123 #define FIFO_CNT        (0x3f << 8) /* the data count in fifo */
124 
125 /* GP_FIFO_DATA_REG default value: 0x0000_0000 */
126 #define GP_FIFO_DATA        (0xfff << 0) /* GPADC data in fifo */
127 
128 /* GP_CB_DATA_REG default value: 0x0000_0000 */
129 #define GP_CB_DATA      (0xfff << 0) /* GPADC calibration data */
130 
131 /* GP_INTC_REG default value: 0x0000_0000 */
132 #define GP_CH7_LOW_IRQ_EN   (1 << 7) /* 0:disable, 1:enable */
133 #define GP_CH6_LOW_IRQ_EN   (1 << 6)
134 #define GP_CH5_LOW_IRQ_EN   (1 << 5)
135 #define GP_CH4_LOW_IRQ_EN   (1 << 4)
136 #define GP_CH3_LOW_IRQ_EN   (1 << 3)
137 #define GP_CH2_LOW_IRQ_EN   (1 << 2)
138 #define GP_CH1_LOW_IRQ_EN   (1 << 1)
139 #define GP_CH0_LOW_IRQ_EN   (1 << 0)
140 #define GP_CH7_HIG_IRQ_EN   (1 << 7)
141 #define GP_CH6_HIG_IRQ_EN   (1 << 6)
142 #define GP_CH5_HIG_IRQ_EN   (1 << 5)
143 #define GP_CH4_HIG_IRQ_EN   (1 << 4)
144 #define GP_CH3_HIG_IRQ_EN   (1 << 3)
145 #define GP_CH2_HIG_IRQ_EN   (1 << 2)
146 #define GP_CH1_HIG_IRQ_EN   (1 << 1)
147 #define GP_CH0_HIG_IRQ_EN   (1 << 0)
148 #define GP_CH7_DATA_IRQ_EN  (1 << 7)
149 #define GP_CH6_DATA_IRQ_EN  (1 << 6)
150 #define GP_CH5_DATA_IRQ_EN  (1 << 5)
151 #define GP_CH4_DATA_IRQ_EN  (1 << 4)
152 #define GP_CH3_DATA_IRQ_EN  (1 << 3)
153 #define GP_CH2_DATA_IRQ_EN  (1 << 2)
154 #define GP_CH1_DATA_IRQ_EN  (1 << 1)
155 #define GP_CH0_DATA_IRQ_EN  (1 << 0)
156 
157 /* GP_INTS_REG default value: 0x0000_0000 */
158 #define GP_CH7_LOW      (1 << 7) /* 0:no pending, 1:pending */
159 #define GP_CH6_LOW      (1 << 6)
160 #define GP_CH5_LOW      (1 << 5)
161 #define GP_CH4_LOW      (1 << 4)
162 #define GP_CH3_LOW      (1 << 3)
163 #define GP_CH2_LOW      (1 << 2)
164 #define GP_CH1_LOW      (1 << 1)
165 #define GP_CH0_LOW      (1 << 0)
166 #define GP_CH7_HIG      (1 << 7)
167 #define GP_CH6_HIG      (1 << 6)
168 #define GP_CH5_HIG      (1 << 5)
169 #define GP_CH4_HIG      (1 << 4)
170 #define GP_CH3_HIG      (1 << 3)
171 #define GP_CH2_HIG      (1 << 2)
172 #define GP_CH1_HIG      (1 << 1)
173 #define GP_CH0_HIG      (1 << 0)
174 #define GP_CH7_DATA     (1 << 7)
175 #define GP_CH6_DATA     (1 << 6)
176 #define GP_CH5_DATA     (1 << 5)
177 #define GP_CH4_DATA     (1 << 4)
178 #define GP_CH3_DATA     (1 << 3)
179 #define GP_CH2_DATA     (1 << 2)
180 #define GP_CH1_DATA     (1 << 1)
181 #define GP_CH0_DATA     (1 << 0)
182 
183 /* GP_CH0_CMP_DATA_REG default value 0x0bff_0400 */
184 #define GP_CH0_CMP_HIG_DATA     (0xfff << 16)
185 #define GP_CH0_CMP_LOW_DATA     (0xfff << 0)
186 /* GP_CH1_CMP_DATA_REG default value 0x0bff_0400 */
187 #define GP_CH1_CMP_HIG_DATA     (0xfff << 16)
188 #define GP_CH1_CMP_LOW_DATA     (0xfff << 0)
189 /* GP_CH2_CMP_DATA_REG default value 0x0bff_0400 */
190 #define GP_CH2_CMP_HIG_DATA     (0xfff << 16)
191 #define GP_CH2_CMP_LOW_DATA     (0xfff << 0)
192 /* GP_CH3_CMP_DATA_REG default value 0x0bff_0400 */
193 #define GP_CH3_CMP_HIG_DATA     (0xfff << 16)
194 #define GP_CH3_CMP_LOW_DATA     (0xfff << 0)
195 /* GP_CH4_CMP_DATA_REG default value 0x0bff_0400 */
196 #define GP_CH4_CMP_HIG_DATA     (0xfff << 16)
197 #define GP_CH4_CMP_LOW_DATA     (0xfff << 0)
198 /* GP_CH5_CMP_DATA_REG default value 0x0bff_0400 */
199 #define GP_CH5_CMP_HIG_DATA     (0xfff << 16)
200 #define GP_CH5_CMP_LOW_DATA     (0xfff << 0)
201 /* GP_CH6_CMP_DATA_REG default value 0x0bff_0400 */
202 #define GP_CH6_CMP_HIG_DATA     (0xfff << 16)
203 #define GP_CH6_CMP_LOW_DATA     (0xfff << 0)
204 /* GP_CH7_CMP_DATA_REG default value 0x0bff_0400 */
205 #define GP_CH7_CMP_HIG_DATA     (0xfff << 16)
206 #define GP_CH7_CMP_LOW_DATA     (0xfff << 0)
207 
208 /* GP_CH0_DATA_REG default value:0x0000_0000 */
209 #define GP_CH_DATA_MASK     (0xfff << 0) /*data mask */
210 
211 #define CHANNEL_0_SELECT        (0x01 << 0)
212 #define CHANNEL_1_SELECT        (0x01 << 1)
213 #define CHANNEL_2_SELECT        (0x01 << 2)
214 #define CHANNEL_3_SELECT        (0x01 << 3)
215 #define CHANNEL_4_SELECT        (0x01 << 4)
216 #define CHANNEL_5_SELECT        (0x01 << 5)
217 #define CHANNEL_6_SELECT        (0x01 << 6)
218 #define CHANNEL_7_SELECT        (0x01 << 7)
219 #define CHANNEL_MAX_NUM         8
220 #define CHANNEL_NUM 4
221 
222 
223 #ifdef __cplusplus
224 }
225 #endif
226 #endif /* __COMMON_GPADC_I_H__ */
227