1 /*
2 * Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
3 *
4 * Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
5 * the the People's Republic of China and other countries.
6 * All Allwinner Technology Co.,Ltd. trademarks are used with permission.
7 *
8 * DISCLAIMER
9 * THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
10 * IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
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14 * COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
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31 */
32 
33 #include <stdio.h>
34 #include <string.h>
35 #include <init.h>
36 
37 #include <hal_gpio.h>
38 #include "../gpio.h"
39 
40 static const unsigned int sun8iw19p1_irq_bank_base[] =
41 {
42     SUNXI_PIO_BANK_BASE(PC_BASE, 0),
43     SUNXI_PIO_BANK_BASE(PD_BASE, 1),
44     SUNXI_PIO_BANK_BASE(PE_BASE, 2),
45     SUNXI_PIO_BANK_BASE(PF_BASE, 3),
46     SUNXI_PIO_BANK_BASE(PG_BASE, 4),
47     SUNXI_PIO_BANK_BASE(PH_BASE, 5),
48     SUNXI_PIO_BANK_BASE(PI_BASE, 6),
49 };
50 
51 static const unsigned int sun8iw19p1_bank_base[] =
52 {
53     SUNXI_PIO_BANK_BASE(PC_BASE, 0),
54     SUNXI_PIO_BANK_BASE(PD_BASE, 1),
55     SUNXI_PIO_BANK_BASE(PE_BASE, 2),
56     SUNXI_PIO_BANK_BASE(PF_BASE, 3),
57     SUNXI_PIO_BANK_BASE(PG_BASE, 4),
58     SUNXI_PIO_BANK_BASE(PH_BASE, 5),
59     SUNXI_PIO_BANK_BASE(PI_BASE, 6),
60 };
61 
62 static const int sun8iw19p1_bank_irq_num[] =
63 {
64     SUNXI_IRQ_GPIOC,
65     SUNXI_IRQ_GPIOD,
66     SUNXI_IRQ_GPIOE,
67     SUNXI_IRQ_GPIOF,
68     SUNXI_IRQ_GPIOG,
69     SUNXI_IRQ_GPIOH,
70     SUNXI_IRQ_GPIOI,
71 };
72 
73 static struct gpio_desc sun8iw19p1_gpio_desc =
74 {
75     .membase = SUNXI_GPIO_PBASE,
76     .virq_offset = 0,
77     .irq_arry_size = ARRAY_SIZE(sun8iw19p1_bank_irq_num),
78     .irq = (const uint32_t *)sun8iw19p1_bank_irq_num,
79     .pin_base = PA_BASE,
80     .banks = ARRAY_SIZE(sun8iw19p1_bank_base),
81     .bank_base = (const uint32_t *)sun8iw19p1_bank_base,
82     .irq_banks = ARRAY_SIZE(sun8iw19p1_irq_bank_base),
83     .irq_bank_base = (const uint32_t *)sun8iw19p1_irq_bank_base,
84 };
85 
86 static const unsigned sun8iw19p1_r_irq_bank_base[] =
87 {
88     SUNXI_R_PIO_BANK_BASE(PL_BASE, 0),
89 };
90 
91 static const unsigned sun8iw19p1_r_bank_base[] =
92 {
93     SUNXI_PIO_BANK_BASE(PL_BASE, 0),
94 };
95 
96 static const int sun8iw19p1_r_bank_irq_num[] =
97 {
98     SUNXI_IRQ_R_GPIOL,
99 };
100 
101 static const struct gpio_desc sun8iw19p1_r_gpio_desc =
102 {
103     .membase = SUXNI_GPIO_R_PBASE,
104     .virq_offset = BANK_BOUNDARY,
105     .irq_arry_size = ARRAY_SIZE(sun8iw19p1_r_bank_irq_num),
106     .irq = (const uint32_t *)sun8iw19p1_r_bank_irq_num,
107     .pin_base = PL_BASE,
108     .banks = ARRAY_SIZE(sun8iw19p1_r_bank_base),
109     .bank_base = (const uint32_t *)sun8iw19p1_r_bank_base,
110     .irq_banks = ARRAY_SIZE(sun8iw19p1_r_irq_bank_base),
111     .irq_bank_base = (const uint32_t *)sun8iw19p1_r_irq_bank_base,
112 };
113 
114 static const struct gpio_desc *platform_gpio_desc[] =
115 {
116     &sun8iw19p1_gpio_desc,
117     &sun8iw19p1_r_gpio_desc,
118     NULL,
119 };
120 
121 /*
122  * Called by hal_gpio_init().
123  */
gpio_get_platform_desc(void)124 const struct gpio_desc **gpio_get_platform_desc(void)
125 {
126     return platform_gpio_desc;
127 }
128