1 /* 2 ********************************************************************************************************* 3 * AR100 SYSTEM 4 * AR100 Software System Develop Kits 5 * clock control unit module 6 * 7 * (c) Copyright 2012-2016, Sunny China 8 * All Rights Reserved 9 * 10 * File : ccu_regs.h 11 * By : Sunny 12 * Version : v1.0 13 * Date : 2012-5-7 14 * Descript: clock control unit register defines. 15 * Update : date auther ver notes 16 * 2012-5-7 8:47:58 Sunny 1.0 Create this file. 17 ********************************************************************************************************* 18 */ 19 20 #ifndef __CCU_REGS_H__ 21 #define __CCU_REGS_H__ 22 23 #include <sunxi_hal_common.h> 24 25 /* refer to prcm spec register description */ 26 typedef struct ccu_cpus_clk_cfg_reg0000 { 27 u32 factor_m:5; /* bit0, cpus clock ratio */ 28 u32 reserved2:3; /* bit5, reserved */ 29 u32 factor_n:2; /* bit8, cpus post divider */ 30 u32 reserved1:14; /* bit10, reserved */ 31 u32 src_sel:3; /* bit24, cpus source select */ 32 u32 reserved0:5; /* bit27, reserved */ 33 } ccu_cpus_clk_cfg_reg0000_t; 34 35 typedef struct ccu_apbs1_cfg_reg000c { 36 u32 factor_m:5; /* bit0, apbs1 clock divider ratio */ 37 u32 reserved2:3; /* bit5, reserved */ 38 u32 factor_n:2; /* bit8, cpus post divider */ 39 u32 reserved1:14; /* bit10, reserved */ 40 u32 src_sel:3; /* bit24, cpus source select */ 41 u32 reserved0:5; /* bit27, reserved */ 42 } ccu_apbs1_cfg_reg000c_t; 43 44 typedef struct ccu_apbs2_cfg_reg0010 { 45 u32 factor_m:5; /* bit0, cpus clock ratio */ 46 u32 reserved2:3; /* bit5, reserved */ 47 u32 factor_n:2; /* bit8, cpus post divider */ 48 u32 reserved1:14; /* bit10, reserved */ 49 u32 src_sel:3; /* bit24, cpus source select */ 50 u32 reserved0:5; /* bit27, reserved */ 51 } ccu_apbs2_cfg_reg0010_t; 52 53 typedef struct ccu_mod_gate_reset_reg { 54 u32 gate:1; /* bit0, gate */ 55 u32 reserved1:15; /* bit1, reserved */ 56 u32 reset:1; /* bit16, reset */ 57 u32 reserved0:15; /* bit17, reserved */ 58 } ccu_mod_gate_reset_reg_t; 59 60 typedef struct ccu_mod_clk_reg { 61 u32 factor_m:5; /* bit0, clock divider ratio m */ 62 u32 reserved2:3; /* bit5, reserved */ 63 u32 factor_n:2; /* bit8, clock pre-divider ratio n */ 64 u32 reserved1:14; /* bit10, reserved */ 65 u32 src_sel:1; /* bit24, clock source select */ 66 u32 reserved0:6; /* bit25, reserved */ 67 u32 sclk_gate:1; /* bit31, gating special clock(max clock = 24M) */ 68 } ccu_mod_clk_reg_t; 69 70 typedef struct ccu_mod_lpsd_clk_reg { 71 u32 factor_m0:5; /* bit0, clock divider ratio m0 */ 72 u32 reserved3:3; /* bit5, reserved */ 73 u32 factor_m1:5; /* bit8 - bit12, clock pre-divider ratio m1 */ 74 u32 reserved2:3; /* bit13 - bit15, reserved */ 75 u32 factor_n:2; /* bit16 - bit17, clock pre-divider ratio n */ 76 u32 reserved1:6; /* bit18 - bit23, reserved */ 77 u32 src_sel:2; /* bit24, clock source select */ 78 u32 reserved0:5; /* bit26, reserved */ 79 u32 sclk_gate:1; /* bit31, gating */ 80 } ccu_mod_lpsd_clk_reg_t; 81 82 typedef struct ccu_mod_audio_clk_reg { 83 u32 factor_m:5; /* bit0, clock divider ratio m */ 84 u32 reserved2:3; /* bit5, reserved */ 85 u32 factor_n:2; /* bit8, clock pre-divider ratio n */ 86 u32 reserved1:14; /* bit10, reserved */ 87 u32 src_sel:2; /* bit24, clock source select */ 88 u32 reserved0:5; /* bit26, reserved */ 89 u32 sclk_gate:1; /* bit31, gating */ 90 } ccu_mod_audio_clk_reg_t; 91 92 typedef struct ccu_pll_ctrl_reg0240 { 93 u32 pll_bias_en:1; /* bit0, pll bias enbale */ 94 u32 gm0:1; /* bit1, gm0 */ 95 u32 gm1:1; /* bit2, gm1 */ 96 u32 reserved1:21; /* bit3, reserved */ 97 u32 test_clk_sel:1; /* bit24, test clock select */ 98 u32 reserved0:7; /* bit25, reserved */ 99 } ccu_pll_ctrl_reg0240_t; 100 101 typedef struct ccu_pll_ctrl_reg0244 { 102 u32 ldo_en:1; /* bit0, ldo enable, all pll digital power */ 103 u32 reserved2:1; /* bit1, reserved */ 104 u32 osc24M_en:1; /* bit2, osc24M enable */ 105 u32 plltest_en:1; /* bit3, clock test enable, for verify */ 106 u32 mbias_en:1; /* bit4, chip master bias enable */ 107 u32 reserved1:11; /* bit5, reserved */ 108 u32 pllvdd_ldo_out_ctrl:3; /* bit16, pllvdd ldo output control */ 109 u32 reserved0:5; /* bit19, reserved */ 110 u32 key_field:8; /* bit24, key field LDO enable bit */ 111 } ccu_pll_ctrl_reg0244_t; 112 113 typedef struct ccu_sys_pwroff_gate_reg0250 { 114 u32 reserved2:2; /* bit0, reserved */ 115 u32 vdd_cpus_gate:1; /* bit2, gating the corresponding modules to the 116 * CPUS power domain when VDD_SYS power off 117 */ 118 u32 vdd_sys2usb_gate:1; /* bit3 */ 119 u32 vdd_ddr_gate:1; /* bit4 */ 120 u32 reserved1:3; /* bit5, reserved */ 121 u32 vdd_usb2cpus_gate:1; /* bit8 */ 122 u32 reserved0:23; /* bit9, reserved */ 123 } ccu_sys_pwroff_gate_reg0250_t; 124 125 typedef struct ccu_ana_pwroff_gate_reg0254 { 126 u32 avcc_a_gate:1; /* bit0, gating the corresponding modules to the 127 * AVCC_A power domain when VDD_SYS power off 128 */ 129 u32 res_vdd_on_ctrl:1; /* bit1 */ 130 u32 reserved0:30; /* bit2, reserved */ 131 } ccu_ana_pwroff_gate_reg0254_t; 132 133 typedef struct ccu_ve_pwroff_gate_reg0258 { 134 u32 poweroff_gate:1; /* bit0, gating the corresponding modules 135 * when VE power off 136 */ 137 u32 reserved0:31; /* bit1, reserved */ 138 } ccu_ve_pwroff_gate_reg0258_t; 139 140 typedef struct ccu_sys_pwr_rst_reg0260 { 141 u32 module_reset : 1; /* bit0, VDD_SYS power domain modules should be 142 * reset before VDD_SYS power on 143 */ 144 u32 reserved0 : 31; /* bit1, reserved */ 145 } ccu_sys_pwr_rst_reg0260_t; 146 147 typedef struct ccu_prcm_sec_sw_cfg_reg0290 { 148 u32 cpus_clk_sec:1; /* bit0, cpus clk relevant register's security */ 149 u32 pll_sec:1; /* bit1, pll ctrl relevant register's security */ 150 u32 power_sec:1; /* bit2, power relevant register' security */ 151 u32 reserved0:29; /* bit3, reserved */ 152 } ccu_prcm_sec_sw_cfg_reg0290_t; 153 154 typedef struct ccu_reg_list { 155 volatile ccu_cpus_clk_cfg_reg0000_t cpus_clk_cfg; /* 0x0000 */ 156 volatile u32 reserved0[2]; /* 0x0004 */ 157 volatile ccu_apbs1_cfg_reg000c_t apbs1_cfg; /* 0x000c */ 158 volatile ccu_apbs2_cfg_reg0010_t apbs2_cfg; /* 0x0010 */ 159 volatile u32 reserved1[47]; /* 0x0014 - 0x0D0 */ 160 volatile ccu_mod_lpsd_clk_reg_t r_lpsd; /* 0x00D0 */ 161 volatile u32 reserved2[18]; /* 0x00D4- 0x011c */ 162 163 volatile ccu_mod_gate_reset_reg_t r_timer; /* 0x011c */ 164 volatile u32 reserved3[3]; /* 0x0120 - 0x0128 */ 165 volatile ccu_mod_gate_reset_reg_t r_twd; /* 0x012c */ 166 volatile u32 reserved4[3]; /* 0x0130 - 0x0138 */ 167 volatile ccu_mod_gate_reset_reg_t r_pwm; /* 0x013c */ 168 169 volatile ccu_mod_audio_clk_reg_t r_ac_adc; /* 0x0140 */ 170 volatile ccu_mod_audio_clk_reg_t r_ac_dac; /* 0x0144 */ 171 volatile u32 reserved5[1]; /* 0x0148 */ 172 volatile ccu_mod_gate_reset_reg_t r_ac_gate; /* 0x014c */ 173 volatile ccu_mod_audio_clk_reg_t r_dmic; /* 0x0150 */ 174 volatile u32 reserved6[2]; /* 0x0154 - 0x0158 */ 175 volatile ccu_mod_gate_reset_reg_t r_dmic_gate; /* 0x015C */ 176 volatile u32 reserved7[4]; /* 0x0160 - 0x016C */ 177 volatile ccu_mod_audio_clk_reg_t r_i2s0; /* 0x0170 */ 178 volatile ccu_mod_audio_clk_reg_t r_i2s0_asrc; /* 0x0174 */ 179 volatile ccu_mod_audio_clk_reg_t r_i2s1; /* 0x0178 */ 180 volatile u32 reserved8[4]; /* 0x017C - 0x0188 */ 181 182 volatile ccu_mod_gate_reset_reg_t r_uart; /* 0x018c */ 183 volatile u32 reserved9[3]; /* 0x0190 - 0x0198 */ 184 volatile ccu_mod_gate_reset_reg_t r_twi; /* 0x019c */ 185 volatile u32 reserved10[7]; /* 0x01a0 - 0x01b8 */ 186 volatile ccu_mod_gate_reset_reg_t r_rsb; /* 0x01bc */ 187 volatile ccu_mod_clk_reg_t r_ir_clk; /* 0x01c0 */ 188 volatile u32 reserved11[2]; /* 0x01c4 - 0x01c8 */ 189 volatile ccu_mod_gate_reset_reg_t r_ir; /* 0x01cc */ 190 volatile u32 reserved12[4]; /* 0x01d0 - 0x01dc */ 191 /* FIXME: no owc register */ 192 volatile ccu_mod_clk_reg_t r_owc_clk; /* 0x01e0 */ 193 volatile u32 reserved13[2]; /* 0x01e4 - 0x01e8 */ 194 volatile ccu_mod_gate_reset_reg_t r_owc; /* 0x01ec */ 195 volatile u32 reserved14[7]; /* 0x01f0 - 0x0208 */ 196 volatile ccu_mod_gate_reset_reg_t r_rtc; /* 0x020c */ 197 volatile u32 reserved15[12]; /* 0x0210 - 0x023c */ 198 volatile ccu_pll_ctrl_reg0240_t pll_ctrl0; /* 0x0240 */ 199 volatile ccu_pll_ctrl_reg0244_t pll_ctrl1; /* 0x0244 */ 200 volatile u32 reserved16[2]; /* 0x0248 - 0x024c */ 201 volatile ccu_sys_pwroff_gate_reg0250_t sys_pwroff_gate;/* 0x0250 */ 202 volatile ccu_ana_pwroff_gate_reg0254_t ana_pwroff_gate;/* 0x0254 */ 203 volatile ccu_ve_pwroff_gate_reg0258_t ve_pwroff_gate; /* 0x0258 */ 204 volatile u32 reserved17; /* 0x025c */ 205 volatile ccu_sys_pwr_rst_reg0260_t sys_pwr_rst; /* 0x0260 */ 206 volatile u32 reserved18[3]; /* 0x0264 - 0x26c */ 207 volatile u32 ram_cfg; /* 0x0270 */ 208 volatile u32 ram_test; /* 0x0274 */ 209 volatile u32 reserved19[6]; /* 0x0278 - 0x028c */ 210 volatile ccu_prcm_sec_sw_cfg_reg0290_t prcm_sec_sw_cfg;/* 0x0290 */ 211 volatile u32 reserved20[87]; /* 0x0294 - 0x03ec */ 212 volatile u32 prcm_version; /* 0x03f0 */ 213 } ccu_reg_list_t; 214 215 /* refer to ccmu spec register description */ 216 typedef struct ccu_pll_c0_cpux_reg0000 { 217 volatile u32 factor_m:2; /* bit0, PLL1 Factor_M */ 218 volatile u32 reserved3:6; /* bit2, reserved */ 219 volatile u32 factor_n:8; /* bit8, PLL1 Factor_N */ 220 volatile u32 factor_p:2; /* bit16, PLL1 Factor_P */ 221 volatile u32 reserved2:6; /* bit18, reserved */ 222 volatile u32 lock_time:3; /* bit24, lock time:freq scaling step */ 223 volatile u32 reserved1:1; /* bit27, reserved */ 224 volatile u32 lock_st:1; /* bit28, 0-unlocked, 1-locked(PLL has been stable) */ 225 volatile u32 lock_en:1; /* bit29, 0-disable lock, 1-enable lock */ 226 volatile u32 reserved0:1; /* bit30, reserved */ 227 volatile u32 enable:1; /* bit31, 0-disable, 1-enable, (24Mhz*N*K)/(M) */ 228 } ccu_pll_c0_cpux_reg0000_t; 229 230 typedef struct ccu_pll_ddr0_reg0010 { 231 volatile u32 factor_m0:1; /* bit0, factor_m0 */ 232 volatile u32 factor_m1:1; /* bit1, factor_m1 */ 233 volatile u32 reserved3:6; /* bit2, reserved */ 234 volatile u32 factor_n:8; /* bit8, factor_n */ 235 volatile u32 reserved2:8; /* bit16, reserved */ 236 volatile u32 sdm_en:1; /* bit24, sdm enable */ 237 volatile u32 reserved1:3; /* bit25, reserved */ 238 volatile u32 lock_st:1; /* bit28, lock state */ 239 volatile u32 lock_en:1; /* bit29, lock enable */ 240 volatile u32 reserved0:1; /* bit30, reserved */ 241 volatile u32 enable:1; /* bit31, 0-disable, 1-enable, (24Mhz*N*K)/(M) */ 242 } ccu_pll_ddr0_reg0010_t; 243 244 typedef struct ccu_pll_periph_reg0010 { 245 volatile u32 reserved0:1; 246 volatile u32 factor_m:1; 247 volatile u32 reserved1:6; 248 volatile u32 factor_n:8; 249 volatile u32 factor_p0:3; 250 volatile u32 reserved2:1; 251 volatile u32 factor_p1:3; 252 volatile u32 reserved3:1; 253 volatile u32 sdm_en:1; 254 volatile u32 reserved4:2; 255 volatile u32 output_en:1; 256 volatile u32 lock:1; 257 volatile u32 lock_en:1; 258 volatile u32 reserved5:1; 259 volatile u32 enable:1; 260 } ccu_pll_periph_reg0010_t; 261 262 typedef struct ccu_pll_audio0_reg0020 { 263 volatile u32 reserved0:1; 264 volatile u32 factor_m:1; 265 volatile u32 reserved1:6; 266 volatile u32 factor_n:8; 267 volatile u32 factor_p0:3; 268 volatile u32 reserved2:1; 269 volatile u32 factor_p1:3; 270 volatile u32 reserved3:1; 271 volatile u32 sdm_en:1; 272 volatile u32 reserved4:2; 273 volatile u32 output_en:1; 274 volatile u32 lock:1; 275 volatile u32 lock_en:1; 276 volatile u32 reserved5:1; 277 volatile u32 enable:1; 278 } ccu_pll_audio0_reg0020_t; 279 280 typedef struct ccu_pll_periph0_reg0020 { 281 volatile u32 factor_m0:1; /* bit0, factor_m0 */ 282 volatile u32 factor_m1:1; /* bit1, factor_m1 */ 283 volatile u32 reserved2:6; /* bit2, reserved */ 284 volatile u32 factor_n:8; /* bit8, factor_n */ 285 volatile u32 reserved1:12; /* bit16, reserved */ 286 volatile u32 lock_st:1; /* bit28, lock state */ 287 volatile u32 lock_en:1; /* bit29, lock enable */ 288 volatile u32 reserved0:1; /* bit30, reserved */ 289 volatile u32 enable:1; /* bit31, 0-disable, 1-enable, (24Mhz*N*K)/(M) */ 290 } ccu_pll_periph0_reg0020_t; 291 292 typedef struct ccu_pll_periph1_reg0028 { 293 volatile u32 factor_m0:1; /* bit0, factor_m0 */ 294 volatile u32 factor_m1:1; /* bit1, factor_m1 */ 295 volatile u32 reserved2:6; /* bit2, reserved */ 296 volatile u32 factor_n:8; /* bit8, factor_n */ 297 volatile u32 reserved1:12; /* bit16, reserved */ 298 volatile u32 lock_st:1; /* bit28, lock state */ 299 volatile u32 lock_en:1; /* bit29, lock enable */ 300 volatile u32 reserved0:1; /* bit30, reserved */ 301 volatile u32 enable:1; /* bit31, 0-disable, 1-enable, (24Mhz*N*K)/(M) */ 302 } ccu_pll_periph1_reg0028_t; 303 304 typedef struct ccu_pll_audio0_reg { 305 volatile u32 factor_m0:1; /* bit0, factor_m0 */ 306 volatile u32 factor_m1:1; /* bit1, factor_m1 */ 307 volatile u32 reserved3:6; /* bit2, reserved */ 308 volatile u32 factor_n:8; /* bit8, factor_n */ 309 volatile u32 div_p0:3; /* bit16, post div-p0 */ 310 volatile u32 reserved2:1; /* bit19, reserved */ 311 volatile u32 div_p1:3; /* bit20, post div-p1 */ 312 volatile u32 sdm_enable:1; /* bit24, pll sdm enable */ 313 volatile u32 reserved1:2; /* bit25, reserved */ 314 volatile u32 pll_out:1; /* bit27, pll output enable */ 315 volatile u32 lock_st:1; /* bit28, lock state */ 316 volatile u32 lock_en:1; /* bit29, lock enable */ 317 volatile u32 reserved0:1; /* bit30, reserved */ 318 volatile u32 enable:1; /* bit31, 0-disable, 1-enable, 1X:(24Mhz*N*M0/M1)/(P)/4 */ 319 } ccu_pll_audio0_reg_t; 320 321 typedef struct ccu_pll_audio1_reg { 322 volatile u32 factor_m0:1; /* bit0, factor_m0 */ 323 volatile u32 factor_m1:1; /* bit1, factor_m1 */ 324 volatile u32 reserved3:6; /* bit2, reserved */ 325 volatile u32 factor_n:8; /* bit8, factor_n */ 326 volatile u32 div_p:6; /* bit16, post div-p */ 327 volatile u32 reserved2:2; /* bit22, reserved */ 328 volatile u32 sdm_enable:1; /* bit24, pll sdm enable */ 329 volatile u32 reserved1:2; /* bit25, reserved */ 330 volatile u32 pll_out:1; /* bit27, pll output enable */ 331 volatile u32 lock_st:1; /* bit28, lock state */ 332 volatile u32 lock_en:1; /* bit29, lock enable */ 333 volatile u32 reserved0:1; /* bit30, reserved */ 334 volatile u32 enable:1; /* bit31, 0-disable, 1-enable, 1X:(24Mhz*N*M0/M1)/(P)/4 */ 335 } ccu_pll_audio1_reg_t; 336 337 typedef struct ccu_pll_audio0_pat0_reg { 338 volatile u32 wave_bot:17; /* bit0 - bit16, wave bottom */ 339 volatile u32 freq:2; /* bit17 - bit18, frequency */ 340 volatile u32 clk_sel:1; /* bit19, 0:24M, 1:12M, SDM clk select */ 341 volatile u32 wave_step:9; /* bit20 - bit28, wave step */ 342 volatile u32 freq_mode:2; /* bit29 - bit30, Spread frequency mode */ 343 volatile u32 enable:1; /* bit31, 0-disable, 1-enable, Sigma-Delta Pattern Enable */ 344 } ccu_pll_audio0_pat0_reg_t; 345 346 typedef struct ccu_pll_audio1_pat0_reg { 347 volatile u32 wave_bot:17; /* bit0 - bit16, wave bottom */ 348 volatile u32 freq:2; /* bit17 - bit18, frequency */ 349 volatile u32 clk_sel:1; /* bit19, 0:24M, 1:12M, SDM clk select */ 350 volatile u32 wave_step:9; /* bit20 - bit28, wave step */ 351 volatile u32 freq_mode:2; /* bit29 - bit30, Spread frequency mode */ 352 volatile u32 enable:1; /* bit31, 0-disable, 1-enable, Sigma-Delta Pattern Enable */ 353 } ccu_pll_audio1_pat0_reg_t; 354 355 #endif /* __CCU_REGS_H__ */ 356