1 
2 /* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
3 
4  * Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
5  * the the People's Republic of China and other countries.
6  * All Allwinner Technology Co.,Ltd. trademarks are used with permission.
7 
8  * DISCLAIMER
9  * THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
10  * IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
11  * IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
12  * ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
13  * ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
14  * COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
15  * YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY.
16 
17 
18  * THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
19  * PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
20  * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
21  * THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
22  * OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
23  * IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26  * LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
28  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
30  * OF THE POSSIBILITY OF SUCH DAMAGE.
31 
32  */
33 
34 #ifndef __PWM_SUN8IW19_H__
35 #define __PWM_SUN8IW19_H__
36 
37 #include <hal_gpio.h>
38 /*****************************************************************************
39  * define  register offset
40  *****************************************************************************/
41 #define  PWM_BASE           0x0300a000UL
42 
43 #define PWM_PIER            0x00  /*PWM IRQ enable register 0x00*/
44 #define PWM_PISR            0x04  /*PWM IRQ status register 0x04*/
45 #define PWM_CIER            0x10  /*PWM capture IRQ enable register 0x10*/
46 
47 #define PWM_CISR            0X14  /*PWM capture IRQ status register 0X14*/
48 
49 #define PWM_PCCR_BASE       0x20
50 #define PWM_PCCR01          0x20  /*PWM01 clock configuration register*/
51 #define PWM_PCCR23          0x24  /*PWM23 clock configuration register */
52 #define PWM_PCCR45          0x28  /*PWM45 clock configuration register */
53 #define PWM_PCCR67          0x2C  /*PWM67 clock configuration register */
54 #define PWM_PCCR8           0x30  /*PWM8 clock configuration register */
55 
56 #define PWM_PCGR            0X40  /*PWM CLOCK Gating Register  0X40*/
57 
58 #define PWM_PDZCR_BASE      0X60
59 #define PWM_PDZCR01         0X60  /*PWM01 Dead Zone Contol Register 0X60*/
60 #define PWM_PDZCR23         0X64  /*PWM23 Dead Zone Contol Register 0X64*/
61 #define PWM_PDZCR45         0X68  /*PWM45 Dead Zone Contol Register 0X68*/
62 #define PWM_PDZCR67         0X6C  /*PWM67 Dead Zone Contol Register 0X6C*/
63 #define PWM_PDZCR89         0X70  /*PWM89 Dead Zone Contol Register 0X70*/
64 
65 #define PWM_PER             0x80  /*enable register 0x80*/
66 
67 #define PWM_PGR0            0X90  /*PWM Group0 Register 0X90*/
68 #define PWM_PGR1            0X94  /*PWM Group0 Register 0X94*/
69 
70 #define PWM_CER             0xc0  /*PWM Capture Enable Register */
71 
72 #define PWM_PCR             0x0100/*PWM Contorl Register */
73 /* offset: 0x0100+0x0000+N*0x0020 N=0~8 */
74 
75 #define PWM_PPR             0x0104/*PWM Period Register */
76 /* offset: 0x0100+0x00004+N*0x0020 N=0~8 */
77 
78 #define PWM_PCNTR           0x0108/*PWM Counter Register */
79 /* offset: 0x0100+0x0008+N*0x0020 N=0~8 */
80 
81 #define PWM_PPCNTR          0x010C/*PWM Pulse Counter Register */
82 /* offset: 0x0100+0x000c+N*0x0020 N=0~8 */
83 
84 #define PWM_CCR             0x0110/*Capture Control Register */
85 /* offset: 0x0100+0x0010+N*0x0020 N=0~8 */
86 
87 #define PWM_CRLR            0x0114/*Capture RIse Lock Register */
88 /* offset: 0x0100+0x0014+N*0x0020 N=0~8 */
89 
90 #define PWM_CFLR            0x0118/*Capture Control Register */
91 /* offset: 0x0100+0x0018+N*0x0020 N=0~8 */
92 
93 #define PWM_VR              0x03f0/*PWM Version Register */
94 
95 
96 /*****************************************************************************
97  * define  PWM SET
98  *****************************************************************************/
99 #define PWM_CLK_SRC_SHIFT   0x7
100 #define PWM_CLK_SRC_WIDTH   0x2
101 
102 #define PWM_DIV_M_SHIFT     0x0
103 #define PWM_DIV_M_WIDTH     0x4
104 
105 #define PWM_PRESCAL_SHIFT     0x0
106 #define PWM_PRESCAL_WIDTH     0x8
107 
108 #define PWM_ACTIVE_CYCLES_SHIFT     0x0
109 #define PWM_ACTIVE_CYCLES_WIDTH     0x10
110 
111 #define PWM_PERIOD_SHIFT     0x10
112 #define PWM_PERIOD_WIDTH     0x10
113 
114 #define PWM_CLK_GATING_SHIFT    0x0
115 #define PWM_CLK_GATING_WIDTH    0x1
116 
117 #define PWM_EN_CONTROL_SHIFT    0x0
118 #define PWM_EN_CONTORL_WIDTH    0x1
119 
120 #define PWM_ACT_STA_SHIFT     0x8
121 #define PWM_ACT_STA_WIDTH     0x1
122 #define PWM_NUM 10
123 
124 #define SUNXI_PWM_CLK_TYPE HAL_CLK_PERIPH
125 #define SUNXI_PWM_CLK_ID HAL_CLK_PERIPH_PWM
126 #define SUNXI_PWM_RESET_TYPE HAL_SUNXI_RESET
127 #define SUNXI_PWM_RESET_ID 0
128 
129 /*****************************************************************************
130  * define  gpio
131  *****************************************************************************/
132 typedef struct pwm_gpio_t
133 {
134     gpio_pin_t pwm_pin;
135     int pwm_function;
136 } pwm_gpio_t;
137 
138 static pwm_gpio_t pwm_gpio[PWM_NUM] =
139 {
140     {
141         .pwm_pin = GPIO_PD1,
142         .pwm_function = 3,
143     },
144     {
145         .pwm_pin = GPIO_PD2,
146         .pwm_function = 3,
147     },
148     {
149         .pwm_pin = GPIO_PD3,
150         .pwm_function = 3,
151     },
152     {
153         .pwm_pin = GPIO_PD4,
154         .pwm_function = 3,
155     },
156     {
157         .pwm_pin = GPIO_PD5,
158         .pwm_function = 3,
159     },
160     {
161         .pwm_pin = GPIO_PD6,
162         .pwm_function = 3,
163     },
164     {
165         .pwm_pin = GPIO_PD7,
166         .pwm_function = 3,
167     },
168     {
169         .pwm_pin = GPIO_PD8,
170         .pwm_function = 3,
171     },
172     {
173         .pwm_pin = GPIO_PD9,
174         .pwm_function = 3,
175     },
176     {
177         .pwm_pin = GPIO_PD22,
178         .pwm_function = 2,
179     },
180 
181 };
182 
183 
184 #endif /* __PWM-SUN8IW19_H__ */
185 
186 
187