1 /*
2  * Copyright (C) 2020 allwinnertech Ltd.
3  */
4 
5 #include <sunxi_hal_regulator.h>
6 #include <sunxi_hal_regulator_private.h>
7 #include <type.h>
8 
9 #define AXP2101_DCDC_CFG0       (0x80)
10 #define AXP2101_DCDC1_CFG       (0x82)
11 #define AXP2101_DCDC2_CFG       (0x83)
12 #define AXP2101_DCDC3_CFG       (0x84)
13 #define AXP2101_DCDC4_CFG       (0x85)
14 #define AXP2101_DCDC5_CFG       (0x86)
15 #define AXP2101_LDO_EN_CFG0     (0x90)
16 #define AXP2101_LDO_EN_CFG1     (0x91)
17 #define AXP2101_ALDO1_CFG       (0x92)
18 #define AXP2101_ALDO2_CFG       (0x93)
19 #define AXP2101_ALDO3_CFG       (0x94)
20 #define AXP2101_ALDO4_CFG       (0x95)
21 #define AXP2101_BLDO1_CFG       (0x96)
22 #define AXP2101_BLDO2_CFG       (0x97)
23 #define AXP2101_CPUSLD_CFG      (0x98)
24 #define AXP2101_DLDO1_CFG       (0x99)
25 #define AXP2101_DLDO2_CFG       (0x9A)
26 
27 static const struct regulator_linear_range axp2101_dcdc2_ranges[] = {
28     REGULATOR_LINEAR_RANGE(500000, 0x0, 0x46, 10000),
29     REGULATOR_LINEAR_RANGE(1220000, 0x47, 0x57, 20000),
30 };
31 
32 static const struct regulator_linear_range axp2101_dcdc3_ranges[] = {
33     REGULATOR_LINEAR_RANGE(500000, 0x0, 0x46, 10000),
34     REGULATOR_LINEAR_RANGE(1220000, 0x47, 0x57, 20000),
35     REGULATOR_LINEAR_RANGE(1600000, 0x58, 0x6a, 100000),
36 };
37 
38 static const struct regulator_linear_range axp2101_dcdc4_ranges[] = {
39     REGULATOR_LINEAR_RANGE(500000, 0x0, 0x46, 10000),
40     REGULATOR_LINEAR_RANGE(1220000, 0x47, 0x66, 20000),
41 };
42 
43 static const struct regulator_linear_range axp2101_dcdc5_ranges[] = {
44     REGULATOR_LINEAR_RANGE(1400000, 0x0, 0x17, 100000),
45     REGULATOR_LINEAR_RANGE(1200000, 0x19, 0x19, 0),
46 };
47 
48 const struct regulator_desc axp2101_regulators[] = {
49     AXP_DESC(1500, 3400, 100, AXP2101_DCDC1_CFG, 0x1f,
50          AXP2101_DCDC_CFG0, BIT(0)),
51     AXP_DESC_RANGES(axp2101_dcdc2_ranges, AXP2101_DCDC2_CFG, 0x7f,
52             AXP2101_DCDC_CFG0, BIT(1)),
53     AXP_DESC_RANGES(axp2101_dcdc3_ranges, AXP2101_DCDC3_CFG, 0x7f,
54             AXP2101_DCDC_CFG0, BIT(2)),
55     AXP_DESC_RANGES(axp2101_dcdc4_ranges, AXP2101_DCDC4_CFG, 0x7f,
56             AXP2101_DCDC_CFG0, BIT(3)),
57     AXP_DESC_RANGES(axp2101_dcdc5_ranges, AXP2101_DCDC5_CFG, 0x1f,
58             AXP2101_DCDC_CFG0, BIT(4)),
59     AXP_DESC(500, 3500, 100, AXP2101_ALDO1_CFG, 0x1f, AXP2101_LDO_EN_CFG0,
60          BIT(0)),
61     AXP_DESC(500, 3500, 100, AXP2101_ALDO2_CFG, 0x1f, AXP2101_LDO_EN_CFG0,
62          BIT(1)),
63     AXP_DESC(500, 3500, 100, AXP2101_ALDO3_CFG, 0x1f, AXP2101_LDO_EN_CFG0,
64          BIT(2)),
65     AXP_DESC(500, 3500, 100, AXP2101_ALDO4_CFG, 0x1f, AXP2101_LDO_EN_CFG0,
66          BIT(3)),
67     AXP_DESC(500, 3500, 100, AXP2101_BLDO1_CFG, 0x1f, AXP2101_LDO_EN_CFG0,
68          BIT(4)),
69     AXP_DESC(500, 3500, 100, AXP2101_BLDO2_CFG, 0x1f, AXP2101_LDO_EN_CFG0,
70          BIT(5)),
71     AXP_DESC(500, 3500, 100, AXP2101_DLDO1_CFG, 0x1f, AXP2101_LDO_EN_CFG0,
72          BIT(7)),
73     AXP_DESC(500, 1400, 50, AXP2101_DLDO2_CFG, 0x1f, AXP2101_LDO_EN_CFG1,
74          BIT(0)),
75     AXP_DESC(500, 1400, 50, AXP2101_CPUSLD_CFG, 0x1f, AXP2101_LDO_EN_CFG0,
76          BIT(6)),
77 };
78