1 /*
2 * Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
3 *
4 * Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
5 * the the people's Republic of China and other countries.
6 * All Allwinner Technology Co.,Ltd. trademarks are used with permission.
7 *
8 * DISCLAIMER
9 * THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
10 * IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
11 * IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
12 * ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
13 * ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
14 * COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
15 * YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY.
16 *
17 *
18 * THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
19 * PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
20 * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
21 * THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
22 * OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
23 * IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
30 * OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32 #include <stdio.h>
33 #include <stdlib.h>
34 #include <string.h>
35 #include <ctype.h>
36 #include <getopt.h>
37 #include <sound/snd_core.h>
38 #include <sound/snd_pcm.h>
39 #include <sound/pcm_common.h>
40 #include <aw_common.h>
41 #include <unistd.h>
42 #include "ac108.h"
43
44 //test config
45 #define AC108_KCONTROL_TEST_EN
46 //add to
47 #undef AC108_IDLE_RESET_EN
48
49 //AC108 SDO2/TX2 Enable (SDO1 has be enabled default)
50 #define AC108_SDO2_EN 0
51 #define AC108_DMIC_EN 0 //0:ADC 1:DMIC
52 #undef AC108_IDLE_RESET_EN //reset AC108 when in idle time
53 #define AC108_POWERON_RESET_EN 1 //AC108 poweron soft reset enable
54 //add to
55 #undef AC108_POWERON_RESET_EN
56
57 #define AC108_REGULATOR_NAME "regulator_name"
58 #define AC108_RATES (SNDRV_PCM_RATE_8000_96000 | SNDRV_PCM_RATE_KNOT)
59 #define AC108_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
60 SNDRV_PCM_FMTBIT_S20_3LE | \
61 SNDRV_PCM_FMTBIT_S24_LE | \
62 SNDRV_PCM_FMTBIT_S32_LE)
63
64 struct real_val_to_reg_val {
65 unsigned int real_val;
66 unsigned int reg_val;
67 };
68
69 struct pll_div {
70 unsigned int freq_in;
71 unsigned int freq_out;
72 unsigned int m1;
73 unsigned int m2;
74 unsigned int n;
75 unsigned int k1;
76 unsigned int k2;
77 };
78
79 #if 0
80 static const unsigned char ac108_reg_addr_list[] = {
81 CHIP_AUDIO_RST,
82
83 //Power Control
84 PWR_CTRL1,
85 PWR_CTRL2,
86 PWR_CTRL3,
87 PWR_CTRL4,
88 PWR_CTRL5,
89 PWR_CTRL6,
90 PWR_CTRL7,
91 PWR_CTRL8,
92 PWR_CTRL9,
93
94 //PLL Configure Control
95 PLL_CTRL1,
96 PLL_CTRL2,
97 PLL_CTRL3,
98 PLL_CTRL4,
99 PLL_CTRL5,
100 PLL_CTRL6,
101 PLL_CTRL7,
102 PLL_LOCK_CTRL,
103
104 //System Clock Control
105 SYSCLK_CTRL,
106 MOD_CLK_EN,
107 MOD_RST_CTRL,
108 DSM_CLK_CTRL,
109
110 //I2S Common Control
111 I2S_CTRL,
112 I2S_BCLK_CTRL,
113 I2S_LRCK_CTRL1,
114 I2S_LRCK_CTRL2,
115 I2S_FMT_CTRL1,
116 I2S_FMT_CTRL2,
117 I2S_FMT_CTRL3,
118
119 //I2S TX1 Control
120 I2S_TX1_CTRL1,
121 I2S_TX1_CTRL2,
122 I2S_TX1_CTRL3,
123 I2S_TX1_CHMP_CTRL1,
124 I2S_TX1_CHMP_CTRL2,
125 I2S_TX1_CHMP_CTRL3,
126 I2S_TX1_CHMP_CTRL4,
127
128 //I2S TX2 Control
129 I2S_TX2_CTRL1,
130 I2S_TX2_CTRL2,
131 I2S_TX2_CTRL3,
132 I2S_TX2_CHMP_CTRL1,
133 I2S_TX2_CHMP_CTRL2,
134 I2S_TX2_CHMP_CTRL3,
135 I2S_TX2_CHMP_CTRL4,
136
137 //I2S RX1 Control
138 I2S_RX1_CTRL1,
139 I2S_RX1_CHMP_CTRL1,
140 I2S_RX1_CHMP_CTRL2,
141 I2S_RX1_CHMP_CTRL3,
142 I2S_RX1_CHMP_CTRL4,
143
144 //I2S Loopback Debug
145 I2S_LPB_DEBUG,
146
147 //ADC Common Control
148 ADC_SPRC,
149 ADC_DIG_EN,
150 DMIC_EN,
151 ADC_DSR,
152 ADC_FIR,
153 ADC_DDT_CTRL,
154
155 //HPF Control
156 HPF_EN,
157 HPF_COEF_REGH1,
158 HPF_COEF_REGH2,
159 HPF_COEF_REGL1,
160 HPF_COEF_REGL2,
161 HPF_GAIN_REGH1,
162 HPF_GAIN_REGH2,
163 HPF_GAIN_REGL1,
164 HPF_GAIN_REGL2,
165
166 //ADC Digital Channel Volume Control
167 ADC1_DVOL_CTRL,
168 ADC2_DVOL_CTRL,
169 ADC3_DVOL_CTRL,
170 ADC4_DVOL_CTRL,
171
172 //ADC Digital Mixer Source and Gain Control
173 ADC1_DMIX_SRC,
174 ADC2_DMIX_SRC,
175 ADC3_DMIX_SRC,
176 ADC4_DMIX_SRC,
177
178 //ADC Digital Debug Control
179 ADC_DIG_DEBUG,
180
181 //I2S Pad Drive Control
182 I2S_DAT_PADDRV_CTRL,
183 I2S_CLK_PADDRV_CTRL,
184
185 //Analog PGA Control
186 ANA_PGA1_CTRL,
187 ANA_PGA2_CTRL,
188 ANA_PGA3_CTRL,
189 ANA_PGA4_CTRL,
190
191 //MIC Offset Control
192 MIC_OFFSET_CTRL1,
193 MIC_OFFSET_CTRL2,
194 MIC1_OFFSET_STATU1,
195 MIC1_OFFSET_STATU2,
196 MIC2_OFFSET_STATU1,
197 MIC2_OFFSET_STATU2,
198 MIC3_OFFSET_STATU1,
199 MIC3_OFFSET_STATU2,
200 MIC4_OFFSET_STATU1,
201 MIC4_OFFSET_STATU2,
202
203 //ADC1 Analog Control
204 ANA_ADC1_CTRL1,
205 ANA_ADC1_CTRL2,
206 ANA_ADC1_CTRL3,
207 ANA_ADC1_CTRL4,
208 ANA_ADC1_CTRL5,
209 ANA_ADC1_CTRL6,
210 ANA_ADC1_CTRL7,
211
212 //ADC2 Analog Control
213 ANA_ADC2_CTRL1,
214 ANA_ADC2_CTRL2,
215 ANA_ADC2_CTRL3,
216 ANA_ADC2_CTRL4,
217 ANA_ADC2_CTRL5,
218 ANA_ADC2_CTRL6,
219 ANA_ADC2_CTRL7,
220
221 //ADC3 Analog Control
222 ANA_ADC3_CTRL1,
223 ANA_ADC3_CTRL2,
224 ANA_ADC3_CTRL3,
225 ANA_ADC3_CTRL4,
226 ANA_ADC3_CTRL5,
227 ANA_ADC3_CTRL6,
228 ANA_ADC3_CTRL7,
229
230 //ADC4 Analog Control
231 ANA_ADC4_CTRL1,
232 ANA_ADC4_CTRL2,
233 ANA_ADC4_CTRL3,
234 ANA_ADC4_CTRL4,
235 ANA_ADC4_CTRL5,
236 ANA_ADC4_CTRL6,
237 ANA_ADC4_CTRL7,
238
239 //GPIO Configure
240 GPIO_CFG1,
241 GPIO_CFG2,
242 GPIO_DAT,
243 GPIO_DRV,
244 GPIO_PULL,
245 GPIO_INT_CFG,
246 GPIO_INT_EN,
247 GPIO_INT_STATUS,
248
249 //Misc
250 BGTC_DAT,
251 BGVC_DAT,
252 PRNG_CLK_CTRL,
253 };
254 #endif
255
256 static const struct real_val_to_reg_val ac108_sample_rate[] = {
257 {8000, 0},
258 {11025, 1},
259 {12000, 2},
260 {16000, 3},
261 {22050, 4},
262 {24000, 5},
263 {32000, 6},
264 {44100, 7},
265 {48000, 8},
266 {96000, 9},
267 };
268
269 static const struct real_val_to_reg_val ac108_sample_resolution[] = {
270 {8, 1},
271 {12, 2},
272 {16, 3},
273 {20, 4},
274 {24, 5},
275 {28, 6},
276 {32, 7},
277 };
278
279 static const struct real_val_to_reg_val ac108_bclk_div[] = {
280 {0, 0},
281 {1, 1},
282 {2, 2},
283 {4, 3},
284 {6, 4},
285 {8, 5},
286 {12, 6},
287 {16, 7},
288 {24, 8},
289 {32, 9},
290 {48, 10},
291 {64, 11},
292 {96, 12},
293 {128, 13},
294 {176, 14},
295 {192, 15},
296 };
297
298 //FOUT =(FIN * N) / [(M1+1) * (M2+1)*(K1+1)*(K2+1)] ;
299 //M1[0,31], M2[0,1], N[0,1023], K1[0,31], K2[0,1]
300 static const struct pll_div ac108_pll_div[] = {
301 {400000, 24576000, 0, 0, 983, 7, 1}, //<out: 24.575M>
302 {512000, 24576000, 0, 0, 960, 9, 1}, //24576000/48
303 {768000, 24576000, 0, 0, 640, 9, 1}, //24576000/32
304 {800000, 24576000, 0, 0, 768, 24, 0},
305 {1024000, 24576000, 0, 0, 480, 9, 1}, //24576000/24
306 {1600000, 24576000, 0, 0, 384, 24, 0},
307 {2048000, 24576000, 0, 0, 240, 9, 1}, //24576000/12
308 {3072000, 24576000, 0, 0, 160, 9, 1}, //24576000/8
309 {4096000, 24576000, 0, 0, 120, 9, 1}, //24576000/6
310 {6000000, 24576000, 4, 0, 512, 24, 0},
311 {12000000, 24576000, 9, 0, 512, 24, 0},
312 {13000000, 24576000, 12, 0, 639, 12, 1}, //<out: 24.577M>
313 {15360000, 24576000, 9, 0, 320, 9, 1},
314 {16000000, 24576000, 9, 0, 384, 24, 0},
315 {19200000, 24576000, 11, 0, 384, 24, 0},
316 {19680000, 24576000, 15, 1, 999, 24, 0}, //<out: 24.575M>
317 {24000000, 24576000, 9, 0, 256, 24, 0},
318
319 {400000, 22579200, 0, 0, 1016, 8, 1}, //<out: 22.5778M>
320 {512000, 22579200, 0, 0, 882, 9, 1},
321 {768000, 22579200, 0, 0, 588, 9, 1},
322 {800000, 22579200, 0, 0, 508, 8, 1}, //<out: 22.5778M>
323 {1024000, 22579200, 0, 0, 441, 9, 1},
324 {1600000, 22579200, 0, 0, 254, 8, 1}, //<out: 22.5778M>
325 {2048000, 22579200, 1, 0, 441, 9, 1},
326 {3072000, 22579200, 2, 0, 441, 9, 1},
327 {4096000, 22579200, 3, 0, 441, 9, 1},
328 {6000000, 22579200, 5, 0, 429, 18, 0}, //<out: 22.5789M>
329 {12000000, 22579200, 11, 0, 429, 18, 0}, //<out: 22.5789M>
330 {13000000, 22579200, 12, 0, 429, 18, 0}, //<out: 22.5789M>
331 {15360000, 22579200, 14, 0, 441, 9, 1},
332 {16000000, 22579200, 24, 0, 882, 24, 0},
333 {19200000, 22579200, 4, 0, 147, 24, 0},
334 {19680000, 22579200, 13, 1, 771, 23, 0}, //<out: 22.5793M>
335 {24000000, 22579200, 24, 0, 588, 24, 0},
336
337 {12288000, 24576000, 9, 0, 400, 9, 1}, //24576000/2
338 {11289600, 22579200, 9, 0, 400, 9, 1}, //22579200/2
339
340 {24576000/1, 24576000, 9, 0, 200, 9, 1}, //24576000
341 {24576000/4, 24576000, 4, 0, 400, 9, 1}, //6144000
342 {24576000/16, 24576000, 0, 0, 320, 9, 1}, //1536000
343 {24576000/64, 24576000, 0, 0, 640, 4, 1}, //384000
344 {24576000/96, 24576000, 0, 0, 960, 4, 1}, //256000
345 {24576000/128, 24576000, 0, 0, 512, 1, 1}, //192000
346 {24576000/176, 24576000, 0, 0, 880, 4, 0}, //140000
347 {24576000/192, 24576000, 0, 0, 960, 4, 0}, //128000
348
349 {22579200/1, 22579200, 9, 0, 200, 9, 1}, //22579200
350 {22579200/4, 22579200, 4, 0, 400, 9, 1}, //5644800
351 {22579200/16, 22579200, 0, 0, 320, 9, 1}, //1411200
352 {22579200/64, 22579200, 0, 0, 640, 4, 1}, //352800
353 {22579200/96, 22579200, 0, 0, 960, 4, 1}, //235200
354 {22579200/128, 22579200, 0, 0, 512, 1, 1}, //176400
355 {22579200/176, 22579200, 0, 0, 880, 4, 0}, //128290
356 {22579200/192, 22579200, 0, 0, 960, 4, 0}, //117600
357
358 {22579200/6, 22579200, 2, 0, 360, 9, 1}, //3763200
359 {22579200/8, 22579200, 0, 0, 160, 9, 1}, //2822400
360 {22579200/12, 22579200, 0, 0, 240, 9, 1}, //1881600
361 {22579200/24, 22579200, 0, 0, 480, 9, 1}, //940800
362 {22579200/32, 22579200, 0, 0, 640, 9, 1}, //705600
363 {22579200/48, 22579200, 0, 0, 960, 9, 1}, //470400
364 };
365
ac108_init_i2c_device(twi_port_t port)366 static twi_status_t ac108_init_i2c_device(twi_port_t port)
367 {
368 twi_status_t ret = 0;
369
370 ret = hal_twi_init(port);
371 if (ret != TWI_STATUS_OK) {
372 snd_err("init i2c err ret=%d.\n", ret);
373 return ret;
374 }
375
376 return TWI_STATUS_OK;
377 }
378
ac108_deinit_i2c_device(twi_port_t port)379 static twi_status_t ac108_deinit_i2c_device(twi_port_t port)
380 {
381 twi_status_t ret = 0;
382
383 ret = hal_twi_uninit(port);
384 if (ret != TWI_STATUS_OK) {
385 snd_err("init i2c err ret=%d.\n", ret);
386 return ret;
387 }
388
389 return TWI_STATUS_OK;
390 }
391
ac108_read(struct twi_device * twi_dev,unsigned char reg,unsigned char * rt_value)392 static twi_status_t ac108_read(struct twi_device *twi_dev,
393 unsigned char reg, unsigned char *rt_value)
394 {
395 twi_status_t ret;
396
397 hal_twi_control(twi_dev->bus, I2C_SLAVE, &twi_dev->addr);
398 ret = hal_twi_read(twi_dev->bus, reg, rt_value, 1);
399 if (ret != TWI_STATUS_OK) {
400 snd_err("error = %d [REG-0x%02x]\n", ret, reg);
401 return ret;
402 }
403
404 return TWI_STATUS_OK;
405 }
406
ac108_write(struct twi_device * twi_dev,unsigned char reg,unsigned char value)407 static int ac108_write(struct twi_device *twi_dev,
408 unsigned char reg, unsigned char value)
409 {
410 twi_status_t ret;
411 twi_msg_t msg;
412 unsigned char buf[2] = {reg, value};
413
414 msg.flags = 0;
415 msg.addr = twi_dev->addr;
416 msg.len = 2;
417 msg.buf = buf;
418
419 ret = hal_twi_control(twi_dev->bus, I2C_RDWR, &msg);
420 if (ret != TWI_STATUS_OK) {
421 snd_err("error = %d [REG-0x%02x]\n", ret, reg);
422 return ret;
423 }
424
425 return TWI_STATUS_OK;
426 }
427
ac108_update_bits(struct twi_device * twi_dev,unsigned char reg,unsigned char mask,unsigned char value)428 static int ac108_update_bits(struct twi_device *twi_dev,
429 unsigned char reg, unsigned char mask, unsigned char value)
430 {
431 unsigned char val_old = 0;
432 unsigned char val_new = 0;
433
434 ac108_read(twi_dev, reg, &val_old);
435 val_new = (val_old & ~mask) | (value & mask);
436 if (val_new != val_old)
437 ac108_write(twi_dev, reg, val_new);
438
439 return 0;
440 }
441
ac108_multi_chips_write(struct ac108_priv * ac108,unsigned char reg,unsigned char value)442 static int ac108_multi_chips_write(struct ac108_priv *ac108,
443 unsigned char reg, unsigned char value)
444 {
445 unsigned char i;
446
447 for (i = 0; i < ac108->param.chip_num; i++)
448 ac108_write(&(ac108->param.twi_dev[i]), reg, value);
449
450 return 0;
451 }
452
ac108_multi_chips_update_bits(struct ac108_priv * ac108,unsigned char reg,unsigned char mask,unsigned char value)453 static int ac108_multi_chips_update_bits(struct ac108_priv *ac108,
454 unsigned char reg, unsigned char mask, unsigned char value)
455 {
456 unsigned char i;
457
458 for (i = 0; i < ac108->param.chip_num; i++)
459 ac108_update_bits(&(ac108->param.twi_dev[i]), reg, mask, value);
460
461 return 0;
462 }
463
464 #ifdef AC108_KCONTROL_TEST_EN
465 /* ac108 mixer controls define */
466 static const char * const adc_digital_src_mux[] = {
467 "ADC1_Switch", "ADC2_Switch", "ADC3_Switch", "ADC4_Switch",
468 };
469
470 static const char * const adc12_dmic1_src_mux[] = {
471 "ADC12_Switch", "DMIC1_Switch",
472 };
473
474 static const char * const adc34_dmic2_src_mux[] = {
475 "ADC34_Switch", "DMIC2_Switch",
476 };
477
478 static const char * const i2s_tx1ch_map_mux[] = {
479 "ADC1_Sample_Switch", "ADC2_Sample_Switch",
480 "ADC3_Sample_Switch", "ADC4_Sample_Switch",
481 };
482
ac108_ctl_enum_value_get(struct snd_kcontrol * kcontrol,struct snd_ctl_info * info)483 static int ac108_ctl_enum_value_get(struct snd_kcontrol *kcontrol,
484 struct snd_ctl_info *info)
485 {
486 unsigned int val = 0;
487
488 if (kcontrol->type != SND_CTL_ELEM_TYPE_ENUMERATED) {
489 snd_err("invalid kcontrol type = %d.\n", kcontrol->type);
490 return -EINVAL;
491 }
492
493 if (kcontrol->private_data_type == SND_MODULE_CODEC) {
494 struct snd_codec *codec = kcontrol->private_data;
495 struct ac108_priv *ac108 = codec->private_data;
496 struct ac108_param *param = &ac108->param;
497 ac108_read(¶m->twi_dev[0], kcontrol->reg, (unsigned char *)&val);
498 } else {
499 snd_err("%s invalid kcontrol data type = %d.\n", __func__,
500 kcontrol->private_data_type);
501 }
502
503 snd_kcontrol_to_snd_ctl_info(kcontrol, info, val);
504
505 return 0;
506 }
507
ac108_ctl_enum_value_set(struct snd_kcontrol * kcontrol,unsigned long val)508 static int ac108_ctl_enum_value_set(struct snd_kcontrol *kcontrol, unsigned long val)
509 {
510 if (kcontrol->type != SND_CTL_ELEM_TYPE_ENUMERATED) {
511 snd_err("invalid kcontrol type = %d.\n", kcontrol->type);
512 return -EINVAL;
513 }
514
515 if (val >= kcontrol->items) {
516 snd_err("invalid kcontrol items = %ld.\n", val);
517 return -EINVAL;
518 }
519
520 if (kcontrol->private_data_type == SND_MODULE_CODEC) {
521 struct snd_codec *codec = kcontrol->private_data;
522 struct ac108_priv *ac108 = codec->private_data;
523 struct ac108_param *param = &ac108->param;
524 ac108_update_bits(¶m->twi_dev[0], kcontrol->reg,
525 (kcontrol->mask << kcontrol->shift),
526 ((unsigned int)val << kcontrol->shift));
527 } else {
528 snd_err("invalid kcontrol data type = %d.\n",
529 kcontrol->private_data_type);
530 return -EINVAL;
531 }
532 kcontrol->value = val & kcontrol->mask;
533
534 snd_info("mask:0x%x, shift:%d, value:0x%x\n",
535 kcontrol->mask, kcontrol->shift, kcontrol->value);
536
537 return 0;
538 }
539
ac108_ctl_value_get(struct snd_kcontrol * kcontrol,struct snd_ctl_info * info)540 static int ac108_ctl_value_get(struct snd_kcontrol *kcontrol,
541 struct snd_ctl_info *info)
542 {
543 unsigned int val = 0;
544 int mask = 0;
545
546 if (kcontrol->type != SND_CTL_ELEM_TYPE_INTEGER) {
547 snd_err("invalid kcontrol type = %d.\n", kcontrol->type);
548 return -EINVAL;
549 }
550
551 if (kcontrol->private_data_type == SND_MODULE_CODEC) {
552 struct snd_codec *codec = kcontrol->private_data;
553 struct ac108_priv *ac108 = codec->private_data;
554 struct ac108_param *param = &ac108->param;
555 ac108_read(¶m->twi_dev[0], kcontrol->reg, (unsigned char *)&val);
556 } else {
557 snd_err("%s invalid kcontrol data type = %d.\n", __func__,
558 kcontrol->private_data_type);
559 }
560
561 snd_kcontrol_to_snd_ctl_info(kcontrol, info, val);
562
563 return 0;
564 }
565
ac108_ctl_value_set(struct snd_kcontrol * kcontrol,unsigned long val)566 static int ac108_ctl_value_set(struct snd_kcontrol *kcontrol, unsigned long val)
567 {
568 if (kcontrol->type != SND_CTL_ELEM_TYPE_INTEGER) {
569 snd_err("invalid kcontrol type = %d.\n", kcontrol->type);
570 return -EINVAL;
571 }
572
573 if (kcontrol->private_data_type == SND_MODULE_CODEC) {
574 struct snd_codec *codec = kcontrol->private_data;
575 struct ac108_priv *ac108 = codec->private_data;
576 struct ac108_param *param = &ac108->param;
577 ac108_update_bits(¶m->twi_dev[0], kcontrol->reg,
578 (kcontrol->mask << kcontrol->shift),
579 ((unsigned int)val << kcontrol->shift));
580 } else {
581 snd_err("%s invalid kcontrol data type = %d.\n", __func__,
582 kcontrol->private_data_type);
583 }
584 snd_info("mask:0x%x, shitf:%d, value:0x%x\n",
585 kcontrol->mask, kcontrol->shift, val);
586 return 0;
587 }
588
589 static struct snd_kcontrol ac108_codec_controls[] = {
590 //ADC1 DIG MUX
591 SND_CTL_ENUM_VALUE_EXT("ADC1 DIG MUX", ARRAY_SIZE(adc_digital_src_mux),
592 adc_digital_src_mux, ADC_DSR, DIG_ADC1_SRS,
593 SND_CTL_ENUM_AUTO_MASK,
594 ac108_ctl_enum_value_get, ac108_ctl_enum_value_set),
595 //ADC2 DIG MUX
596 SND_CTL_ENUM_VALUE_EXT("ADC2 DIG MUX", ARRAY_SIZE(adc_digital_src_mux),
597 adc_digital_src_mux, ADC_DSR, DIG_ADC2_SRS,
598 SND_CTL_ENUM_AUTO_MASK,
599 ac108_ctl_enum_value_get, ac108_ctl_enum_value_set),
600 //ADC3 DIG MUX
601 SND_CTL_ENUM_VALUE_EXT("ADC3 DIG MUX", ARRAY_SIZE(adc_digital_src_mux),
602 adc_digital_src_mux, ADC_DSR, DIG_ADC3_SRS,
603 SND_CTL_ENUM_AUTO_MASK,
604 ac108_ctl_enum_value_get, ac108_ctl_enum_value_set),
605 //ADC4 DIG MUX
606 SND_CTL_ENUM_VALUE_EXT("ADC4 DIG MUX", ARRAY_SIZE(adc_digital_src_mux),
607 adc_digital_src_mux, ADC_DSR, DIG_ADC4_SRS,
608 SND_CTL_ENUM_AUTO_MASK,
609 ac108_ctl_enum_value_get, ac108_ctl_enum_value_set),
610
611 //ADC12 DMIC1 MUX
612 SND_CTL_ENUM_VALUE_EXT("ADC12 DMIC1 MUX", ARRAY_SIZE(adc12_dmic1_src_mux),
613 adc12_dmic1_src_mux, DMIC_EN, DMIC1_EN,
614 SND_CTL_ENUM_AUTO_MASK,
615 ac108_ctl_enum_value_get, ac108_ctl_enum_value_set),
616 //ADC34 DMIC2 MUX
617 SND_CTL_ENUM_VALUE_EXT("ADC34 DMIC2 MUX", ARRAY_SIZE(adc34_dmic2_src_mux),
618 adc34_dmic2_src_mux, DMIC_EN, DMIC2_EN,
619 SND_CTL_ENUM_AUTO_MASK,
620 ac108_ctl_enum_value_get, ac108_ctl_enum_value_set),
621
622 //ADC1 DIG MIXER
623 SND_CTL_KCONTROL_VALUE_EXT("ADC1 DIG MIXER ADC1 DAT switch",
624 ADC1_DMIX_SRC, ADC1_ADC1_DMXL_SRC, 1, 0,
625 ac108_ctl_value_get, ac108_ctl_value_set),
626 SND_CTL_KCONTROL_VALUE_EXT("ADC1 DIG MIXER ADC2 DAT switch",
627 ADC1_DMIX_SRC, ADC1_ADC2_DMXL_SRC, 1, 0,
628 ac108_ctl_value_get, ac108_ctl_value_set),
629 SND_CTL_KCONTROL_VALUE_EXT("ADC1 DIG MIXER ADC3 DAT switch",
630 ADC1_DMIX_SRC, ADC1_ADC3_DMXL_SRC, 1, 0,
631 ac108_ctl_value_get, ac108_ctl_value_set),
632 SND_CTL_KCONTROL_VALUE_EXT("ADC1 DIG MIXER ADC4 DAT switch",
633 ADC1_DMIX_SRC, ADC1_ADC4_DMXL_SRC, 1, 0,
634 ac108_ctl_value_get, ac108_ctl_value_set),
635 //ADC2 DIG MIXER
636 SND_CTL_KCONTROL_VALUE_EXT("ADC2 DIG MIXER ADC1 DAT switch",
637 ADC2_DMIX_SRC, ADC2_ADC1_DMXL_SRC, 1, 0,
638 ac108_ctl_value_get, ac108_ctl_value_set),
639 SND_CTL_KCONTROL_VALUE_EXT("ADC2 DIG MIXER ADC2 DAT switch",
640 ADC2_DMIX_SRC, ADC2_ADC2_DMXL_SRC, 1, 0,
641 ac108_ctl_value_get, ac108_ctl_value_set),
642 SND_CTL_KCONTROL_VALUE_EXT("ADC2 DIG MIXER ADC3 DAT switch",
643 ADC2_DMIX_SRC, ADC2_ADC3_DMXL_SRC, 1, 0,
644 ac108_ctl_value_get, ac108_ctl_value_set),
645 SND_CTL_KCONTROL_VALUE_EXT("ADC2 DIG MIXER ADC4 DAT switch",
646 ADC2_DMIX_SRC, ADC2_ADC4_DMXL_SRC, 1, 0,
647 ac108_ctl_value_get, ac108_ctl_value_set),
648 //ADC3 DIG MIXER
649 SND_CTL_KCONTROL_VALUE_EXT("ADC3 DIG MIXER ADC1 DAT switch",
650 ADC3_DMIX_SRC, ADC3_ADC1_DMXL_SRC, 1, 0,
651 ac108_ctl_value_get, ac108_ctl_value_set),
652 SND_CTL_KCONTROL_VALUE_EXT("ADC3 DIG MIXER ADC2 DAT switch",
653 ADC3_DMIX_SRC, ADC3_ADC2_DMXL_SRC, 1, 0,
654 ac108_ctl_value_get, ac108_ctl_value_set),
655 SND_CTL_KCONTROL_VALUE_EXT("ADC3 DIG MIXER ADC3 DAT switch",
656 ADC3_DMIX_SRC, ADC3_ADC3_DMXL_SRC, 1, 0,
657 ac108_ctl_value_get, ac108_ctl_value_set),
658 SND_CTL_KCONTROL_VALUE_EXT("ADC3 DIG MIXER ADC4 DAT switch",
659 ADC3_DMIX_SRC, ADC3_ADC4_DMXL_SRC, 1, 0,
660 ac108_ctl_value_get, ac108_ctl_value_set),
661 //ADC4 DIG MIXER
662 SND_CTL_KCONTROL_VALUE_EXT("ADC4 DIG MIXER ADC1 DAT switch",
663 ADC4_DMIX_SRC, ADC4_ADC1_DMXL_SRC, 1, 0,
664 ac108_ctl_value_get, ac108_ctl_value_set),
665 SND_CTL_KCONTROL_VALUE_EXT("ADC4 DIG MIXER ADC2 DAT switch",
666 ADC4_DMIX_SRC, ADC4_ADC2_DMXL_SRC, 1, 0,
667 ac108_ctl_value_get, ac108_ctl_value_set),
668 SND_CTL_KCONTROL_VALUE_EXT("ADC4 DIG MIXER ADC3 DAT switch",
669 ADC4_DMIX_SRC, ADC4_ADC3_DMXL_SRC, 1, 0,
670 ac108_ctl_value_get, ac108_ctl_value_set),
671 SND_CTL_KCONTROL_VALUE_EXT("ADC4 DIG MIXER ADC4 DAT switch",
672 ADC4_DMIX_SRC, ADC4_ADC4_DMXL_SRC, 1, 0,
673 ac108_ctl_value_get, ac108_ctl_value_set),
674
675 //I2S TX1 CH1 MUX
676 SND_CTL_ENUM_VALUE_EXT("I2S TX1 CH1 MUX", ARRAY_SIZE(i2s_tx1ch_map_mux),
677 i2s_tx1ch_map_mux, I2S_TX1_CHMP_CTRL1, TX1_CH1_MAP,
678 SND_CTL_ENUM_AUTO_MASK,
679 ac108_ctl_enum_value_get, ac108_ctl_enum_value_set),
680 //I2S TX1 CH2 MUX
681 SND_CTL_ENUM_VALUE_EXT("I2S TX1 CH2 MUX", ARRAY_SIZE(i2s_tx1ch_map_mux),
682 i2s_tx1ch_map_mux, I2S_TX1_CHMP_CTRL1, TX1_CH2_MAP,
683 SND_CTL_ENUM_AUTO_MASK,
684 ac108_ctl_enum_value_get, ac108_ctl_enum_value_set),
685 //I2S TX1 CH3 MUX
686 SND_CTL_ENUM_VALUE_EXT("I2S TX1 CH3 MUX", ARRAY_SIZE(i2s_tx1ch_map_mux),
687 i2s_tx1ch_map_mux, I2S_TX1_CHMP_CTRL1, TX1_CH3_MAP,
688 SND_CTL_ENUM_AUTO_MASK,
689 ac108_ctl_enum_value_get, ac108_ctl_enum_value_set),
690 //I2S TX1 CH4 MUX
691 SND_CTL_ENUM_VALUE_EXT("I2S TX1 CH4 MUX", ARRAY_SIZE(i2s_tx1ch_map_mux),
692 i2s_tx1ch_map_mux, I2S_TX1_CHMP_CTRL1, TX1_CH4_MAP,
693 SND_CTL_ENUM_AUTO_MASK,
694 ac108_ctl_enum_value_get, ac108_ctl_enum_value_set),
695 };
696 #endif
697
ac108_codec_startup(struct snd_pcm_substream * substream,struct snd_dai * dai)698 static int ac108_codec_startup(struct snd_pcm_substream *substream,
699 struct snd_dai *dai)
700 {
701 struct snd_codec *codec = dai->component;
702 struct ac108_priv *ac108 = codec->private_data;
703 struct ac108_param *param = &ac108->param;
704 int ret = 0;
705
706 snd_print("\n");
707
708 return 0;
709 }
710
ac108_codec_set_pll(struct snd_dai * dai,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)711 static int ac108_codec_set_pll(struct snd_dai *dai, int pll_id, int source,
712 unsigned int freq_in, unsigned int freq_out)
713 {
714 struct snd_codec *codec = dai->component;
715 struct ac108_priv *ac108 = codec->private_data;
716 struct ac108_param *param = &ac108->param;
717 unsigned int i = 0;
718 unsigned int m1 = 0;
719 unsigned int m2 = 0;
720 unsigned int n = 0;
721 unsigned int k1 = 0;
722 unsigned int k2 = 0;
723
724 snd_print("\n");
725 if (freq_out == 0) {
726 snd_err("freq_out is 0.\n");
727 return 0;
728 }
729
730 //default: freq_int == freq_out; pll_id = 0; source = 0;
731 if (freq_in < 128000 || freq_in > 24576000) {
732 snd_err("AC108 PLLCLK source input freq only support [128K,24M],while now %u\n\n", freq_in);
733 return -EINVAL;
734 } else if ((freq_in == 24576000 || freq_in == 22579200) &&
735 pll_id == SYSCLK_SRC_MCLK) {
736 //System Clock Source Select MCLK, SYSCLK Enable
737 snd_print("AC108 don't need to use PLL\n\n");
738 ac108_multi_chips_update_bits(ac108, SYSCLK_CTRL,
739 0x1 << SYSCLK_SRC | 0x1 << SYSCLK_EN,
740 0x0 << SYSCLK_SRC | 0x1 << SYSCLK_EN);
741 return 0; //Don't need to use PLL
742 }
743
744 //PLL Clock Source Select
745 switch (pll_id) {
746 case PLLCLK_SRC_MCLK:
747 snd_print("AC108 PLLCLK input source select MCLK\n");
748 ac108_multi_chips_update_bits(ac108, SYSCLK_CTRL, 0x3 << PLLCLK_SRC,
749 0x0 << PLLCLK_SRC);
750 break;
751 case PLLCLK_SRC_BCLK:
752 snd_print("AC108 PLLCLK input source select BCLK\n");
753 ac108_multi_chips_update_bits(ac108, SYSCLK_CTRL, 0x3 << PLLCLK_SRC,
754 0x1 << PLLCLK_SRC);
755 break;
756 case PLLCLK_SRC_GPIO2:
757 snd_print("AC108 PLLCLK input source select GPIO2\n");
758 ac108_multi_chips_update_bits(ac108, SYSCLK_CTRL, 0x3 << PLLCLK_SRC,
759 0x2 << PLLCLK_SRC);
760 break;
761 case PLLCLK_SRC_GPIO3:
762 snd_print("AC108 PLLCLK input source select GPIO3\n");
763 ac108_multi_chips_update_bits(ac108, SYSCLK_CTRL, 0x3 << PLLCLK_SRC,
764 0x3 << PLLCLK_SRC);
765 break;
766 default:
767 snd_err("AC108 PLLCLK source config error:%d\n", pll_id);
768 return -EINVAL;
769 }
770
771 //FOUT =(FIN * N) / [(M1+1) * (M2+1)*(K1+1)*(K2+1)] ;
772 for (i = 0; i < ARRAY_SIZE(ac108_pll_div); i++) {
773 if (ac108_pll_div[i].freq_in == freq_in &&
774 ac108_pll_div[i].freq_out == freq_out) {
775 m1 = ac108_pll_div[i].m1;
776 m2 = ac108_pll_div[i].m2;
777 n = ac108_pll_div[i].n;
778 k1 = ac108_pll_div[i].k1;
779 k2 = ac108_pll_div[i].k2;
780 snd_print("AC108 PLL freq_in match:%u, freq_out:%u\n",
781 freq_in, freq_out);
782 break;
783 }
784 }
785
786 if (i == ARRAY_SIZE(ac108_pll_div)) {
787 snd_err("AC108 don't match PLLCLK freq_in and freq_out table\n");
788 return -EINVAL;
789 }
790
791 //Config PLL DIV param M1/M2/N/K1/K2
792 ac108_multi_chips_update_bits(ac108, PLL_CTRL2,
793 0x1f << PLL_PREDIV1 | 0x1 << PLL_PREDIV2,
794 m1 << PLL_PREDIV1 | m2 << PLL_PREDIV2);
795 ac108_multi_chips_update_bits(ac108, PLL_CTRL3, 0x3 << PLL_LOOPDIV_MSB,
796 (n >> 8) << PLL_LOOPDIV_MSB);
797 ac108_multi_chips_update_bits(ac108, PLL_CTRL4, 0xff << PLL_LOOPDIV_LSB,
798 (u8)n << PLL_LOOPDIV_LSB);
799 ac108_multi_chips_update_bits(ac108, PLL_CTRL5,
800 (0x1f << PLL_POSTDIV1) | (0x1 << PLL_POSTDIV2),
801 k1 << PLL_POSTDIV1 | (k2 << PLL_POSTDIV2));
802
803 //Config PLL module current
804 //ac108_multi_chips_update_bits(ac108, PLL_CTRL1, 0x7<<PLL_IBIAS, 0x4<<PLL_IBIAS);
805 //ac108_multi_chips_update_bits(ac108, PLL_CTRL6, 0x1f<<PLL_CP, 0xf<<PLL_CP);
806
807 //PLL module enable
808 //PLL CLK lock enable
809 ac108_multi_chips_update_bits(ac108, PLL_LOCK_CTRL, 0x1 << PLL_LOCK_EN,
810 0x1 << PLL_LOCK_EN);
811 //PLL Common voltage Enable, PLL Enable
812 //ac108_multi_chips_update_bits(ac108, PLL_CTRL1,
813 // 0x1 << PLL_EN | 0x1 << PLL_COM_EN,
814 // 0x1<<PLL_EN | 0x1<<PLL_COM_EN);
815
816 //PLLCLK Enable, SYSCLK Enable
817 //0x1<<SYSCLK_SRC
818 ac108_multi_chips_update_bits(ac108, SYSCLK_CTRL,
819 0x1 << PLLCLK_EN | 0x1 << SYSCLK_EN,
820 0x1 << PLLCLK_EN | 0x1 << SYSCLK_EN);
821
822 return 0;
823 }
824
ac108_codec_set_clkdiv(struct snd_dai * dai,int div_id,int div)825 static int ac108_codec_set_clkdiv(struct snd_dai *dai, int div_id, int div)
826 {
827 struct snd_codec *codec = dai->component;
828 struct ac108_priv *ac108 = codec->private_data;
829 struct ac108_param *param = &ac108->param;
830 unsigned int i = 0;
831 unsigned int bclk_div = 0;
832 unsigned int bclk_div_reg_val = 0;
833
834 snd_print("\n");
835 /* default: div_id = 0; */
836 if (param->daudio_master == 4) {
837 /*
838 *daudio_master(val << 12):
839 * 1: SND_SOC_DAIFMT_CBM_CFM(codec clk & FRM master)
840 * 4: SND_SOC_DAIFMT_CBS_CFS(codec clk & FRM slave)
841 */
842 snd_print("AC108 work as Slave mode, don't need to config BCLK_DIV.\n");
843 return 0;
844 }
845
846 /* SND_SOC_DAIFMT_I2S*/
847 switch (param->daudio_format) {
848 case SND_SOC_DAIFMT_DSP_A:
849 case SND_SOC_DAIFMT_DSP_B:
850 bclk_div = div / param->lrck_period;
851 break;
852 case SND_SOC_DAIFMT_I2S:
853 case SND_SOC_DAIFMT_RIGHT_J:
854 case SND_SOC_DAIFMT_LEFT_J:
855 default:
856 bclk_div = div / (2 * param->lrck_period);
857 break;
858 }
859
860 for (i = 0; i < ARRAY_SIZE(ac108_bclk_div); i++) {
861 if (ac108_bclk_div[i].real_val == bclk_div) {
862 bclk_div_reg_val = ac108_bclk_div[i].reg_val;
863 snd_print("AC108 set BCLK_DIV_[%u]\n", bclk_div);
864 break;
865 }
866 }
867
868 if (i == ARRAY_SIZE(ac108_bclk_div)) {
869 snd_err("AC108 don't support BCLK_DIV_[%u]\n", bclk_div);
870 return -EINVAL;
871 }
872
873 //AC108 set BCLK DIV
874 ac108_multi_chips_update_bits(ac108, I2S_BCLK_CTRL, 0xf << BCLKDIV,
875 bclk_div_reg_val << BCLKDIV);
876 return 0;
877 }
878
ac108_codec_set_fmt(struct snd_dai * dai,unsigned int fmt)879 static int ac108_codec_set_fmt(struct snd_dai *dai, unsigned int fmt)
880 {
881 struct snd_codec *codec = dai->component;
882 struct ac108_priv *ac108 = codec->private_data;
883 struct ac108_param *param = &ac108->param;
884 unsigned int i = 0;
885 unsigned char tx_offset = 0;
886 unsigned char i2s_mode = 0;
887 unsigned char lrck_polarity = 0;
888 unsigned char brck_polarity = 0;
889
890 snd_print("\n");
891 //AC108 config Master/Slave mode
892 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
893 case SND_SOC_DAIFMT_CBM_CFM: //AC108 Master
894 snd_print("AC108 set to work as Master\n");
895 //BCLK & LRCK output
896 ac108_update_bits(¶m->twi_dev[0], I2S_CTRL, 0x3 << LRCK_IOEN,
897 0x3 << LRCK_IOEN);
898 break;
899 case SND_SOC_DAIFMT_CBS_CFS: //AC108 Slave
900 snd_print("AC108 set to work as Slave\n");
901 //BCLK & LRCK input
902 ac108_update_bits(¶m->twi_dev[0], I2S_CTRL, 0x3 << LRCK_IOEN,
903 0x0 << LRCK_IOEN);
904 break;
905 default:
906 snd_err("AC108 Master/Slave mode config error:%u\n\n",
907 (fmt & SND_SOC_DAIFMT_MASTER_MASK) >> 12);
908 return -EINVAL;
909 }
910
911 for (i = 0; i < param->chip_num; i++) {
912 /*
913 * multi_chips: only one chip set as Master,
914 * and the others also need to set as Slave
915 */
916 ac108_update_bits(¶m->twi_dev[i], I2S_CTRL, 0x3 << LRCK_IOEN,
917 0x0 << LRCK_IOEN);
918 }
919
920 //AC108 config I2S/LJ/RJ/PCM format
921 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
922 case SND_SOC_DAIFMT_I2S:
923 snd_print("AC108 config I2S format\n");
924 i2s_mode = LEFT_JUSTIFIED_FORMAT;
925 tx_offset = 1;
926 break;
927 case SND_SOC_DAIFMT_RIGHT_J:
928 snd_print("AC108 config RIGHT-JUSTIFIED format\n");
929 i2s_mode = RIGHT_JUSTIFIED_FORMAT;
930 tx_offset = 0;
931 break;
932 case SND_SOC_DAIFMT_LEFT_J:
933 snd_print("AC108 config LEFT-JUSTIFIED format\n");
934 i2s_mode = LEFT_JUSTIFIED_FORMAT;
935 tx_offset = 0;
936 break;
937 case SND_SOC_DAIFMT_DSP_A:
938 snd_print("AC108 config PCM-A format\n");
939 i2s_mode = PCM_FORMAT;
940 tx_offset = 1;
941 break;
942 case SND_SOC_DAIFMT_DSP_B:
943 snd_print("AC108 config PCM-B format\n");
944 i2s_mode = PCM_FORMAT;
945 tx_offset = 0;
946 break;
947 default:
948 snd_err("AC108 I2S format config error:%u\n\n",
949 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
950 return -EINVAL;
951 }
952
953 ac108_multi_chips_update_bits(ac108, I2S_FMT_CTRL1,
954 0x3 << MODE_SEL | 0x1 << TX2_OFFSET | 0x1 << TX1_OFFSET,
955 i2s_mode<<MODE_SEL | tx_offset<<TX2_OFFSET | tx_offset << TX1_OFFSET);
956
957 //AC108 config BCLK&LRCK polarity
958 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
959 case SND_SOC_DAIFMT_NB_NF:
960 snd_print("AC108 config: BCLK_normal,LRCK_normal.\n");
961 brck_polarity = BCLK_NORMAL_DRIVE_N_SAMPLE_P;
962 lrck_polarity = LRCK_LEFT_LOW_RIGHT_HIGH;
963 break;
964 case SND_SOC_DAIFMT_NB_IF:
965 snd_print("AC108 config: BCLK_normal,LRCK_invert.\n");
966 brck_polarity = BCLK_NORMAL_DRIVE_N_SAMPLE_P;
967 lrck_polarity = LRCK_LEFT_HIGH_RIGHT_LOW;
968 break;
969 case SND_SOC_DAIFMT_IB_NF:
970 snd_print("AC108 config: BCLK_invert,LRCK_normal.\n");
971 brck_polarity = BCLK_INVERT_DRIVE_P_SAMPLE_N;
972 lrck_polarity = LRCK_LEFT_LOW_RIGHT_HIGH;
973 break;
974 case SND_SOC_DAIFMT_IB_IF:
975 snd_print("AC108 config: BCLK_invert,LRCK_invert.\n");
976 brck_polarity = BCLK_INVERT_DRIVE_P_SAMPLE_N;
977 lrck_polarity = LRCK_LEFT_HIGH_RIGHT_LOW;
978 break;
979 default:
980 snd_err("AC108 config BCLK/LRCLK polarity error:%u\n",
981 (fmt & SND_SOC_DAIFMT_INV_MASK) >> 8);
982 return -EINVAL;
983 }
984 ac108_multi_chips_update_bits(ac108, I2S_BCLK_CTRL, 0x1<<BCLK_POLARITY,
985 brck_polarity << BCLK_POLARITY);
986 ac108_multi_chips_update_bits(ac108, I2S_LRCK_CTRL1, 0x1<<LRCK_POLARITY,
987 lrck_polarity << LRCK_POLARITY);
988
989 return 0;
990 }
991
ac108_codec_set_pga_gain(struct twi_device * twi_dev,struct ac108_param * param)992 static void ac108_codec_set_pga_gain(struct twi_device *twi_dev, struct ac108_param *param)
993 {
994 unsigned int i;
995
996 snd_print("\n");
997 if (twi_dev->ref_chan.ref_channel != 0x0) {
998 snd_info("ref_cfg.ref_channel:0x%x, set ref_pga_gain:%d\n",
999 twi_dev->ref_chan.ref_channel, twi_dev->ref_chan.ref_pga);
1000 /* set the gain for referenced channels, always used for aec */
1001 for (i = 0; i < 4; i++) {
1002 if ((twi_dev->ref_chan.ref_channel >> i) & 0x1) {
1003 ac108_update_bits(twi_dev, ANA_PGA1_CTRL + i,
1004 0x1F << ADC1_ANALOG_PGA,
1005 twi_dev->ref_chan.ref_pga << ADC1_ANALOG_PGA);
1006 } else
1007 ac108_update_bits(twi_dev, ANA_PGA1_CTRL + i,
1008 0x1F << ADC1_ANALOG_PGA,
1009 param->pga_gain << ADC1_ANALOG_PGA);
1010 }
1011 } else {
1012 for (i = 0; i < 4; i++)
1013 ac108_update_bits(twi_dev, ANA_PGA1_CTRL + i,
1014 0x1F << ADC1_ANALOG_PGA,
1015 param->pga_gain << ADC1_ANALOG_PGA);
1016 }
1017 }
1018
ac108_codec_hw_init(struct twi_device * twi_dev,struct ac108_param * param)1019 static void ac108_codec_hw_init(struct twi_device *twi_dev, struct ac108_param *param)
1020 {
1021 /*** Chip reset ***/
1022 /*0x00=0x12: reset all registers to their default state*/
1023 //ac108_write(twi_dev, CHIP_AUDIO_RST, 0x12);
1024
1025 #if !AC108_DMIC_EN
1026 /*** Analog voltage enable ***/
1027 /*0x06=0x01: Enable Analog LDO*/
1028 ac108_write(twi_dev, PWR_CTRL6, 0x01);
1029 /*
1030 * 0x07=0x9b: VREF faststart Enable,
1031 * Enable VREF @ 3.4V (5V) or 3.1V (3.3V)
1032 * (needed for Analog LDO and MICBIAS)
1033 */
1034 ac108_write(twi_dev, PWR_CTRL7, 0x9b);
1035 /*
1036 * 0x09=0x81: VREFP faststart Enable, Enable VREFP_FASTSTART_ENABLE
1037 * (needed by all audio input channels)
1038 */
1039 ac108_write(twi_dev, PWR_CTRL9, 0x81);
1040 /*
1041 * DSM low power mode enable, Control bias current for
1042 * DSM integrator opamps
1043 */
1044 ac108_write(twi_dev, ANA_ADC3_CTRL7, 0x0b);
1045 #endif
1046 /*** SYSCLK Config ***/
1047 /*SYSCLK Enable*/
1048 ac108_update_bits(twi_dev, SYSCLK_CTRL, 0x1 << SYSCLK_EN, 0x1 << SYSCLK_EN);
1049 /*
1050 * 0x21=0x93: Module clock enable<I2S, ADC digital,
1051 * MIC offset Calibration, ADC analog>
1052 */
1053 ac108_write(twi_dev, MOD_CLK_EN, 0x93);
1054 /*
1055 * 0x22=0x93: Module reset de-asserted
1056 * <I2S, ADC digital, MIC offset Calibration, ADC analog>
1057 */
1058 ac108_write(twi_dev, MOD_RST_CTRL, 0x93);
1059 /*** I2S Common Config ***/
1060 /*SDO1 enable, SDO2 Enable*/
1061 ac108_update_bits(twi_dev, I2S_CTRL, ((0x1 << SDO1_EN) | (0x1 << SDO2_EN)),
1062 ((0x1 << SDO1_EN) | (!!AC108_SDO2_EN << SDO2_EN)));
1063 /*SDO drive data and SDI sample data at the different BCLK edge*/
1064 ac108_update_bits(twi_dev, I2S_BCLK_CTRL, (0x1 << EDGE_TRANSFER),
1065 (0x0 << EDGE_TRANSFER));
1066 ac108_update_bits(twi_dev, I2S_LRCK_CTRL1, 0x3 << LRCK_PERIODH,
1067 (((param->lrck_period - 1) >> 8) << LRCK_PERIODH));
1068
1069 /*
1070 * config LRCK period:
1071 * 16bit * 8ch = 128,
1072 * 32bit * 8ch = 256,
1073 * 32bit *16ch = 512
1074 */
1075 ac108_write(twi_dev, I2S_LRCK_CTRL2, (param->lrck_period - 1) & 0xFF);
1076 /*
1077 * Encoding mode enable, Turn to hi-z state (TDM)
1078 * when not transferring slot
1079 */
1080 ac108_update_bits(twi_dev, I2S_FMT_CTRL1,
1081 0x1 << ENCD_SEL | 0x1 << TX_SLOT_HIZ | 0x1 << TX_STATE,
1082 !!AC108_ENCODING_EN << ENCD_SEL | 0x0 << TX_SLOT_HIZ | 0x1 << TX_STATE);
1083 /* 8/12/16/20/24/28/32bit Slot Width */
1084 ac108_update_bits(twi_dev, I2S_FMT_CTRL2, 0x7 << SLOT_WIDTH_SEL,
1085 (param->slot_width / 4 - 1) << SLOT_WIDTH_SEL);
1086 /*
1087 * 0x36=0x70: TX MSB first, TX2 Mute, Transfer 0 after
1088 * each sample in each slot(sample resolution < slot width),
1089 * LRCK = 1 BCLK width (short frame), Linear PCM Data Mode
1090 */
1091 ac108_write(twi_dev, I2S_FMT_CTRL3, AC108_SDO2_EN ? 0x60 : 0x70);
1092
1093 /*0x3C=0xe4: TX1 CHn Map to CHn adc sample, n=[1,4]*/
1094 ac108_write(twi_dev, I2S_TX1_CHMP_CTRL1, 0xe4);
1095 /*0x3D=0xe4: TX1 CHn Map to CH(n-4) adc sample, n=[5,8]*/
1096 ac108_write(twi_dev, I2S_TX1_CHMP_CTRL2, 0xe4);
1097 /*0x3E=0xe4: TX1 CHn Map to CH(n-8) adc sample, n=[9,12]*/
1098 ac108_write(twi_dev, I2S_TX1_CHMP_CTRL3, 0xe4);
1099 /*0x3F=0xe4: TX1 CHn Map to CH(n-12) adc sample, n=[13,16]*/
1100 ac108_write(twi_dev, I2S_TX1_CHMP_CTRL4, 0xe4);
1101
1102 #if AC108_SDO2_EN
1103 /*
1104 * 0x44=0x4e: TX2 CH1/2 Map to CH3/4 adc sample,
1105 * TX2 CH3/4 Map to CH1/2 adc sample
1106 */
1107 ac108_write(twi_dev, I2S_TX2_CHMP_CTRL1, 0x4e);
1108 /*0x45=0xe4: TX2 CHn Map to CH(n-4) adc sample, n=[5,8]*/
1109 ac108_write(twi_dev, I2S_TX2_CHMP_CTRL2, 0xe4);
1110 /*0x46=0xe4: TX2 CHn Map to CH(n-8) adc sample, n=[9,12]*/
1111 ac108_write(twi_dev, I2S_TX2_CHMP_CTRL3, 0xe4);
1112 /*0x47=0xe4: TX2 CHn Map to CH(n-12) adc sample, n=[13,16]*/
1113 ac108_write(twi_dev, I2S_TX2_CHMP_CTRL4, 0xe4);
1114 #endif
1115
1116 /*** ADC DIG part Config***/
1117 /*0x60=0x03: ADC Sample Rate 16KHz*/
1118 //ac108_write(ADC_SPRC, 0x03);
1119 /*0x61=0x1f: Digital part globe enable, ADCs digital part enable*/
1120 ac108_write(twi_dev, ADC_DIG_EN, 0x1f);
1121 /*0xBB=0x0f: Gating ADCs CLK de-asserted (ADCs CLK Enable)*/
1122 ac108_write(twi_dev, ANA_ADC4_CTRL7, 0x0f);
1123
1124 if (twi_dev->debug_mode) {
1125 /*0x66=0x00: Digital ADCs channel HPF disable*/
1126 ac108_write(twi_dev, HPF_EN, 0x00);
1127 /*
1128 * 0X7F=0x00: ADC pattern select: 0:ADC normal, 1:0x5A5A5A,
1129 * 2:0x123456, 3:0x00, 4~7:I2S RX data
1130 */
1131 ac108_write(twi_dev, ADC_DIG_DEBUG, twi_dev->debug_mode & 0x7);
1132 }
1133
1134 #if !AC108_DMIC_EN
1135 /*** ADCs analog PGA gain Config***/
1136 ac108_codec_set_pga_gain(twi_dev, param);
1137
1138 /*** enable AAF/ADC/PGA and UnMute Config ***/
1139 /*
1140 * 0xA0=0x07: ADC1 AAF & ADC enable, ADC1 PGA enable,
1141 * ADC1 MICBIAS enable and UnMute
1142 */
1143 ac108_write(twi_dev, ANA_ADC1_CTRL1, 0x07);
1144 /*
1145 * 0xA7=0x07: ADC2 AAF & ADC enable, ADC2 PGA enable,
1146 * ADC2 MICBIAS enable and UnMute
1147 */
1148 ac108_write(twi_dev, ANA_ADC2_CTRL1, 0x07);
1149 /*
1150 * 0xAE=0x07: ADC3 AAF & ADC enable, ADC3 PGA enable,
1151 * ADC3 MICBIAS enable and UnMute
1152 */
1153 ac108_write(twi_dev, ANA_ADC3_CTRL1, 0x07);
1154 /*
1155 * 0xB5=0x07: ADC4 AAF & ADC enable, ADC4 PGA enable,
1156 * ADC4 MICBIAS enable and UnMute
1157 */
1158 ac108_write(twi_dev, ANA_ADC4_CTRL1, 0x07);
1159
1160 /*
1161 * delay 50ms to let VREF/VRP faststart powerup stable,
1162 * then disable faststart
1163 */
1164 usleep(50 * 1000);
1165 /* VREF faststart disable */
1166 ac108_update_bits(twi_dev, PWR_CTRL7, 0x1 << VREF_FASTSTART_ENABLE,
1167 0x0 << VREF_FASTSTART_ENABLE);
1168 /*VREFP faststart disable*/
1169 ac108_update_bits(twi_dev, PWR_CTRL9, 0x1 << VREFP_FASTSTART_ENABLE,
1170 0x0 << VREFP_FASTSTART_ENABLE);
1171 #else
1172 /*** DMIC module Enable ***/
1173 /*DMIC1/2 Enable, while ADC DIG source select DMIC1/2*/
1174 ac108_write(twi_dev, DMIC_EN, 0x03);
1175 /*GPIO1 as DMIC1_DAT, GPIO2 as DMIC_CLK*/
1176 ac108_write(twi_dev, GPIO_CFG1, 0xee);
1177 /*GPIO3 as DMIC2_DAT*/
1178 ac108_write(twi_dev, GPIO_CFG2, 0x7e);
1179 #endif
1180 }
1181
ac108_codec_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_dai * dai)1182 static int ac108_codec_hw_params(struct snd_pcm_substream *substream,
1183 struct snd_pcm_hw_params *params, struct snd_dai *dai)
1184 {
1185 struct snd_codec *codec = dai->component;
1186 struct ac108_priv *ac108 = codec->private_data;
1187 struct ac108_param *param = &ac108->param;
1188 int i = 0;
1189 int ret = 0;
1190 unsigned char reg_val = 0;
1191 unsigned short channels = 0;
1192 unsigned short channels_en = 0;
1193 unsigned short sample_resolution = 0;
1194
1195 snd_print("\n");
1196 /* set codec dai fmt */
1197 ret = snd_soc_dai_set_fmt(dai, param->daudio_format
1198 | (param->signal_inversion << SND_SOC_DAIFMT_SIG_SHIFT)
1199 | (param->daudio_master << SND_SOC_DAIFMT_MASTER_SHIFT));
1200 if (ret < 0) {
1201 snd_err("codec_dai set pll failed\n");
1202 return -EINVAL;
1203 }
1204
1205 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1206 snd_print("AC108 not need playback.\n");
1207 return 0;
1208 }
1209
1210 //AC108 hw init
1211 for (i = 0; i < param->chip_num; i++)
1212 ac108_codec_hw_init(¶m->twi_dev[i], param);
1213
1214 //AC108 set sample rate
1215 for (i = 0; i < ARRAY_SIZE(ac108_sample_rate); i++) {
1216 if (ac108_sample_rate[i].real_val ==
1217 params_rate(params) / (AC108_ENCODING_EN ? AC108_ENCODING_CH_NUMS / 2 : 1)) {
1218 ac108_multi_chips_update_bits(ac108, ADC_SPRC,
1219 0xf << ADC_FS_I2S1,
1220 ac108_sample_rate[i].reg_val << ADC_FS_I2S1);
1221 break;
1222 }
1223 }
1224
1225 //AC108 set channels
1226 #if !AC108_SDO2_EN
1227 channels = params_channels(params) *
1228 (AC108_ENCODING_EN ? AC108_ENCODING_CH_NUMS/2 : 1);
1229 for (i = 0; i < (channels + 3) / 4; i++) {
1230 channels_en = (channels >= 4 * (i + 1)) ? 0x000f << (4 * i) :
1231 ((1 << (channels % 4)) - 1) << (4 * i);
1232 ac108_write(¶m->twi_dev[i], I2S_TX1_CTRL1, channels - 1);
1233 ac108_write(¶m->twi_dev[i], I2S_TX1_CTRL2, (unsigned char )channels_en);
1234 ac108_write(¶m->twi_dev[i], I2S_TX1_CTRL3, channels_en >> 8);
1235 }
1236
1237 for (; i < param->chip_num; i++) {
1238 ac108_write(¶m->twi_dev[i], I2S_TX1_CTRL1, 0);
1239 ac108_write(¶m->twi_dev[i], I2S_TX1_CTRL2, 0);
1240 ac108_write(¶m->twi_dev[i], I2S_TX1_CTRL3, 0);
1241 }
1242 #else
1243 channels = params_channels(params);
1244 for (i = 0; i < (channels + 3) / 4; i++) {
1245 //(2 >= 4*(i+1)) ? 0x000f<<(4*i) : ((1<<(2%4))-1)<<(4*i);
1246 channels_en = 0x03;
1247 ac108_write(¶m->twi_dev[i], I2S_TX1_CTRL1, 2 - 1);
1248 ac108_write(¶m->twi_dev[i], I2S_TX1_CTRL2, (u8)channels_en);
1249 ac108_write(¶m->twi_dev[i], I2S_TX1_CTRL3, channels_en >> 8);
1250 }
1251 for (; i < param->chip_num; i++) {
1252 ac108_write(¶m->twi_dev[i], I2S_TX1_CTRL1, 0);
1253 ac108_write(¶m->twi_dev[i], I2S_TX1_CTRL2, 0);
1254 ac108_write(¶m->twi_dev[i], I2S_TX1_CTRL3, 0);
1255 }
1256
1257 for (i = 0; i < (channels + 3) / 4; i++) {
1258 //(2 >= 4*(i+1)) ? 0x000f<<(4*i) : ((1<<(2%4))-1)<<(4*i);
1259 channels_en = 0x03;
1260 ac108_write(¶m->twi_dev[i], I2S_TX2_CTRL1, 2 - 1);
1261 ac108_write(¶m->twi_dev[i], I2S_TX2_CTRL2, (u8)channels_en);
1262 ac108_write(¶m->twi_dev[i], I2S_TX2_CTRL3, channels_en >> 8);
1263 }
1264 for (; i < param->chip_num; i++) {
1265 ac108_write(¶m->twi_dev[i], I2S_TX2_CTRL1, 0);
1266 ac108_write(¶m->twi_dev[i], I2S_TX2_CTRL2, 0);
1267 ac108_write(¶m->twi_dev[i], I2S_TX2_CTRL3, 0);
1268 }
1269 #endif
1270
1271 //AC108 set sample resorution
1272 switch (params_format(params)) {
1273 case SND_PCM_FORMAT_S16_LE:
1274 sample_resolution = 16;
1275 break;
1276 case SND_PCM_FORMAT_S24_LE:
1277 sample_resolution = 24;
1278 break;
1279 case SND_PCM_FORMAT_S32_LE:
1280 sample_resolution = 32;
1281 break;
1282 default:
1283 snd_err("AC108 don't supported the sample resolution: %u\n",
1284 params_format(params));
1285 return -EINVAL;
1286 }
1287
1288 #if 0
1289 //AC108_ENCODING_EN
1290 //TX Encoding mode, SR add 4bits to mark channel number
1291 if ((sample_resolution <= 24) && (sample_resolution != 16))
1292 sample_resolution += 4;
1293 #endif
1294 for (i = 0; i < ARRAY_SIZE(ac108_sample_resolution); i++) {
1295 if (ac108_sample_resolution[i].real_val == sample_resolution) {
1296 ac108_multi_chips_update_bits(ac108, I2S_FMT_CTRL2,
1297 0x7 << SAMPLE_RESOLUTION,
1298 ac108_sample_resolution[i].reg_val << SAMPLE_RESOLUTION);
1299 break;
1300 }
1301 }
1302
1303 ac108_read(¶m->twi_dev[0], SYSCLK_CTRL, ®_val);
1304 if (reg_val & 0x80) {
1305 //PLLCLK Enable
1306 //PLL Common voltage Enable, PLL Enable
1307 ac108_multi_chips_update_bits(ac108, PLL_CTRL1,
1308 0x1 << PLL_EN | 0x1 << PLL_COM_EN,
1309 0x1 << PLL_EN | 0x1 << PLL_COM_EN);
1310 if (!(reg_val & 0x08)) {
1311 //SYSCLK select MCLK
1312 //GPIO4 output Clock 24MHz from DPLL
1313 ac108_multi_chips_update_bits(ac108, GPIO_CFG2,
1314 0xf << GPIO4_SELECT, 0x9 << GPIO4_SELECT);
1315 }
1316 }
1317
1318 return 0;
1319 }
1320
ac108_codec_set_sysclk(struct snd_dai * dai,int clk_id,unsigned int freq,int dir)1321 static int ac108_codec_set_sysclk(struct snd_dai *dai,
1322 int clk_id, unsigned int freq, int dir)
1323 {
1324 struct snd_codec *codec = dai->component;
1325 struct ac108_priv *ac108 = codec->private_data;
1326 struct ac108_param *param = &ac108->param;
1327
1328 snd_print("\n");
1329 //default: clk_id = 0;
1330 switch (clk_id) {
1331 case SYSCLK_SRC_MCLK:
1332 snd_print("AC108 SYSCLK source select MCLK.\n");
1333 //System Clock Source Select MCLK
1334 ac108_multi_chips_update_bits(ac108,
1335 SYSCLK_CTRL, 0x1 << SYSCLK_SRC,
1336 0x0 << SYSCLK_SRC);
1337 break;
1338 case SYSCLK_SRC_PLL:
1339 snd_print("AC108 SYSCLK source select PLL.\n");
1340 //System Clock Source Select PLL
1341 ac108_multi_chips_update_bits(ac108,
1342 SYSCLK_CTRL, 0x1 << SYSCLK_SRC,
1343 0x1 << SYSCLK_SRC);
1344 break;
1345 default:
1346 snd_err("AC108 SYSCLK source config error:%d\n\n", clk_id);
1347 return -EINVAL;
1348 }
1349
1350 //SYSCLK Enable
1351 ac108_multi_chips_update_bits(ac108,
1352 SYSCLK_CTRL, 0x1 << SYSCLK_EN,
1353 0x1 << SYSCLK_EN);
1354 //AC108 TX enable, Globle enable
1355 ac108_multi_chips_update_bits(ac108, I2S_CTRL,
1356 0x1 << TXEN | 0x1 << GEN,
1357 0x1 << TXEN | 0x1 << GEN);
1358 return 0;
1359 }
1360
ac108_codec_prepare(struct snd_pcm_substream * substream,struct snd_dai * dai)1361 static int ac108_codec_prepare(struct snd_pcm_substream *substream,
1362 struct snd_dai *dai)
1363 {
1364 struct snd_codec *codec = dai->component;
1365 struct ac108_priv *ac108 = codec->private_data;
1366 struct ac108_param *param = &ac108->param;
1367
1368 snd_print("\n");
1369 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1370 snd_print("ac108 playback prepare.\n");
1371 } else {
1372 snd_print("ac108 capture prepare.\n");
1373 }
1374 return 0;
1375 }
1376
1377 void ac108_reg_show(void);
ac108_codec_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_dai * dai)1378 static int ac108_codec_trigger(struct snd_pcm_substream *substream,
1379 int cmd, struct snd_dai *dai)
1380 {
1381 struct snd_codec *codec = dai->component;
1382 struct ac108_priv *ac108 = codec->private_data;
1383 struct ac108_param *param = &ac108->param;
1384
1385 snd_print("\n");
1386 switch (cmd) {
1387 case SNDRV_PCM_TRIGGER_START:
1388 case SNDRV_PCM_TRIGGER_RESUME:
1389 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1390 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1391 snd_print("ac108 playback trigger start.\n");
1392 } else {
1393 snd_print("ac108 capture trigger start\n");
1394 }
1395 break;
1396 case SNDRV_PCM_TRIGGER_STOP:
1397 case SNDRV_PCM_TRIGGER_SUSPEND:
1398 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1399 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1400 snd_print("ac108 playback trigger stop.\n");
1401 } else {
1402 snd_print("ac108 capture trigger stop\n");
1403 }
1404 break;
1405 default:
1406 return -EINVAL;
1407 }
1408 return 0;
1409 }
1410
ac108_codec_hw_free(struct snd_pcm_substream * substream,struct snd_dai * dai)1411 static int ac108_codec_hw_free(struct snd_pcm_substream *substream,
1412 struct snd_dai *dai)
1413 {
1414 struct snd_codec *codec = dai->component;
1415 struct ac108_priv *ac108 = codec->private_data;
1416 struct ac108_param *param = &ac108->param;
1417
1418 snd_print("\n");
1419 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1420 snd_print("AC108 playback hw_free.\n");
1421 return 0;
1422 }
1423
1424 //AC108 I2S Globle disable
1425 ac108_multi_chips_update_bits(ac108, I2S_CTRL,
1426 0x1 << GEN, 0x0 << GEN);
1427
1428 #ifdef AC108_IDLE_RESET_EN
1429 snd_print("AC108 reset all register to their default value\n");
1430 ac108_multi_chips_write(ac108, CHIP_AUDIO_RST, 0x12);
1431 #else
1432 //repair PLL version no sync problem && Encoding no DAT
1433 ac108_multi_chips_update_bits(ac108, PLL_CTRL1,
1434 0x1 << PLL_EN | 0x1 << PLL_COM_EN,
1435 0x0 << PLL_EN | 0x0 << PLL_COM_EN);
1436 ac108_multi_chips_update_bits(ac108, MOD_CLK_EN,
1437 0x1 << I2S | 0x1 << ADC_DIGITAL,
1438 0x0<<I2S | 0x0<<ADC_DIGITAL);
1439 ac108_multi_chips_update_bits(ac108, MOD_RST_CTRL,
1440 0x1 << I2S | 0x1 << ADC_DIGITAL,
1441 0x0 << I2S | 0x0 << ADC_DIGITAL);
1442 #endif
1443 return 0;
1444 }
1445
ac108_codec_shutdown(struct snd_pcm_substream * substream,struct snd_dai * dai)1446 static void ac108_codec_shutdown(struct snd_pcm_substream *substream,
1447 struct snd_dai *dai)
1448 {
1449 struct snd_codec *codec = dai->component;
1450 struct ac108_priv *ac108 = codec->private_data;
1451 struct ac108_param *param = &ac108->param;
1452 int ret = 0;
1453 unsigned int i = 0;
1454
1455 snd_print("\n");
1456 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1457 snd_print("AC108 playback shutdown.\n");
1458 } else {
1459 snd_print("AC108 capture shutdown.\n");
1460 }
1461
1462 return;
1463 }
1464
1465 static struct snd_dai_ops ac108_codec_dai_ops = {
1466 .startup = ac108_codec_startup,
1467 .set_sysclk = ac108_codec_set_sysclk,
1468 .set_pll = ac108_codec_set_pll,
1469 .set_clkdiv = ac108_codec_set_clkdiv,
1470 .set_fmt = ac108_codec_set_fmt,
1471 .hw_params = ac108_codec_hw_params,
1472 .prepare = ac108_codec_prepare,
1473 .trigger = ac108_codec_trigger,
1474 .hw_free = ac108_codec_hw_free,
1475 .shutdown = ac108_codec_shutdown,
1476 };
1477
1478 static struct snd_dai ac108_codec_dai[] = {
1479 {
1480 .name = "ac108-codecdai",
1481 .playback = {
1482 .stream_name = "Playback",
1483 .channels_min = 1,
1484 .channels_max = 8,
1485 .rates = SNDRV_PCM_RATE_8000_192000
1486 | SNDRV_PCM_RATE_KNOT,
1487 .formats = SNDRV_PCM_FMTBIT_S16_LE
1488 | SNDRV_PCM_FMTBIT_S24_LE
1489 | SNDRV_PCM_FMTBIT_S32_LE,
1490 .rate_min = 8000,
1491 .rate_max = 48000,
1492 },
1493 .capture = {
1494 .stream_name = "Capture",
1495 .channels_min = 1,
1496 .channels_max = 8,
1497 .rates = SNDRV_PCM_RATE_8000_48000
1498 | SNDRV_PCM_RATE_KNOT,
1499 .formats = SNDRV_PCM_FMTBIT_S16_LE
1500 | SNDRV_PCM_FMTBIT_S24_LE,
1501 .rate_min = 8000,
1502 .rate_max = 48000,
1503 },
1504 .ops = &ac108_codec_dai_ops,
1505 },
1506 };
1507
ac108_codec_probe(struct snd_codec * codec)1508 static int ac108_codec_probe(struct snd_codec *codec)
1509 {
1510 unsigned char read_data = 0x0;
1511
1512 struct ac108_priv *ac108 = NULL;
1513 unsigned int i = 0;
1514 twi_status_t ret = 0;
1515 unsigned char reset_cmd[2] = {0x0, 0x12};
1516 struct ac108_param default_param = {
1517 .chip_num = AC108_CHIP_NUM,
1518 .twi_dev = AC108_CHIP_CFG,
1519 .pga_gain = AC108_PGA_GAIN,
1520 .daudio_master = AC108_DAUDIO_MASTER,
1521 .daudio_format = AC108_DAUDIO_FORMAT,
1522 .signal_inversion = AC108_DAUDIO_SIG_INV,
1523 .lrck_period = AC108_LRCK_PERIOD,
1524 .slot_width = AC108_SLOT_WIDTH,
1525 };
1526
1527 if (!codec->codec_dai) {
1528 snd_err("codec->codec_dai is null.\n");
1529 return -EFAULT;
1530 }
1531
1532 ac108 = snd_malloc(sizeof(struct ac108_priv));
1533 if (!ac108) {
1534 snd_err("no memory\n");
1535 return -ENOMEM;
1536 }
1537
1538 snd_print("codec para init.\n");
1539 codec->private_data = (void *)ac108;
1540 ac108->param = default_param;
1541 ac108->codec = codec;
1542 codec->codec_dai->component = codec;
1543
1544 snd_print("init ac108 i2c port.\n");
1545 ret = ac108_init_i2c_device(ac108->param.twi_dev[i].bus);
1546 if (ret != TWI_STATUS_OK) {
1547 snd_err("init i2c err\n");
1548 ret = -EFAULT;
1549 goto err_twi_init;
1550 }
1551
1552 for (i = 0; i < ac108->param.chip_num; i++) {
1553 hal_twi_control(ac108->param.twi_dev[i].bus, I2C_SLAVE, &default_param.twi_dev[i].addr);
1554 }
1555 snd_print("ac108 codec register finished.\n");
1556
1557 return 0;
1558
1559 err_twi_init:
1560 snd_free(ac108);
1561 return ret;
1562 }
1563
ac108_codec_remove(struct snd_codec * codec)1564 static int ac108_codec_remove(struct snd_codec *codec)
1565 {
1566 struct ac108_priv *ac108 = codec->private_data;
1567 struct ac108_param *param = &ac108->param;
1568 unsigned int i = 0;
1569 int ret = 0;
1570
1571 snd_print("deinit ac108 i2c port.\n");
1572 ret = ac108_deinit_i2c_device(param->twi_dev[i].bus);
1573 if (ret != TWI_STATUS_OK) {
1574 snd_err("i2c deinit port %d failed.\n",
1575 param->twi_dev[i].bus);
1576 }
1577 snd_free(ac108);
1578 codec->private_data = NULL;
1579
1580 return 0;
1581 }
1582
1583 struct snd_codec ac108_codec = {
1584 .name = "ac108-codec",
1585 .codec_dai = ac108_codec_dai,
1586 .codec_dai_num = ARRAY_SIZE(ac108_codec_dai),
1587 .private_data = NULL,
1588 .probe = ac108_codec_probe,
1589 .remove = ac108_codec_remove,
1590 #ifdef AC108_KCONTROL_TEST_EN
1591 .controls = ac108_codec_controls,
1592 .num_controls = ARRAY_SIZE(ac108_codec_controls),
1593 #endif
1594 };
1595
1596 /* for ac108 debug */
ac108_reg_dump_usage(void)1597 void ac108_reg_dump_usage(void)
1598 {
1599 printf("\n\n=========ac108 debug===========\n");
1600 printf("Usage: ac108_reg [option]\n");
1601 printf("\t-l, ac108 dev list\n");
1602 printf("\t-h, tools help\n");
1603 printf("\t-d, ac108 dev addr(hex)\n");
1604 printf("\t-r, ac108 reg addr(hex)\n");
1605 printf("\t-n, ac108 reg read num(hex)\n");
1606 printf("\t-s, ac108 show all regs\n");
1607 printf("\t-w, ac108 write reg val(hex)\n");
1608 printf("\n");
1609 }
1610
ac108_chip_list(void)1611 void ac108_chip_list(void)
1612 {
1613 unsigned int chip_num = AC108_CHIP_NUM;
1614 struct twi_device twi_dev[] = AC108_CHIP_CFG;
1615 int i = 0;
1616
1617 printf("\n\n=========ac108 show ===========\n");
1618 printf("\tac108 dev num:\t%d\n", chip_num);
1619 for (i = 0; i < chip_num; i++)
1620 printf("\t%d i2c%d-0x%02x\n", i, twi_dev[i].bus, twi_dev[i].addr);
1621 printf("===============================\n");
1622 }
1623
ac108_reg_show(void)1624 void ac108_reg_show(void)
1625 {
1626 unsigned int chip_num = AC108_CHIP_NUM;
1627 struct twi_device twi_dev[] = AC108_CHIP_CFG;
1628 unsigned char read_command;
1629 unsigned char read_data[1] = {0x0};
1630 twi_status_t ret = 0;
1631 unsigned int i = 0;
1632 unsigned int j = 0;
1633
1634 for (i = 0; i < chip_num; i++) {
1635 printf("\n=========ac108 chip [i2c%d-0x%02x] ===========\n",
1636 twi_dev[i].bus, twi_dev[i].addr);
1637 for (j = 0; j <= AC108_REG_MAX; j++) {
1638 if (j % 8 == 0)
1639 printf("\n");
1640 read_command = 0x0 + j;
1641 ret = ac108_read(&twi_dev[i], read_command, read_data);
1642 if (ret != TWI_STATUS_OK) {
1643 snd_err("[i2c%d-0x%02x] read [REG-0x%02x,val-0x%02x] ret = %d.\n",
1644 twi_dev[i].bus, twi_dev[i].addr,
1645 read_command, read_data[0], ret);
1646 }
1647 printf("[0x%02x]: 0x%02x ", read_command, read_data[0]);
1648 }
1649 printf("\n=========================================\n");
1650 }
1651 }
1652
cmd_ac108_reg(int argc,char ** argv)1653 int cmd_ac108_reg(int argc, char ** argv)
1654 {
1655 twi_status_t ret = -1;
1656 unsigned int i;
1657 const struct option long_option[] = {
1658 {"help", 0, NULL, 'h'},
1659 {"list", 0, NULL, 'l'},
1660 {"addr", 1, NULL, 'd'},
1661 {"reg", 1, NULL, 'r'},
1662 {"num", 1, NULL, 'n'},
1663 {"show", 0, NULL, 's'},
1664 {"write", 1, NULL, 'w'},
1665 {NULL, 0, NULL, 0},
1666 };
1667 unsigned int chip_num = AC108_CHIP_NUM;
1668 struct twi_device twi_dev[] = AC108_CHIP_CFG;
1669 unsigned char reset_cmd[2] = {0x0, 0x12};
1670 unsigned char write_cmd[2] = {0x0, 0x0};
1671 unsigned char read_cmd[1] = {0x0};
1672 unsigned char read_data[1] = {0x0};
1673 unsigned int num = 1;
1674 unsigned int twi_addr = 0x3b;
1675 bool wr_flag = 0;
1676
1677 while (1) {
1678 int c;
1679
1680 if ((c = getopt_long(argc, argv, "hlsd:r:n:w:", long_option, NULL)) < 0)
1681 break;
1682 switch (c) {
1683 case 'h':
1684 ac108_reg_dump_usage();
1685 goto ac108_reg_exit;
1686 case 'l':
1687 ac108_chip_list();
1688 goto ac108_reg_exit;
1689 case 's':
1690 ac108_reg_show();
1691 goto ac108_reg_exit;
1692 case 'd':
1693 if (isdigit(*optarg)) {
1694 sscanf(optarg, "0x%x", &twi_addr);
1695 //twi_addr = atoi(optarg);
1696 printf("\ntwi_addr slave address is 0x%02x.\n", twi_addr);
1697 } else
1698 fprintf(stderr, "twi addr is not a digital value.\n");
1699 break;
1700 case 'r':
1701 if (isdigit(*optarg)) {
1702 sscanf(optarg, "0x%hhx", &read_cmd[0]);
1703 //read_cmd[0] = atoi(optarg);
1704 write_cmd[0] = read_cmd[0];
1705 printf("\nreg is 0x%02x.\n", read_cmd[0]);
1706 } else
1707 fprintf(stderr, "reg is not a digital value.\n");
1708 break;
1709 case 'n':
1710 if (isdigit(*optarg)) {
1711 sscanf(optarg, "0x%x", &num);
1712 //num = atoi(optarg);
1713 printf("\nnum is %d.\n", num);
1714 } else
1715 fprintf(stderr, "num is not a digital value.\n");
1716 break;
1717 case 'w':
1718 if (isdigit(*optarg)) {
1719 wr_flag = 1;
1720 sscanf(optarg, "0x%hhx", &write_cmd[1]);
1721 //write_cmd[1] = atoi(optarg);
1722 printf("\nwrite val is 0x%02x.\n", write_cmd[1]);
1723 } else
1724 fprintf(stderr, "write val is not a digital value.\n");
1725 break;
1726 default:
1727 fprintf(stderr, "Invalid switch or option needs an argument.\n");
1728 break;
1729 }
1730 }
1731
1732 //checkout i2c port and addr.
1733 for (i = 0; i < chip_num; i++) {
1734 if (twi_addr == twi_dev[i].addr)
1735 break;
1736 }
1737 if (i >= chip_num) {
1738 fprintf(stderr, "the addr is error.\n");
1739 goto ac108_reg_exit;
1740 }
1741 if ((read_cmd[0] > AC108_REG_MAX) ||
1742 (write_cmd[0] > AC108_REG_MAX)) {
1743 fprintf(stderr, "the reg is over 0x%02x error.\n", AC108_REG_MAX);
1744 goto ac108_reg_exit;
1745 }
1746
1747 if (wr_flag) {
1748 ret = ac108_write(&twi_dev[i], write_cmd[0], write_cmd[1]);
1749 if (ret != TWI_STATUS_OK) {
1750 snd_err("write error [REG-0x%02x,val-0x%02x] ret = %d.\n",
1751 write_cmd[0], write_cmd[1], ret);
1752 }
1753 ret = ac108_read(&twi_dev[i], read_cmd[0], read_data);
1754 if (ret != TWI_STATUS_OK) {
1755 snd_err("write error [I2C%d-0x%0x] REG=0x%02x, val=0x%02x] ret = %d.\n",
1756 twi_dev[i].bus, twi_dev[i].addr, read_cmd[0], read_data[0], ret);
1757 goto ac108_reg_exit;
1758 }
1759 if (read_data[0] == write_cmd[1]) {
1760 printf("write success, [I2C%d-0x%0x] REG=0x%02x, val=0x%02x] ret = %d.\n",
1761 twi_dev[i].bus, twi_dev[i].addr, read_cmd[0], read_data[0], ret);
1762 } else {
1763 printf("write val:0x%02x failed, [I2C%d-0x%0x] REG=0x%02x, val=0x%02x] ret = %d.\n",
1764 write_cmd[1], twi_dev[i].bus, twi_dev[i].addr, read_cmd[0], read_data[0], ret);
1765 }
1766 } else {
1767 for (i = 0; i < num; i++) {
1768 ret = ac108_read(&twi_dev[i], read_cmd[0], read_data);
1769 if (ret != TWI_STATUS_OK) {
1770 snd_err("read error [I2C%d-0x%0x] REG=0x%02x, val=0x%02x] ret = %d.\n",
1771 twi_dev[i].bus, twi_dev[i].addr, read_cmd[0], read_data[0], ret);
1772 goto ac108_reg_exit;
1773 } else {
1774 printf("read success. [I2C%d-0x%0x] REG=0x%02x, val=0x%02x].\n",
1775 twi_dev[i].bus, twi_dev[i].addr, read_cmd[0], read_data[0]);
1776 }
1777 }
1778 }
1779
1780 ac108_reg_exit:
1781 return 0;
1782 }
1783 FINSH_FUNCTION_EXPORT_CMD(cmd_ac108_reg, ac108_reg, ac108 regs dump);
1784