1 /* 2 * Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved. 3 * 4 * Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in 5 * the the people's Republic of China and other countries. 6 * All Allwinner Technology Co.,Ltd. trademarks are used with permission. 7 * 8 * DISCLAIMER 9 * THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT. 10 * IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.) 11 * IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN 12 * ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES. 13 * ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS 14 * COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE. 15 * YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY. 16 * 17 * 18 * THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT 19 * PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND, 20 * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING 21 * THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE 22 * OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. 23 * IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 26 * LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 30 * OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 #ifndef _SUN8IW19_CODEC_H 33 #define _SUN8IW19_CODEC_H 34 35 #define SUNXI_CODEC_BASE_ADDR (0x05096000) 36 37 #define SUNXI_DAC_DPC 0x00 38 #define SUNXI_DAC_FIFOC 0x10 39 #define SUNXI_DAC_FIFOS 0x14 40 #define SUNXI_DAC_TXDATA 0X20 41 #define SUNXI_DAC_CNT 0x24 42 #define SUNXI_DAC_DG 0x28 43 44 #define SUNXI_ADC_FIFOC 0x30 45 #define SUNXI_ADC_FIFOS 0x38 46 #define SUNXI_ADC_RXDATA 0x40 47 #define SUNXI_ADC_CNT 0x44 48 #define SUNXI_ADC_DG 0x4C 49 50 #define SUNXI_DAC_DAP_CTL 0xF0 51 #define SUNXI_ADC_DAP_CTL 0xF8 52 53 #define SUNXI_DAC_DRC_HHPFC 0x100 54 #define SUNXI_DAC_DRC_LHPFC 0x104 55 #define SUNXI_DAC_DRC_CTRL 0x108 56 #define SUNXI_DAC_DRC_LPFHAT 0x10C 57 #define SUNXI_DAC_DRC_LPFLAT 0x110 58 #define SUNXI_DAC_DRC_RPFHAT 0x114 59 #define SUNXI_DAC_DRC_RPFLAT 0x118 60 #define SUNXI_DAC_DRC_LPFHRT 0x11C 61 #define SUNXI_DAC_DRC_LPFLRT 0x120 62 #define SUNXI_DAC_DRC_RPFHRT 0x124 63 #define SUNXI_DAC_DRC_RPFLRT 0x128 64 #define SUNXI_DAC_DRC_LRMSHAT 0x12C 65 #define SUNXI_DAC_DRC_LRMSLAT 0x130 66 #define SUNXI_DAC_DRC_RRMSHAT 0x134 67 #define SUNXI_DAC_DRC_RRMSLAT 0x138 68 #define SUNXI_DAC_DRC_HCT 0x13C 69 #define SUNXI_DAC_DRC_LCT 0x140 70 #define SUNXI_DAC_DRC_HKC 0x144 71 #define SUNXI_DAC_DRC_LKC 0x148 72 #define SUNXI_DAC_DRC_HOPC 0x14C 73 #define SUNXI_DAC_DRC_LOPC 0x150 74 #define SUNXI_DAC_DRC_HLT 0x154 75 #define SUNXI_DAC_DRC_LLT 0x158 76 #define SUNXI_DAC_DRC_HKI 0x15C 77 #define SUNXI_DAC_DRC_LKI 0x160 78 #define SUNXI_DAC_DRC_HOPL 0x164 79 #define SUNXI_DAC_DRC_LOPL 0x168 80 #define SUNXI_DAC_DRC_HET 0x16C 81 #define SUNXI_DAC_DRC_LET 0x170 82 #define SUNXI_DAC_DRC_HKE 0x174 83 #define SUNXI_DAC_DRC_LKE 0x178 84 #define SUNXI_DAC_DRC_HOPE 0x17C 85 #define SUNXI_DAC_DRC_LOPE 0x180 86 #define SUNXI_DAC_DRC_HKN 0x184 87 #define SUNXI_DAC_DRC_LKN 0x188 88 #define SUNXI_DAC_DRC_SFHAT 0x18C 89 #define SUNXI_DAC_DRC_SFLAT 0x190 90 #define SUNXI_DAC_DRC_SFHRT 0x194 91 #define SUNXI_DAC_DRC_SFLRT 0x198 92 #define SUNXI_DAC_DRC_MXGHS 0x19C 93 #define SUNXI_DAC_DRC_MXGLS 0x1A0 94 #define SUNXI_DAC_DRC_MNGHS 0x1A4 95 #define SUNXI_DAC_DRC_MNGLS 0x1A8 96 #define SUNXI_DAC_DRC_EPSHC 0x1AC 97 #define SUNXI_DAC_DRC_EPSLC 0x1B0 98 #define SUNXI_DAC_DRC_OPT 0x1B4 99 #define SUNXI_DAC_DRC_HPFHGAIN 0x1B8 100 #define SUNXI_DAC_DRC_HPFLGAIN 0x1BC 101 102 #define SUNXI_ADC_DRC_HHPFC 0x200 103 #define SUNXI_ADC_DRC_LHPFC 0x204 104 #define SUNXI_ADC_DRC_CTRL 0x208 105 #define SUNXI_ADC_DRC_LPFHAT 0x20C 106 #define SUNXI_ADC_DRC_LPFLAT 0x210 107 #define SUNXI_ADC_DRC_RPFHAT 0x214 108 #define SUNXI_ADC_DRC_RPFLAT 0x218 109 #define SUNXI_ADC_DRC_LPFHRT 0x21C 110 #define SUNXI_ADC_DRC_LPFLRT 0x220 111 #define SUNXI_ADC_DRC_RPFHRT 0x224 112 #define SUNXI_ADC_DRC_RPFLRT 0x228 113 #define SUNXI_ADC_DRC_LRMSHAT 0x22C 114 #define SUNXI_ADC_DRC_LRMSLAT 0x230 115 #define SUNXI_ADC_DRC_HCT 0x23C 116 #define SUNXI_ADC_DRC_LCT 0x240 117 #define SUNXI_ADC_DRC_HKC 0x244 118 #define SUNXI_ADC_DRC_LKC 0x248 119 #define SUNXI_ADC_DRC_HOPC 0x24C 120 #define SUNXI_ADC_DRC_LOPC 0x250 121 #define SUNXI_ADC_DRC_HLT 0x254 122 #define SUNXI_ADC_DRC_LLT 0x258 123 #define SUNXI_ADC_DRC_HKI 0x25C 124 #define SUNXI_ADC_DRC_LKI 0x260 125 #define SUNXI_ADC_DRC_HOPL 0x264 126 #define SUNXI_ADC_DRC_LOPL 0x268 127 #define SUNXI_ADC_DRC_HET 0x26C 128 #define SUNXI_ADC_DRC_LET 0x270 129 #define SUNXI_ADC_DRC_HKE 0x274 130 #define SUNXI_ADC_DRC_LKE 0x278 131 #define SUNXI_ADC_DRC_HOPE 0x27C 132 #define SUNXI_ADC_DRC_LOPE 0x280 133 #define SUNXI_ADC_DRC_HKN 0x284 134 #define SUNXI_ADC_DRC_LKN 0x288 135 #define SUNXI_ADC_DRC_SFHAT 0x28C 136 #define SUNXI_ADC_DRC_SFLAT 0x290 137 #define SUNXI_ADC_DRC_SFHRT 0x294 138 #define SUNXI_ADC_DRC_SFLRT 0x298 139 #define SUNXI_ADC_DRC_MXGHS 0x29C 140 #define SUNXI_ADC_DRC_MXGLS 0x2A0 141 #define SUNXI_ADC_DRC_MNGHS 0x2A4 142 #define SUNXI_ADC_DRC_MNGLS 0x2A8 143 #define SUNXI_ADC_DRC_EPSHC 0x2AC 144 #define SUNXI_ADC_DRC_EPSLC 0x2B0 145 #define SUNXI_ADC_DRC_OPT 0x2B4 146 #define SUNXI_ADC_DRC_HPFHGAIN 0x2B8 147 #define SUNXI_ADC_DRC_HPFLGAIN 0x2BC 148 149 #define SUNXI_AC_VERSION 0x2C0 150 151 /* Analog register base - Digital register base */ 152 /*SUNXI_PR_CFG is to tear the acreg and dcreg, it is of no real meaning*/ 153 #define SUNXI_PR_CFG (0x300) 154 #define SUNXI_ADCL_ANA_CTL (SUNXI_PR_CFG + 0x00) 155 #define SUNXI_DAC_ANA_CTL (SUNXI_PR_CFG + 0x10) 156 #define SUNXI_MICBIAS_ANA_CTL (SUNXI_PR_CFG + 0x18) 157 #define SUNXI_BIAS_ANA_CTL (SUNXI_PR_CFG + 0x20) 158 159 /* SUNXI_DAC_DPC:0x00 */ 160 #define EN_DAC 31 161 #define MODQU 25 162 #define DWA_EN 24 163 #define HPF_EN 18 164 #define DVOL 12 165 #define DAC_HUB_EN 0 166 167 /* SUNXI_DAC_FIFOC:0x10 */ 168 #define DAC_FS 29 169 #define FIR_VER 28 170 #define SEND_LASAT 26 171 #define FIFO_MODE 24 172 #define DAC_DRQ_CLR_CNT 21 173 #define TX_TRIG_LEVEL 8 174 #define DAC_MONO_EN 6 175 #define TX_SAMPLE_BITS 5 176 #define DAC_DRQ_EN 4 177 #define DAC_IRQ_EN 3 178 #define FIFO_UNDERRUN_IRQ_EN 2 179 #define FIFO_OVERRUN_IRQ_EN 1 180 #define FIFO_FLUSH 0 181 182 /* SUNXI_DAC_FIFOS:0x14 */ 183 #define TX_EMPTY 23 184 #define DAC_TXE_CNT 8 185 #define DAC_TXE_INT 3 186 #define DAC_TXU_INT 2 187 #define DAC_TXO_INT 1 188 189 /* SUNXI_DAC_DG:0x28 */ 190 #define DAC_MODU_SEL 11 191 #define DAC_PATTERN_SEL 9 192 #define DAC_CODEC_CLK_SEL 8 193 #define DAC_SWP 6 194 #define ADDA_LOOP_MODE 0 195 196 /* SUNXI_ADC_FIFOC:0x30 */ 197 #define ADC_FS 29 198 #define EN_AD 28 199 #define ADCFDT 26 200 #define ADCDFEN 25 201 #define RX_FIFO_MODE 24 202 #define RX_SAMPLE_BITS 16 203 #define ADC_CHAN_SEL 12 204 #define RX_FIFO_TRG_LEVEL 4 205 #define ADC_DRQ_EN 3 206 #define ADC_IRQ_EN 2 207 #define ADC_OVERRUN_IRQ_EN 1 208 #define ADC_FIFO_FLUSH 0 209 210 /* SUNXI_ADC_FIFOS:0x38 */ 211 #define RXA 23 212 #define ADC_RXA_CNT 8 213 #define ADC_RXA_INT 3 214 #define ADC_RXO_INT 1 215 216 /* SUNXI_ADC_DG:0x4C */ 217 #define AD_SWP 24 218 219 /* SUNXI_DAC_DAP_CTL:0xf0 */ 220 #define DDAP_EN 31 221 #define DDAP_DRC_EN 29 222 #define DDAP_HPF_EN 28 223 224 /* SUNXI_ADC_DAP_CTL:0xf8 */ 225 #define ADC_DAP0_EN 31 226 #define ADC_DRC0_EN 29 227 #define ADC_HPF0_EN 28 228 229 /* SUNXI_DAC_DRC_HHPFC : 0x100*/ 230 #define DAC_HHPF_CONF 0 231 232 /* SUNXI_DAC_DRC_LHPFC : 0x104*/ 233 #define DAC_LHPF_CONF 0 234 235 /* SUNXI_DAC_DRC_CTRL : 0x108*/ 236 #define DAC_DRC_DELAY_OUT_STATE 15 237 #define DAC_DRC_SIGNAL_DELAY 8 238 #define DAC_DRC_DELAY_BUF_EN 7 239 #define DAC_DRC_GAIN_MAX_EN 6 240 #define DAC_DRC_GAIN_MIN_EN 5 241 #define DAC_DRC_NOISE_DET_EN 4 242 #define DAC_DRC_SIGNAL_SEL 3 243 #define DAC_DRC_DELAY_EN 2 244 #define DAC_DRC_LT_EN 1 245 #define DAC_DRC_ET_EN 0 246 247 /* SUNXI_ADC_DRC_HHPFC : 0x200*/ 248 #define ADC_HHPF_CONF 0 249 250 /* SUNXI_ADC_DRC_LHPFC : 0x204*/ 251 #define ADC_LHPF_CONF 0 252 253 /* SUNXI_ADC_DRC_CTRL : 0x208*/ 254 #define ADC_DRC_DELAY_OUT_STATE 15 255 #define ADC_DRC_SIGNAL_DELAY 8 256 #define ADC_DRC_DELAY_BUF_EN 7 257 #define ADC_DRC_GAIN_MAX_EN 6 258 #define ADC_DRC_GAIN_MIN_EN 5 259 #define ADC_DRC_NOISE_DET_EN 4 260 #define ADC_DRC_SIGNAL_SEL 3 261 #define ADC_DRC_DELAY_EN 2 262 #define ADC_DRC_LT_EN 1 263 #define ADC_DRC_ER_EN 0 264 265 /* SUNXI_ADCL_ANA_CTL: SUNXI_PR_CFG + 0x00 */ 266 #define ADCLEN 31 267 #define MIC1AMPEN 30 268 #define ADC_DITHER_RESET 29 269 #define LINEINLEN 23 270 #define LINEINLG 22 271 #define IOPLINE 20 272 #define PGA_CTRL_RCM 18 273 #define PGA_IN_VCM_CTRL 16 274 #define PGA_GAIN_CTRL 8 275 #define ADCL_IOPAAFL 6 276 #define ADCLIOPSDML1 4 277 #define ADCLIOPSDML2 2 278 #define PGA_IOPMICL 0 279 280 /* SUNXI_DAC_ANA_CTL: SUNXI_PR_CFG + 0x10 */ 281 #define CURRENT_TEST_SELECT 23 282 #define VRA2_IOPVRS 20 283 #define ILINEOUTAMPS 18 284 #define IOPDACS 16 285 #define DACLEN 15 286 #define LINEOUTL_EN 13 287 #define DACLMUTE 12 288 #define LINEOUTLDIFFEN 6 289 #define LINEOUT_VOL 0 290 291 /* SUNXI_MICBIAS_ANA_CTL: SUNXI_PR_CFG + 0x18 */ 292 #define MMICBIASEN 7 293 #define MBIASSEL 5 294 #define MMICBIAS_CHOP_EN 4 295 #define MMICBIAS_CHOP_CLK_SEL 2 296 297 /* SUNXI_BIAS_ANA_CTL: SUNXI_PR_CFG + 0x20 */ 298 #define AC_BIASDATA 0 299 300 #define CODEC_REG_LABEL(constant) {#constant, constant, 0} 301 #define CODEC_REG_LABEL_END {NULL, 0, 0} 302 303 /* SUNXI_CODEC_DAP_ENABLE: Whether to use the adc/dac drc/hpf function */ 304 #define SUNXI_CODEC_DAP_ENABLE 305 306 /* SUNXI_ADC_DAUDIO_SYNC: Whether to enable ADC AEC Drive adaptation */ 307 /* #define SUNXI_ADC_DAUDIO_SYNC */ 308 309 extern int sunxi_codec_get_pcm_trigger_substream_mode(void); 310 extern void sunxi_codec_set_pcm_trigger_substream_mode(int value); 311 extern int sunxi_codec_get_pcm_adc_sync_flag(void); 312 extern void sunxi_codec_set_pcm_adc_sync_flag(int value); 313 extern void sunxi_cpudai_adc_drq_enable(bool enable); 314 315 #endif /* __SUN8IW19_CODEC_H */ 316