1 /* 2 * Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved. 3 * 4 * Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in 5 * the the people's Republic of China and other countries. 6 * All Allwinner Technology Co.,Ltd. trademarks are used with permission. 7 * 8 * DISCLAIMER 9 * THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT. 10 * IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.) 11 * IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN 12 * ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES. 13 * ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS 14 * COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE. 15 * YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY. 16 * 17 * 18 * THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT 19 * PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND, 20 * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING 21 * THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE 22 * OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. 23 * IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 26 * LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 30 * OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 #ifndef __SUN8IW20_DAUDIO_H_ 33 #define __SUN8IW20_DAUDIO_H_ 34 35 #define SUNXI_DAUDIO_BASE (0x02032000) 36 37 #define DAUDIO_NUM_MAX 3 38 39 /*------------------------ CLK CONFIG FOR NORMAL ---------------------------*/ 40 #define SUNXI_DAUDIO_CLK_PLL_AUDIO CLK_PLL_AUDIO0 41 #define SUNXI_DAUDIO_CLK_PLL_AUDIO1 CLK_PLL_AUDIO0_4X 42 #define SUNXI_DAUDIO_CLK_I2S_ASRC CLK_I2S2_ASRC 43 44 #define SUNXI_DAUDIO_CLK_I2S0 CLK_I2S0 45 #define SUNXI_DAUDIO_CLK_BUS_I2S0 CLK_BUS_I2S0 46 #define SUNXI_DAUDIO_CLK_RST_I2S0 RST_BUS_I2S0 47 48 #define SUNXI_DAUDIO_CLK_I2S1 CLK_I2S1 49 #define SUNXI_DAUDIO_CLK_BUS_I2S1 CLK_BUS_I2S1 50 #define SUNXI_DAUDIO_CLK_RST_I2S1 RST_BUS_I2S1 51 52 #define SUNXI_DAUDIO_CLK_I2S2 CLK_I2S2 53 #define SUNXI_DAUDIO_CLK_BUS_I2S2 CLK_BUS_I2S2 54 #define SUNXI_DAUDIO_CLK_RST_I2S2 RST_BUS_I2S2 55 56 #define SUNXI_DAUDIO_CLK_I2S3 0 57 #define SUNXI_DAUDIO_CLK_BUS_I2S3 0 58 #define SUNXI_DAUDIO_CLK_RST_I2S3 0 59 60 /*------------------------ PIN CONFIG FOR NORMAL ---------------------------*/ 61 62 63 64 /*------------------------ PIN CONFIG FOR FPGA VERIFY -----------------------*/ 65 /* daudio0 pin config */ 66 #define DAUDIO0_PIN_MCLK \ 67 {.gpio_pin = GPIOB(29), .mux = 2, .driv_level = GPIO_DRIVING_LEVEL1} 68 #define DAUDIO0_PIN_BCLK \ 69 {.gpio_pin = GPIOB(23), .mux = 2, .driv_level = GPIO_DRIVING_LEVEL1} 70 #define DAUDIO0_PIN_LRCK \ 71 {.gpio_pin = GPIOB(24), .mux = 2, .driv_level = GPIO_DRIVING_LEVEL1} 72 #define DAUDIO0_PIN_DOUT0 \ 73 {.gpio_pin = GPIOB(25), .mux = 2, .driv_level = GPIO_DRIVING_LEVEL1} 74 #define DAUDIO0_PIN_DIN \ 75 {.gpio_pin = GPIOB(22), .mux = 2, .driv_level = GPIO_DRIVING_LEVEL1} 76 77 /* daudio1 pin config */ 78 #define DAUDIO1_PIN_MCLK \ 79 {.gpio_pin = GPIOG(11), .mux = 2, .driv_level = GPIO_DRIVING_LEVEL1} 80 #define DAUDIO1_PIN_BCLK \ 81 {.gpio_pin = GPIOG(13), .mux = 2, .driv_level = GPIO_DRIVING_LEVEL1} 82 #define DAUDIO1_PIN_LRCK \ 83 {.gpio_pin = GPIOG(12), .mux = 2, .driv_level = GPIO_DRIVING_LEVEL1} 84 #define DAUDIO1_PIN_DOUT0 \ 85 {.gpio_pin = GPIOG(15), .mux = 2, .driv_level = GPIO_DRIVING_LEVEL1} 86 #define DAUDIO1_PIN_DIN \ 87 {.gpio_pin = GPIOG(14), .mux = 2, .driv_level = GPIO_DRIVING_LEVEL1} 88 89 /* daudio2 pin config */ 90 #define DAUDIO2_PIN_MCLK \ 91 {.gpio_pin = GPIOB(29), .mux = 4, .driv_level = GPIO_DRIVING_LEVEL1} 92 #define DAUDIO2_PIN_BCLK \ 93 {.gpio_pin = GPIOB(23), .mux = 4, .driv_level = GPIO_DRIVING_LEVEL1} 94 #define DAUDIO2_PIN_LRCK \ 95 {.gpio_pin = GPIOB(24), .mux = 4, .driv_level = GPIO_DRIVING_LEVEL1} 96 #define DAUDIO2_PIN_DOUT0 \ 97 {.gpio_pin = GPIOB(25), .mux = 4, .driv_level = GPIO_DRIVING_LEVEL1} 98 #define DAUDIO2_PIN_DIN \ 99 {.gpio_pin = GPIOB(22), .mux = 4, .driv_level = GPIO_DRIVING_LEVEL1} 100 101 /* 102 * Daudio Params Setting 103 * 104 *daudio_master: 105 * 1: SND_SOC_DAIFMT_CBM_CFM(codec clk & FRM master) use 106 * 2: SND_SOC_DAIFMT_CBS_CFM(codec clk slave & FRM master) not use 107 * 3: SND_SOC_DAIFMT_CBM_CFS(codec clk master & frame slave) not use 108 * 4: SND_SOC_DAIFMT_CBS_CFS(codec clk & FRM slave) use 109 *tdm_config: 110 * 0 is pcm; 1 is i2s 111 *audio_format: 112 * 1:SND_SOC_DAIFMT_I2S(standard i2s format). use 113 * 2:SND_SOC_DAIFMT_RIGHT_J(right justfied format). 114 * 3:SND_SOC_DAIFMT_LEFT_J(left justfied format) 115 * 4:SND_SOC_DAIFMT_DSP_A(pcm. MSB is available on 2nd BCLK rising edge after LRC rising edge). use 116 * 5:SND_SOC_DAIFMT_DSP_B(pcm. MSB is available on 1nd BCLK rising edge after LRC rising edge) 117 *signal_inversion: 118 * 1:SND_SOC_DAIFMT_NB_NF(normal bit clock + frame) use 119 * 2:SND_SOC_DAIFMT_NB_IF(normal BCLK + inv FRM) 120 * 3:SND_SOC_DAIFMT_IB_NF(invert BCLK + nor FRM) use 121 * 4:SND_SOC_DAIFMT_IB_IF(invert BCLK + FRM) 122 *pcm_lrck_period :16/32/64/128/256 123 *msb_lsb_first :0: msb first; 1: lsb first 124 *sign_extend :0: zero pending; 1: sign extend 125 *slot_width_select :8 bit width / 16 bit width / 32 bit width 126 *frametype :0: short frame = 1 clock width; 1: long frame = 2 clock width 127 *mclk_div :0: not output(normal setting this); 128 * :1/2/4/6/8/12/16/24/32/48/64/96/128/176/192: 129 * setting mclk as input clock to external codec, 130 * freq is pll_audio/mclk_div 131 *tx_data_mode :0: 16bit linear PCM; (use) 1: reserved; 132 * :2: 8bit u-law; (no use) 3: 8bit a-law (no use) 133 *rx_data_mode :0: 16bit linear PCM; (use) 1: reserved; 134 * :2: 8bit u-law; (no use) 3: 8bit a-law (no use) 135 */ 136 137 #define DAUDIO0_PARAMS \ 138 {.tdm_num = 0, \ 139 .daudio_master = 4, .audio_format = 1, .signal_inversion = 1, \ 140 .pcm_lrck_period = 128, .slot_width_select = 32, \ 141 .msb_lsb_first = 0, .frametype = 0, \ 142 .tx_data_mode = 0, .rx_data_mode = 0, \ 143 .tdm_config = 1, .mclk_div = 1,\ 144 } 145 146 #define DAUDIO1_PARAMS \ 147 {.tdm_num = 1, \ 148 .daudio_master = 4, .audio_format = 1, .signal_inversion = 1, \ 149 .pcm_lrck_period = 128, .slot_width_select = 32, \ 150 .msb_lsb_first = 1, .frametype = 1, \ 151 .tx_data_mode = 0, .rx_data_mode = 0, \ 152 .tdm_config = 1, .mclk_div = 1,\ 153 } 154 155 #define DAUDIO2_PARAMS \ 156 {.tdm_num = 2, \ 157 .daudio_master = 4, .audio_format = 1, .signal_inversion = 1, \ 158 .pcm_lrck_period = 128, .slot_width_select = 32, \ 159 .msb_lsb_first = 0, .frametype = 0, \ 160 .tx_data_mode = 0, .rx_data_mode = 0, \ 161 .tdm_config = 1, .mclk_div = 1,\ 162 } 163 164 struct daudio_pinctrl daudio0_pinctrl[] = { 165 DAUDIO0_PIN_MCLK, 166 DAUDIO0_PIN_BCLK, 167 DAUDIO0_PIN_LRCK, 168 DAUDIO0_PIN_DOUT0, 169 /* DAUDIO0_PIN_DOUT1, */ 170 DAUDIO0_PIN_DIN, 171 }; 172 173 struct daudio_pinctrl daudio1_pinctrl[] = { 174 DAUDIO1_PIN_MCLK, 175 DAUDIO1_PIN_BCLK, 176 DAUDIO1_PIN_LRCK, 177 DAUDIO1_PIN_DOUT0, 178 /* DAUDIO1_PIN_DOUT1, */ 179 DAUDIO1_PIN_DIN, 180 }; 181 182 struct daudio_pinctrl daudio2_pinctrl[] = { 183 DAUDIO2_PIN_MCLK, 184 DAUDIO2_PIN_BCLK, 185 DAUDIO2_PIN_LRCK, 186 DAUDIO2_PIN_DOUT0, 187 /* DAUDIO2_PIN_DOUT1, */ 188 DAUDIO2_PIN_DIN, 189 }; 190 191 struct sunxi_daudio_param daudio_param[] = { 192 DAUDIO0_PARAMS, 193 DAUDIO1_PARAMS, 194 DAUDIO2_PARAMS, 195 }; 196 197 #endif /* __SUN8IW20_DAUDIO_H_ */ 198