1 /* 2 * Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved. 3 * 4 * Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in 5 * the the people's Republic of China and other countries. 6 * All Allwinner Technology Co.,Ltd. trademarks are used with permission. 7 * 8 * DISCLAIMER 9 * THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT. 10 * IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.) 11 * IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN 12 * ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES. 13 * ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS 14 * COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE. 15 * YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY. 16 * 17 * 18 * THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT 19 * PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND, 20 * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING 21 * THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE 22 * OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. 23 * IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 26 * LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 30 * OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 #ifndef __SUN8IW20_DMIC_H_ 33 #define __SUN8IW20_DMIC_H_ 34 35 #define SUNXI_DMIC_MEMBASE (0x02031000) 36 37 /*------------------------ CLK CONFIG FOR NORMAL ---------------------------*/ 38 #define SUNXI_DMIC_CLK_PLL_AUDIO CLK_PLL_AUDIO0 39 #define SUNXI_DMIC_CLK_DMIC CLK_DMIC 40 #define SUNXI_DMIC_CLK_BUS CLK_BUS_DMIC 41 #define SUNXI_DMIC_CLK_RST RST_BUS_DMIC 42 43 /*------------------------ PIN CONFIG FOR NORMAL ---------------------------*/ 44 45 46 47 /*------------------------ PIN CONFIG FOR FPGA VERIFY -----------------------*/ 48 dmic_gpio_t g_dmic_gpio = { 49 .clk = {GPIOF(9), 2}, 50 .din0 = {GPIOF(28), 2}, 51 .din1 = {GPIOG(30), 2}, 52 .din2 = {GPIOG(28), 2}, 53 .din3 = {GPIOG(26), 2}, 54 }; 55 56 #endif /* __SUN8IW20_DMIC_H_ */ 57