1 /* 2 * Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved. 3 * 4 * Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in 5 * the the people's Republic of China and other countries. 6 * All Allwinner Technology Co.,Ltd. trademarks are used with permission. 7 * 8 * DISCLAIMER 9 * THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT. 10 * IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.) 11 * IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN 12 * ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES. 13 * ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS 14 * COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE. 15 * YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY. 16 * 17 * 18 * THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT 19 * PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND, 20 * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING 21 * THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE 22 * OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. 23 * IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 26 * LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 30 * OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 #ifndef __SUNXI_DMIC_H_ 33 #define __SUNXI_DMIC_H_ 34 35 #include <aw_common.h> 36 #include <hal_clk.h> 37 #include <hal_reset.h> 38 #include <hal_gpio.h> 39 #include <sound/snd_core.h> 40 #include <sound/snd_pcm.h> 41 #include <sound/snd_io.h> 42 43 #define DMIC_NAME_LEN (16) 44 45 /*------------------DMIC register definition--------------------*/ 46 #define SUNXI_DMIC_EN 0x00 47 #define SUNXI_DMIC_SR 0x04 48 #define SUNXI_DMIC_CTR 0x08 49 #define SUNXI_DMIC_DATA 0x10 50 #define SUNXI_DMIC_INTC 0x14 51 #define SUNXI_DMIC_INTS 0x18 52 #define SUNXI_DMIC_FIFO_CTR 0x1c 53 #define SUNXI_DMIC_FIFO_STA 0x20 54 #define SUNXI_DMIC_CH_NUM 0x24 55 #define SUNXI_DMIC_CH_MAP 0x28 56 #define SUNXI_DMIC_CNT 0x2c 57 #define SUNXI_DMIC_DATA0_1_VOL 0x30 58 #define SUNXI_DMIC_DATA2_3_VOL 0x34 59 #define SUNXI_DMIC_HPF_CTRL 0x38 60 #define SUNXI_DMIC_HPF_COEF 0x3C 61 #define SUNXI_DMIC_HPF_GAIN 0x40 62 #define SUNXI_DMIC_REV 0x50 63 64 /*0x00:SUNXI_DMIC_EN*/ 65 #define GLOBE_EN 8 66 #define DATA3_CHR_EN 7 67 #define DATA3_CHL_EN 6 68 #define DATA2_CHR_EN 5 69 #define DATA2_CHL_EN 4 70 #define DATA1_CHR_EN 3 71 #define DATA1_CHL_EN 2 72 #define DATA0_CHR_EN 1 73 #define DATA0_CHL_EN 0 74 #define DATA_CH_EN 0 75 76 /*SUNXI_DMIC_SR:0x04*/ 77 #define DMIC_SR 0 78 79 /*SUNXI_DMIC_CTR:0x08*/ 80 #define DMICFDT 9 81 #define DMICDFEN 8 82 #define DATA3_LR_SWEEP_EN 7 83 #define DATA2_LR_SWEEP_EN 6 84 #define DATA1_LR_SWEEP_EN 5 85 #define DATA0_LR_SWEEP_EN 4 86 #define DMIC_OVERSAMPLE_RATE 0 87 88 /*SUNXI_DMIC_DATA:0x10*/ 89 #define DMIC_DATA 0 90 91 /*SUNXI_DMIC_INTC:0x14*/ 92 #define FIFO_DRQ_EN 2 93 #define FIFO_OVERRUN_IRQ_EN 1 94 #define DATA_IRQ_EN 0 95 96 /*SUNXI_DMIC_INTS:0x18*/ 97 #define FIFO_OVERRUN_IRQ_PENDING 1 98 #define FIFO_DATA_IRQ_PENDING 0 99 100 /*SUNXI_DMIC_FIFO_CTR:0x1c*/ 101 #define DMIC_FIFO_FLUSH 31 102 #define DMIC_FIFO_MODE 9 103 #define DMIC_SAMPLE_RESOLUTION 8 104 #define FIFO_TRG_LEVEL 0 105 106 /*SUNXI_DMIC_FIFO_STA:0x20*/ 107 #define DMIC_DATA_CNT 0 108 109 /*SUNXI_DMIC_CH_NUM:0x24*/ 110 #define DMIC_CH_NUM 0 111 112 /*SUNXI_DMIC_CH_MAP:0x28*/ 113 #define DMIC_CH7_MAP 28 114 #define DMIC_CH6_MAP 24 115 #define DMIC_CH5_MAP 20 116 #define DMIC_CH4_MAP 16 117 #define DMIC_CH3_MAP 12 118 #define DMIC_CH2_MAP 8 119 #define DMIC_CH1_MAP 4 120 #define DMIC_CH0_MAP 0 121 #define DMIC_CHANMAP_DEFAULT (0x76543210) 122 /*SUNXI_DMIC_CNT:0x2c*/ 123 #define DMIC_CNT 0 124 125 /*SUNXI_DMIC_DATA0_1_VOL:0x30*/ 126 #define DATA1L_VOL 24 127 #define DATA1R_VOL 16 128 #define DATA0L_VOL 8 129 #define DATA0R_VOL 0 130 131 /*SUNXI_DMIC_DATA2_3_VOL:0x34*/ 132 #define DATA3L_VOL 24 133 #define DATA3R_VOL 16 134 #define DATA2L_VOL 8 135 #define DATA2R_VOL 0 136 #define DMIC_DEFAULT_VOL 0xB0B0B0B0 137 138 /*SUNXI_DMIC_HPF_EN_CTR:0x38*/ 139 #define HPF_DATA3_CHR_EN 7 140 #define HPF_DATA3_CHL_EN 6 141 #define HPF_DATA2_CHR_EN 5 142 #define HPF_DATA2_CHL_EN 4 143 #define HPF_DATA1_CHR_EN 3 144 #define HPF_DATA1_CHL_EN 2 145 #define HPF_DATA0_CHR_EN 1 146 #define HPF_DATA0_CHL_EN 0 147 148 /*SUNXI_DMIC_HPF_COEF:0x3C*/ 149 #define HPF_COEF 0 150 151 /*SUNXI_DMIC_HPF_GAIN:0x40*/ 152 #define HPF_GAIN 0 153 154 #define SUNXI_DMIC_RATES (SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_KNOT) 155 156 typedef struct { 157 gpio_pin_t gpio; 158 unsigned int mux; 159 } dmic_gpio; 160 161 typedef struct { 162 dmic_gpio clk; 163 dmic_gpio din0; 164 dmic_gpio din1; 165 dmic_gpio din2; 166 dmic_gpio din3; 167 } dmic_gpio_t; 168 169 struct dmic_rate { 170 unsigned int samplerate; 171 unsigned int rate_bit; 172 }; 173 174 struct sunxi_dmic_info { 175 struct sunxi_dma_params capture_dma_param; 176 u32 chanmap; 177 hal_clk_t pllclk; 178 hal_clk_t moduleclk; 179 hal_clk_t busclk; 180 struct reset_control *rstclk; 181 }; 182 183 /* aw1851 */ 184 #ifdef CONFIG_ARCH_SUN8IW18P1 185 #include "platforms/dmic-sun8iw18.h" 186 #endif 187 /* aw1859 */ 188 #ifdef CONFIG_ARCH_SUN8IW20 189 #include "platforms/dmic-sun8iw20.h" 190 #endif 191 192 #endif /* SUNXI_DMIC_H */ 193