1 /*
2 * Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
3 *
4 * Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
5 * the the people's Republic of China and other countries.
6 * All Allwinner Technology Co.,Ltd. trademarks are used with permission.
7 *
8 * DISCLAIMER
9 * THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
10 * IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
11 * IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
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14 * COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
15 * YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY.
16 *
17 *
18 * THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
19 * PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
20 * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
21 * THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
22 * OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
23 * IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
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29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
30 * OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32 #ifndef __SUNXI_SPDIF_H_
33 #define __SUNXI_SPDIF_H_
34 
35 #include <aw_common.h>
36 #include <hal_clk.h>
37 #include <hal_reset.h>
38 #include <hal_gpio.h>
39 #include <sound/snd_core.h>
40 #include <sound/snd_pcm.h>
41 #include <sound/snd_io.h>
42 
43 /*#define SUNXI_SPDIF_DEBUG_REG*/
44 
45 #define SPDIF_NAME_LEN      (16)
46 
47 /*------------------SPDIF register definition--------------------*/
48 #define SUNXI_SPDIF_CTL     0x00
49 #define SUNXI_SPDIF_TXCFG   0x04
50 #define SUNXI_SPDIF_RXCFG   0x08
51 #define SUNXI_SPDIF_INT_STA (0x0C)
52 #define SUNXI_SPDIF_RXFIFO  0x10
53 #define SUNXI_SPDIF_FIFO_CTL    0x14
54 #define SUNXI_SPDIF_FIFO_STA    0x18
55 #define SUNXI_SPDIF_INT     0x1C
56 #define SUNXI_SPDIF_TXFIFO  (0x20)
57 #define SUNXI_SPDIF_TXCNT   0x24
58 #define SUNXI_SPDIF_RXCNT   0x28
59 #define SUNXI_SPDIF_TXCH_STA0   0x2C
60 #define SUNXI_SPDIF_TXCH_STA1   0x30
61 #define SUNXI_SPDIF_RXCH_STA0   0x34
62 #define SUNXI_SPDIF_RXCH_STA1   0x38
63 
64 /* SUNXI_SPDIF_CTL register */
65 #define CTL_RESET       0
66 #define CTL_GEN_EN      1
67 #define CTL_LOOP_EN     2
68 #define CTL_RESET_RX        0
69 
70 /* SUNXI_SPDIF_TXCFG register */
71 #define TXCFG_TXEN      0
72 /* Chan status generated form TX_CHSTA */
73 #define TXCFG_CHAN_STA_EN   1
74 #define TXCFG_SAMPLE_BIT    2
75 #define TXCFG_CLK_DIV_RATIO 4
76 #define TXCFG_DATA_TYPE     16
77 /* Only valid in PCM mode */
78 #define TXCFG_ASS       17
79 #define TXCFG_SINGLE_MOD    31
80 
81 /* SUNXI_SPDIF_RXCFG register */
82 #define RXCFG_RXEN      0
83 #define RXCFG_CHSR_CP       1
84 #define RXCFG_CHST_SRC      3
85 #define RXCFG_LOCK_FLAG     4
86 
87 /* SUNXI_SPDIF_FIFO_CTL register */
88 #define FIFO_CTL_RXOM       0
89 #define FIFO_CTL_TXIM       2
90 #define FIFO_CTL_RXTL       4
91 #define FIFO_CTL_TXTL       12
92 #define FIFO_CTL_FRX        29
93 #define FIFO_CTL_FTX        30
94 #define FIFO_CTL_HUBEN      31
95 #define CTL_TXTL_MASK       0xFF
96 #define CTL_TXTL_DEFAULT    0x40
97 #define CTL_RXTL_MASK       0x7F
98 #define CTL_RXTL_DEFAULT    0x20
99 
100 /* SUNXI_SPDIF_FIFO_STA register */
101 #define FIFO_STA_RXA_CNT    0
102 #define FIFO_STA_RXA        15
103 #define FIFO_STA_TXA_CNT    16
104 #define FIFO_STA_TXE        31
105 
106 /* SUNXI_SPDIF_INT register */
107 #define INT_RXAIEN      0
108 #define INT_RXOIEN      1
109 #define INT_RXDRQEN     2
110 #define INT_TXEIEN      4
111 #define INT_TXOIEN      5
112 #define INT_TXUIEN      6
113 #define INT_TXDRQEN     7
114 #define INT_RXPAREN     16
115 #define INT_RXUNLOCKEN      17
116 #define INT_RXLOCKEN        18
117 
118 /* SUNXI_SPDIF_INT_STA  */
119 #define INT_STA_RXA     0
120 #define INT_STA_RXO     1
121 #define INT_STA_TXE     4
122 #define INT_STA_TXO     5
123 #define INT_STA_TXU     6
124 #define INT_STA_RXPAR       16
125 #define INT_STA_RXUNLOCK    17
126 #define INT_STA_RXLOCK      18
127 
128 /* SUNXI_SPDIF_TXCH_STA0 register */
129 #define TXCHSTA0_PRO        0
130 #define TXCHSTA0_AUDIO      1
131 #define TXCHSTA0_CP     2
132 #define TXCHSTA0_EMPHASIS   3
133 #define TXCHSTA0_MODE       6
134 #define TXCHSTA0_CATACOD    8
135 #define TXCHSTA0_SRCNUM     16
136 #define TXCHSTA0_CHNUM      20
137 #define TXCHSTA0_SAMFREQ    24
138 #define TXCHSTA0_CLK        28
139 
140 /* SUNXI_SPDIF_TXCH_STA1 register */
141 #define TXCHSTA1_MAXWORDLEN 0
142 #define TXCHSTA1_SAMWORDLEN 1
143 #define TXCHSTA1_ORISAMFREQ 4
144 #define TXCHSTA1_CGMSA      8
145 
146 /* SUNXI_SPDIF_RXCH_STA0 register */
147 #define RXCHSTA0_PRO        0
148 #define RXCHSTA0_AUDIO      1
149 #define RXCHSTA0_CP     2
150 #define RXCHSTA0_EMPHASIS   3
151 #define RXCHSTA0_MODE       6
152 #define RXCHSTA0_CATACOD    8
153 #define RXCHSTA0_SRCNUM     16
154 #define RXCHSTA0_CHNUM      20
155 #define RXCHSTA0_SAMFREQ    24
156 #define RXCHSTA0_CLK        28
157 
158 /* SUNXI_SPDIF_RXCH_STA1 register */
159 #define RXCHSTA1_MAXWORDLEN 0
160 #define RXCHSTA1_SAMWORDLEN 1
161 #define RXCHSTA1_ORISAMFREQ 4
162 #define RXCHSTA1_CGMSA      8
163 
164 #define SUNXI_SPDIF_RATES (SNDRV_PCM_RATE_8000_192000 | SNDRV_PCM_RATE_KNOT)
165 
166 typedef struct {
167     gpio_pin_t gpio;
168     unsigned int mux;
169 } spdif_gpio;
170 
171 typedef struct {
172 //  spdif_gpio clk;
173     spdif_gpio out;
174     spdif_gpio in;
175 } spdif_gpio_t;
176 
177 struct spdif_rate {
178     unsigned int samplerate;
179     unsigned int rate_bit;
180 };
181 
182 struct sunxi_spdif_info {
183     struct sunxi_dma_params playback_dma_param;
184     struct sunxi_dma_params capture_dma_param;
185     hal_clk_t pllclk;
186     hal_clk_t moduleclk;
187     hal_clk_t busclk;
188     struct reset_control *rstclk;
189     hal_clk_t pllclk1;
190     hal_clk_t pllclk1_div;
191     hal_clk_t moduleclk_rx;
192 };
193 
194 /* aw1859 */
195 #ifdef CONFIG_ARCH_SUN8IW20
196 #include "platforms/spdif-sun8iw20.h"
197 #endif
198 
199 #endif /* __SUNXI_SPDIF_H_ */
200