1 /* 2 * Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved. 3 * 4 * Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in 5 * the the People's Republic of China and other countries. 6 * All Allwinner Technology Co.,Ltd. trademarks are used with permission. 7 * 8 * DISCLAIMER 9 * THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT. 10 * IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.) 11 * IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN 12 * ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES. 13 * ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS 14 * COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE. 15 * YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY. 16 * 17 * 18 * THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT 19 * PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND, 20 * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING 21 * THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE 22 * OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. 23 * IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 26 * LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 30 * OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef __COMMON_SPI_I_H__ 34 #define __COMMON_SPI_I_H__ 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 #define SUNXI_SPI_REG_SIZE 0x1000 /* controler reg sized */ 41 42 #define HEXADECIMAL (0x10) 43 #define REG_INTERVAL (0x04) 44 #define REG_CL (0x0c) 45 46 #define SPI_FIFO_DEPTH (128) 47 #define MAX_FIFU 64 48 #define BULK_DATA_BOUNDARY 64 /* can modify to adapt the application */ 49 #define SPI_MAX_FREQUENCY 100000000 /* spi controller just support 100Mhz */ 50 #define SPI_HIGH_FREQUENCY 60000000 /* sample mode threshold frequency */ 51 #define SPI_LOW_FREQUENCY 24000000 /* sample mode threshold frequency */ 52 #define SPI_MOD_CLK 50000000 /* sample mode frequency */ 53 54 /* SPI Registers offsets from peripheral base address */ 55 #define SPI_VER_REG (0x00) /* version number register */ 56 #define SPI_GC_REG (0x04) /* global control register */ 57 #define SPI_TC_REG (0x08) /* transfer control register */ 58 #define SPI_INT_CTL_REG (0x10) /* interrupt control register */ 59 #define SPI_INT_STA_REG (0x14) /* interrupt status register */ 60 #define SPI_FIFO_CTL_REG (0x18) /* fifo control register */ 61 #define SPI_FIFO_STA_REG (0x1C) /* fifo status register */ 62 #define SPI_WAIT_CNT_REG (0x20) /* wait clock counter register */ 63 #define SPI_CLK_CTL_REG \ 64 (0x24) /* clock rate control register. better not to use it */ 65 #define SPI_BURST_CNT_REG (0x30) /* burst counter register */ 66 #define SPI_TRANSMIT_CNT_REG (0x34) /* transmit counter register */ 67 #define SPI_BCC_REG (0x38) /* burst control counter register */ 68 #define SPI_DMA_CTL_REG (0x88) /* DMA control register, only for 1639 */ 69 #define SPI_TXDATA_REG (0x200) /* tx data register */ 70 #define SPI_RXDATA_REG (0x300) /* rx data register */ 71 72 /* SPI Global Control Register Bit Fields & Masks,default value:0x0000_0080 */ 73 #define SPI_GC_EN \ 74 (0x1 \ 75 << 0) /* SPI module enable control 1:enable; 0:disable; default:0 */ 76 #define SPI_GC_MODE \ 77 (0x1 << 1) /* SPI function mode select 1:master; 0:slave; default:0 */ 78 #define SPI_GC_TP_EN \ 79 (0x1 << 7) /* SPI transmit stop enable 1:stop transmit data when \ 80 RXFIFO is full; 0:ignore RXFIFO status; default:1 */ 81 #define SPI_GC_SRST \ 82 (0x1 << 31) /* soft reset, write 1 will clear SPI control, auto \ 83 clear to 0 */ 84 /* SPI Transfer Control Register Bit Fields & Masks,default value:0x0000_0087 */ 85 #define SPI_TC_PHA \ 86 (0x1 << 0) /* SPI Clock/Data phase control,0: phase0,1: \ 87 phase1;default:1 */ 88 #define SPI_TC_POL \ 89 (0x1 << 1) /* SPI Clock polarity control,0:low level idle,1:high \ 90 level idle;default:1 */ 91 #define SPI_TC_SPOL \ 92 (0x1 << 2) /* SPI Chip select signal polarity control,default: 1,low \ 93 effective like this:~~|_____~~ */ 94 #define SPI_TC_SSCTL \ 95 (0x1 \ 96 << 3) /* SPI chip select control,default 0:SPI_SSx remains asserted \ 97 between SPI bursts,1:negate SPI_SSx between SPI bursts */ 98 #define SPI_TC_SS_MASK \ 99 (0x3 << 4) /* SPI chip \ 100 select:00-SPI_SS0;01-SPI_SS1;10-SPI_SS2;11-SPI_SS3*/ 101 #define SPI_TC_SS_OWNER \ 102 (0x1 << 6) /* SS output mode select default is 0:automatic output \ 103 SS;1:manual output SS */ 104 #define SPI_TC_SS_LEVEL \ 105 (0x1 << 7) /* defautl is 1:set SS to high;0:set SS to low */ 106 #define SPI_TC_DHB \ 107 (0x1 \ 108 << 8) /* Discard Hash Burst,default 0:receiving all spi burst in BC \ 109 period 1:discard unused,fectch WTC bursts */ 110 #define SPI_TC_DDB \ 111 (0x1 << 9) /* Dummy burst Type,default 0: dummy spi burst is \ 112 zero;1:dummy spi burst is one */ 113 #define SPI_TC_RPSM \ 114 (0x1 << 10) /* select mode for high speed write,0:normal write \ 115 mode,1:rapids write mode,default 0 */ 116 #define SPI_TC_SDM \ 117 (0x1 << 13) /* master sample data mode, 1: normal sample \ 118 mode;0:delay sample mode. */ 119 #define SPI_TC_SDC \ 120 (0x1 << 11) /* master sample data control, 1: delay--high speed \ 121 operation;0:no delay. */ 122 #define SPI_TC_FBS \ 123 (0x1 << 12) /* LSB/MSB transfer first select 0:MSB,1:LSB,default \ 124 0:MSB first */ 125 #define SPI_TC_XCH \ 126 (0x1 \ 127 << 31) /* Exchange burst default 0:idle,1:start exchange;when BC is \ 128 zero,this bit cleared by SPI controller*/ 129 #define SPI_TC_SS_BIT_POS (4) 130 131 /* SPI Interrupt Control Register Bit Fields & Masks,default value:0x0000_0000 132 */ 133 #define SPI_INTEN_RX_RDY \ 134 (0x1 << 0) /* rxFIFO Ready Interrupt Enable,---used for immediately \ 135 received,0:disable;1:enable */ 136 #define SPI_INTEN_RX_EMP \ 137 (0x1 << 1) /* rxFIFO Empty Interrupt Enable ---used for IRQ received \ 138 */ 139 #define SPI_INTEN_RX_FULL \ 140 (0x1 << 2) /* rxFIFO Full Interrupt Enable ---seldom used */ 141 #define SPI_INTEN_TX_ERQ \ 142 (0x1 << 4) /* txFIFO Empty Request Interrupt Enable ---seldom used */ 143 #define SPI_INTEN_TX_EMP \ 144 (0x1 << 5) /* txFIFO Empty Interrupt Enable ---used for IRQ tx */ 145 #define SPI_INTEN_TX_FULL \ 146 (0x1 << 6) /* txFIFO Full Interrupt Enable ---seldom used */ 147 #define SPI_INTEN_RX_OVF \ 148 (0x1 \ 149 << 8) /* rxFIFO Overflow Interrupt Enable ---used for error detect */ 150 #define SPI_INTEN_RX_UDR \ 151 (0x1 \ 152 << 9) /* rxFIFO Underrun Interrupt Enable ---used for error detect */ 153 #define SPI_INTEN_TX_OVF \ 154 (0x1 << 10) /* txFIFO Overflow Interrupt Enable ---used for error \ 155 detect */ 156 #define SPI_INTEN_TX_UDR \ 157 (0x1 << 11) /* txFIFO Underrun Interrupt Enable ---not happened */ 158 #define SPI_INTEN_TC \ 159 (0x1 << 12) /* Transfer Completed Interrupt Enable ---used */ 160 #define SPI_INTEN_SSI \ 161 (0x1 << 13) /* SSI interrupt Enable,chip select from valid state to \ 162 invalid state,for slave used only */ 163 #define SPI_INTEN_ERR \ 164 (SPI_INTEN_TX_OVF | SPI_INTEN_RX_UDR | \ 165 SPI_INTEN_RX_OVF) /* NO txFIFO underrun */ 166 #define SPI_INTEN_MASK (0x77 | (0x3f << 8)) 167 168 /* SPI Interrupt Status Register Bit Fields & Masks,default value:0x0000_0022 */ 169 #define SPI_INT_STA_RX_RDY \ 170 (0x1 << 0) /* rxFIFO ready, 0:RX_WL < RX_TRIG_LEVEL,1:RX_WL >= \ 171 RX_TRIG_LEVEL */ 172 #define SPI_INT_STA_RX_EMP \ 173 (0x1 << 1) /* rxFIFO empty, this bit is set when rxFIFO is empty */ 174 #define SPI_INT_STA_RX_FULL \ 175 (0x1 << 2) /* rxFIFO full, this bit is set when rxFIFO is full */ 176 #define SPI_INT_STA_TX_RDY \ 177 (0x1 << 4) /* txFIFO ready, 0:TX_WL > TX_TRIG_LEVEL,1:TX_WL <= \ 178 TX_TRIG_LEVEL */ 179 #define SPI_INT_STA_TX_EMP \ 180 (0x1 << 5) /* txFIFO empty, this bit is set when txFIFO is empty */ 181 #define SPI_INT_STA_TX_FULL \ 182 (0x1 << 6) /* txFIFO full, this bit is set when txFIFO is full */ 183 #define SPI_INT_STA_RX_OVF \ 184 (0x1 << 8) /* rxFIFO overflow, when set rxFIFO has overflowed */ 185 #define SPI_INT_STA_RX_UDR \ 186 (0x1 << 9) /* rxFIFO underrun, when set rxFIFO has underrun */ 187 #define SPI_INT_STA_TX_OVF \ 188 (0x1 << 10) /* txFIFO overflow, when set txFIFO has overflowed */ 189 #define SPI_INT_STA_TX_UDR \ 190 (0x1 << 11) /* fxFIFO underrun, when set txFIFO has underrun */ 191 #define SPI_INT_STA_TC (0x1 << 12) /* Transfer Completed */ 192 #define SPI_INT_STA_SSI \ 193 (0x1 << 13) /* SS invalid interrupt, when set SS has changed from \ 194 valid to invalid */ 195 #define SPI_INT_STA_ERR \ 196 (SPI_INT_STA_TX_OVF | SPI_INT_STA_RX_UDR | \ 197 SPI_INT_STA_RX_OVF) /* NO txFIFO underrun */ 198 #define SPI_INT_STA_MASK (0x77 | (0x3f << 8)) 199 200 /* SPI FIFO Control Register Bit Fields & Masks,default value:0x0040_0001 */ 201 #define SPI_FIFO_CTL_RX_LEVEL \ 202 (0xFF << 0) /* rxFIFO reday request trigger level,default 0x1 */ 203 #define SPI_FIFO_CTL_RX_DRQEN \ 204 (0x1 << 8) /* rxFIFO DMA request enable,1:enable,0:disable */ 205 #define SPI_FIFO_CTL_RX_TESTEN \ 206 (0x1 << 14) /* rxFIFO test mode enable,1:enable,0:disable */ 207 #define SPI_FIFO_CTL_RX_RST \ 208 (0x1 << 15) /* rxFIFO reset, write 1, auto clear to 0 */ 209 #define SPI_FIFO_CTL_TX_LEVEL \ 210 (0xFF << 16) /* txFIFO empty request trigger level,default 0x40 */ 211 #define SPI_FIFO_CTL_TX_DRQEN \ 212 (0x1 << 24) /* txFIFO DMA request enable,1:enable,0:disable */ 213 #define SPI_FIFO_CTL_TX_TESTEN \ 214 (0x1 << 30) /* txFIFO test mode enable,1:enable,0:disable */ 215 #define SPI_FIFO_CTL_TX_RST \ 216 (0x1 << 31) /* txFIFO reset, write 1, auto clear to 0 */ 217 #define SPI_FIFO_CTL_DRQEN_MASK (SPI_FIFO_CTL_TX_DRQEN | SPI_FIFO_CTL_RX_DRQEN) 218 219 /* SPI FIFO Status Register Bit Fields & Masks,default value:0x0000_0000 */ 220 #define SPI_FIFO_STA_RX_CNT \ 221 (0xFF << 0) /* rxFIFO counter,how many bytes in rxFIFO */ 222 #define SPI_FIFO_STA_RB_CNT \ 223 (0x7 << 12) /* rxFIFO read buffer counter,how many bytes in rxFIFO \ 224 read buffer */ 225 #define SPI_FIFO_STA_RB_WR (0x1 << 15) /* rxFIFO read buffer write enable */ 226 #define SPI_FIFO_STA_TX_CNT \ 227 (0xFF << 16) /* txFIFO counter,how many bytes in txFIFO */ 228 #define SPI_FIFO_STA_TB_CNT \ 229 (0x7 << 28) /* txFIFO write buffer counter,how many bytes in txFIFO \ 230 write buffer */ 231 #define SPI_FIFO_STA_TB_WR (0x1 << 31) /* txFIFO write buffer write enable */ 232 #define SPI_RXCNT_BIT_POS (0) 233 #define SPI_TXCNT_BIT_POS (16) 234 235 /* SPI Wait Clock Register Bit Fields & Masks,default value:0x0000_0000 */ 236 #define SPI_WAIT_WCC_MASK \ 237 (0xFFFF << 0) /* used only in master mode: Wait Between Transactions \ 238 */ 239 #define SPI_WAIT_SWC_MASK \ 240 (0xF << 16) /* used only in master mode: Wait before start dual data \ 241 transfer in dual SPI mode */ 242 243 /* SPI Clock Control Register Bit Fields & Masks,default:0x0000_0002 */ 244 #define SPI_CLK_CTL_CDR2 \ 245 (0xFF << 0) /* Clock Divide Rate 2,master mode only : SPI_CLK = \ 246 AHB_CLK/(2*(n+1)) */ 247 #define SPI_CLK_CTL_CDR1 \ 248 (0xF << 8) /* Clock Divide Rate 1,master mode only : SPI_CLK = \ 249 AHB_CLK/2^n */ 250 #define SPI_CLK_CTL_DRS \ 251 (0x1 << 12) /* Divide rate select,default,0:rate 1;1:rate 2 */ 252 #define SPI_CLK_SCOPE (SPI_CLK_CTL_CDR2 + 1) 253 254 /* SPI Master Burst Counter Register Bit Fields & Masks,default:0x0000_0000 */ 255 /* master mode: when SMC = 1,BC specifies total burst number, Max length is 256 * 16Mbytes */ 257 #define SPI_BC_CNT_MASK \ 258 (0xFFFFFF << 0) /* Total Burst Counter, tx length + rx length ,SMC=1 \ 259 */ 260 261 /* SPI Master Transmit Counter reigster default:0x0000_0000 */ 262 #define SPI_TC_CNT_MASK \ 263 (0xFFFFFF \ 264 << 0) /* Write Transmit Counter, tx length, NOT rx length!!! */ 265 266 /* SPI Master Burst Control Counter reigster Bit Fields & 267 * Masks,default:0x0000_0000 */ 268 #define SPI_BCC_STC_MASK \ 269 (0xFFFFFF << 0) /* master single mode transmit counter */ 270 #define SPI_BCC_DBC_MASK (0xF << 24) /* master dummy burst counter */ 271 #define SPI_BCC_DUAL_MODE (0x1 << 28) /* master dual mode RX enable */ 272 #define SPI_BCC_QUAD_MODE (0x1 << 29) /* master quad mode RX enable */ 273 274 #define SPI_PHA_ACTIVE_ (0x01) 275 #define SPI_POL_ACTIVE_ (0x02) 276 277 #define SPI_MODE_0_ACTIVE_ (0 | 0) 278 #define SPI_MODE_1_ACTIVE_ (0 | SPI_PHA_ACTIVE_) 279 #define SPI_MODE_2_ACTIVE_ (SPI_POL_ACTIVE_ | 0) 280 #define SPI_MODE_3_ACTIVE_ (SPI_POL_ACTIVE_ | SPI_PHA_ACTIVE_) 281 #define SPI_CS_HIGH_ACTIVE_ (0x04) 282 #define SPI_LSB_FIRST_ACTIVE_ (0x08) 283 #define SPI_DUMMY_ONE_ACTIVE_ (0x10) 284 #define SPI_RECEIVE_ALL_ACTIVE_ (0x20) 285 286 #define SUNXI_SPI_DRQ_RX(ch) (DRQSRC_SPI0_RX + ch) 287 #define SUNXI_SPI_DRQ_TX(ch) (DRQDST_SPI0_TX + ch) 288 289 #define SPIM_BUSY (1) 290 #define SPIM_IDLE (0) 291 292 #define spim_set_idle(master_port) \ 293 do { \ 294 g_spi_master_status[master_port] = SPIM_IDLE; \ 295 } while (0) 296 297 #define SPI_MASTER_MB_LSB_FIRST (0x1UL << 3) 298 #define SPI_MASTER_MB_MSB_FIRST (0x0UL << 3) 299 300 #define SPI_MASTER_CPOL_0 (0x0UL << 4) 301 #define SPI_MASTER_CPOL_1 (0x1UL << 4) 302 303 #define SPI_MASTER_CPHA_0 (0x0UL << 5) 304 #define SPI_MASTER_CPHA_1 (0x1UL << 5) 305 306 #define SPI_MASTER_INT_DISABLE (0x0UL << 9) 307 #define SPI_MASTER_INT_ENABLE (0x1UL << 9) 308 309 #define SPI_MASTER_HALF_DUPLEX (0x0UL << 10) 310 #define SPI_MASTER_FULL_DUPLEX (0x1UL << 10) 311 312 #define SPI_MASTER_SLAVE_SEL_0 (0x0UL << 29) 313 #define SPI_MASTER_SLAVE_SEL_1 (0x1UL << 29) 314 315 #ifdef __cplusplus 316 } 317 #endif 318 #endif /* __COMMON_SPI_I_H__ */ 319