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3 *
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7 *
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31 */
32 
33 #ifndef __COMMON_TPADC_H__
34 #define __COMMON_TPADC_H__
35 
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39 
40 /* SET_BITS */
41 #define SETMASK(width, shift)   ((width?((-1U) >> (32-width)):0)  << (shift))
42 #define CLRMASK(width, shift)   (~(SETMASK(width, shift)))
43 #define GET_BITS(shift, width, reg)     \
44     (((reg) & SETMASK(width, shift)) >> (shift))
45 #define SET_BITS(shift, width, reg, val) \
46     (((reg) & CLRMASK(width, shift)) | (val << (shift)))
47 
48 #define TPADC_WIDTH     4095  /*12bit 0XFFF*/
49 #define TPADC_CLK_IN        (12000000)
50 #define DCXO24M         (24000000)
51 
52 /* TPADC register offset */
53 #define TP_CTRL0        0x00
54 #define TP_CTRL1        0x04
55 #define TP_CTRL2        0x08
56 #define TP_CTRL3        0x0c
57 #define TP_INT_FIFOC    0x10
58 #define TP_INT_FIFOS    0x14
59 #define TP_TPR          0x18
60 #define TP_CDAT         0x1c
61 #define TP_DATA     0x24
62 
63 /* tpadc regsiter offset and width */
64 #define FIFO_OVERRUN_PENDING    17
65 #define FIFO_OVERRUN_PENDIN_WIDTH 1
66 
67 #define FIFO_DATA_PENDING   16
68 #define FIFO_DATA_PENDING_WIDTH 1
69 
70 #define TP_FIFO_FLUSH   4
71 #define TP_FIFO_FLUSH_WIDTH 1
72 
73 #define TACQ    0
74 #define TACQ_WIDTH  16
75 
76 #define FS_DIV  16
77 #define FS_DIV_WIDTH    4
78 
79 #define ADC_CLK_DIVIDER 20
80 #define ADC_CLK_DIVIDER_WIDTH   2
81 
82 #define ADC_FIRST_DLY_MODE  23
83 #define ADC_FIRST_DLY_MODE_WIDTH    1
84 
85 #define ADC_FIRST_DLY   24
86 #define ADC_FIRST_DLY_WIDTH 8
87 
88 #define TP_MODE_SELECT  4
89 #define TP_MODE_SELECT_WIDTH    1
90 
91 #define TP_EN   5
92 #define TP_EN_WIDTH 1
93 
94 #define TP_DEBOUNCE 12
95 #define TP_DEBOUNCE_WIDTH   8
96 
97 #define PRE_MEA 0
98 #define PRE_MEA_WIDTH   24
99 
100 #define PRE_MEA_EN  24
101 #define PRE_MEA_EN_WIDTH    1
102 
103 #define TP_FIFO_MODE    26
104 #define TP_FIFO_MODE_WIDTH  2
105 
106 #define TP_SENSITIVE    28
107 #define TP_SENSITIVE_WIDTH  4
108 
109 #define FILTER_TYPE 0
110 #define FILTER_TYPE_WIDTH   2
111 
112 #define FILTER_EN   2
113 #define FILTER_EN_WIDTH 1
114 
115 #define TP_DOWN_IRQ_EN  0
116 #define TP_DOWN_IRQ_ENWIDTH 1
117 
118 #define TP_UP_IRQ_EN    1
119 #define TP_UP_IRQ_EN_WIDTH  1
120 
121 #define TP_DATA_DRQ_EN  7
122 #define TP_DATA_DRQ_EN_WIDTH    1
123 
124 #define TP_FIFO_TRIG 8
125 #define TP_FIFO_TRIG_WIDTH  5
126 
127 #define TP_DATA_XY_CHANGE   13
128 #define TP_DATA_XY_CHANGE_WIDTH 1
129 
130 #define TP_DATA_IRQ_EN  16
131 #define TP_DATA_IRQ_EN_WIDTH    1
132 
133 #define TP_FIFO_OVERRUN_IRQ 17
134 #define TP_FIFO_OVERRUN_IRQ_WIDTH   1
135 
136 #define TP_DATAPEND     (1<<16)
137 #define TP_UPPEND       (1<<1)
138 #define TP_DOWNPEND     (1<<0)
139 
140 #define OSC_FREQUENCY       24000000
141 #define HOSC            1
142 #define TP_IO_INPUT_MODE    0xfffff
143 
144 #define TP_CH3_SELECT       (1 << 3) /* channale 3 select enable,  0:disable, 1:enable */
145 #define TP_CH2_SELECT       (1 << 2) /* channale 2 select enable,  0:disable, 1:enable */
146 #define TP_CH1_SELECT       (1 << 1) /* channale 1 select enable,  0:disable, 1:enable */
147 #define TP_CH0_SELECT       (1 << 0) /* channale 0 select enable,  0:disable, 1:enable */
148 
149 #ifdef __cplusplus
150 }
151 #endif
152 
153 #endif /* __COMMON_TPADC_I_H__ */
154