1 /*
2 * Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
3 *
4 * Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
5 * the the People's Republic of China and other countries.
6 * All Allwinner Technology Co.,Ltd. trademarks are used with permission.
7 *
8 * DISCLAIMER
9 * THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
10 * IF YOU NEED TO INTEGRATE THIRD PARTY'S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
11 * IN ALLWINNERS'SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
12 * ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
13 * ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
14 * COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
15 * YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY'S TECHNOLOGY.
16 *
17 *
18 * THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
19 * PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
20 * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
21 * THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
22 * OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
23 * IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
30 * OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32 
33 #ifndef __UART_SUN8IW20_H__
34 #define __UART_SUN8IW20_H__
35 
36 #include <rtthread.h>
37 
38 /* config for DSP */
39 #if defined(CONFIG_CORE_DSP0)
40 #include <interrupt.h>
41 
42 #define SUNXI_CLK_UART0 CLK_BUS_UART0
43 #define SUNXI_RST_UART0 RST_BUS_UART0
44 
45 #define SUNXI_CLK_UART1 CLK_BUS_UART1
46 #define SUNXI_RST_UART1 RST_BUS_UART1
47 
48 #define SUNXI_CLK_UART2 CLK_BUS_UART2
49 #define SUNXI_RST_UART2 RST_BUS_UART2
50 
51 #define SUNXI_CLK_UART3 CLK_BUS_UART3
52 #define SUNXI_RST_UART3 RST_BUS_UART3
53 
54 #define SUNXI_IRQ_UART0     (RINTC_IRQ_MASK | 1)
55 #define SUNXI_IRQ_UART1     (RINTC_IRQ_MASK | 2)
56 #define SUNXI_IRQ_UART2     (RINTC_IRQ_MASK | 3)
57 #define SUNXI_IRQ_UART3     (RINTC_IRQ_MASK | 4)
58 
59 #define SUNXI_UART0_BASE    (0x02500000)
60 #define SUNXI_UART1_BASE    (0x02500400)
61 #define SUNXI_UART2_BASE    (0x02500800)
62 #define SUNXI_UART3_BASE    (0x02500C00)
63 
64 #define UART_FIFO_SIZE      (64)
65 
66 #define UART0_GPIO_FUNCTION (3)
67 #define UART1_GPIO_FUNCTION (7)
68 #define UART2_GPIO_FUNCTION (2)
69 #define UART3_GPIO_FUNCTION (5)
70 
71 #define UART0_TX        GPIOF(2)
72 #define UART0_RX        GPIOF(4)
73 #define UART1_TX        GPIOB(8)
74 #define UART1_RX        GPIOB(9)
75 #define UART2_TX        GPIOC(8)
76 #define UART2_RX        GPIOC(9)
77 #define UART3_TX        GPIOD(10)
78 #define UART3_RX        GPIOD(11)
79 
80 #else
81 
82 #define SUNXI_CLK_UART0 CLK_BUS_UART0;
83 #define SUNXI_RST_UART0 RST_BUS_UART0;
84 
85 #define SUNXI_CLK_UART1 CLK_BUS_UART1;
86 #define SUNXI_RST_UART1 RST_BUS_UART1;
87 
88 #define SUNXI_CLK_UART2 CLK_BUS_UART2;
89 #define SUNXI_RST_UART2 RST_BUS_UART2;
90 
91 #define SUNXI_CLK_UART3 CLK_BUS_UART3;
92 #define SUNXI_RST_UART3 RST_BUS_UART3;
93 
94 #define SUNXI_IRQ_UART0     (18)
95 #define SUNXI_IRQ_UART1     (19)
96 #define SUNXI_IRQ_UART2     (20)
97 #define SUNXI_IRQ_UART3     (21)
98 #define SUNXI_IRQ_UART4     (22)
99 #define SUNXI_IRQ_UART5     (23)
100 
101 
102 #define SUNXI_UART0_BASE    (0x02500000)
103 #define SUNXI_UART1_BASE    (0x02500400)
104 #define SUNXI_UART2_BASE    (0x02500800)
105 #define SUNXI_UART3_BASE    (0x02500c00)
106 #define SUNXI_UART4_BASE    (0x02501000)
107 #define SUNXI_UART5_BASE    (0x02501400)
108 
109 //TODO:UART1~5 FIFO:256
110 #define UART_FIFO_SIZE      (64)
111 
112 #define UART0_GPIO_FUNCTION (6)
113 #define UART1_GPIO_FUNCTION (6)
114 #define UART2_GPIO_FUNCTION (6)
115 #define UART3_GPIO_FUNCTION (6)
116 
117 #ifdef BOARD_allwinnerd1
118 #define UART0_TX        GPIOB(8)
119 #define UART0_RX        GPIOB(9)
120 #elif defined(BOARD_allwinnerd1s)
121 #define UART0_TX        GPIOE(2)
122 #define UART0_RX        GPIOE(3)
123 #endif
124 #define UART1_TX        GPIOB(10)
125 #define UART1_RX        GPIOB(11)
126 #define UART2_TX        GPIOL(8)
127 #define UART2_RX        GPIOL(9)
128 #define UART3_TX        GPIOL(8)
129 #define UART3_RX        GPIOL(9)
130 
131 #endif /* CONFIG_CORE_DSP0 */
132 
133 #endif /*__UART_SUN8IW20_H__  */
134