1 /*
2 * Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
3 *
4 * Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
5 * the the People's Republic of China and other countries.
6 * All Allwinner Technology Co.,Ltd. trademarks are used with permission.
7 *
8 * DISCLAIMER
9 * THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
10 * IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
11 * IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
12 * ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
13 * ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
14 * COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
15 * YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY.
16 *
17 *
18 * THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
19 * PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
20 * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
21 * THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
22 * OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
23 * IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
30 * OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32 
33 #ifndef __UART_I_H__
34 #define __UART_I_H__
35 
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39 
40 /*
41  * Register definitions for UART
42  */
43 #define UART_RHB (0x00)
44 #define UART_RBR (0x00)         /* receive buffer register */
45 #define UART_THR (0x00)         /* transmit holding register */
46 #define UART_DLL (0x00)         /* divisor latch low register */
47 #define UART_DLH (0x04)         /* diviso latch high register */
48 #define UART_IER (0x04)         /* interrupt enable register */
49 #define UART_IIR (0x08)         /* interrupt identity register */
50 #define UART_FCR (0x08)         /* FIFO control register */
51 #define UART_LCR (0x0c)         /* line control register */
52 #define UART_MCR (0x10)         /* modem control register */
53 #define UART_LSR (0x14)         /* line status register */
54 #define UART_MSR (0x18)         /* modem status register */
55 #define UART_SCH (0x1c)         /* scratch register */
56 #define UART_USR (0x7c)         /* status register */
57 #define UART_TFL (0x80)         /* transmit FIFO level */
58 #define UART_RFL (0x84)         /* RFL */
59 #define UART_HALT (0xa4)        /* halt tx register */
60 #define UART_RS485 (0xc0)       /* RS485 control and status register */
61 
62 /*
63  * register bit field define
64  */
65 
66 /* Interrupt Enable Register */
67 #define UART_IER_MASK       (0xff)
68 #define UART_IER_PTIME      (BIT(7))
69 #define UART_IER_RS485      (BIT(4))
70 #define UART_IER_MSI        (BIT(3))
71 #define UART_IER_RLSI       (BIT(2))
72 #define UART_IER_THRI       (BIT(1))
73 #define UART_IER_RDI        (BIT(0))
74 /* Interrupt ID Register */
75 #define UART_IIR_FEFLAG_MASK    (BIT(6)|BIT(7))
76 #define UART_IIR_IID_MASK   (BIT(0)|BIT(1)|BIT(2)|BIT(3))
77 #define UART_IIR_IID_MSTA   (0)
78 #define UART_IIR_IID_NOIRQ  (1)
79 #define UART_IIR_IID_THREMP (2)
80 #define UART_IIR_IID_RXDVAL (4)
81 #define UART_IIR_IID_LINESTA    (6)
82 #define UART_IIR_IID_BUSBSY (7)
83 #define UART_IIR_IID_CHARTO (12)
84 /* FIFO Control Register */
85 #define UART_FCR_RXTRG_MASK (BIT(6)|BIT(7))
86 #define UART_FCR_RXTRG_1CH  (0 << 6)
87 #define UART_FCR_RXTRG_1_4  (1 << 6)
88 #define UART_FCR_RXTRG_1_2  (2 << 6)
89 #define UART_FCR_RXTRG_FULL     (3 << 6)
90 #define UART_FCR_TXTRG_MASK (BIT(4)|BIT(5))
91 #define UART_FCR_TXTRG_EMP  (0 << 4)
92 #define UART_FCR_TXTRG_2CH  (1 << 4)
93 #define UART_FCR_TXTRG_1_4  (2 << 4)
94 #define UART_FCR_TXTRG_1_2  (3 << 4)
95 #define UART_FCR_TXFIFO_RST (BIT(2))
96 #define UART_FCR_RXFIFO_RST (BIT(1))
97 #define UART_FCR_FIFO_EN    (BIT(0))
98 /* Line Control Register */
99 #define UART_LCR_DLAB       (BIT(7))
100 #define UART_LCR_SBC        (BIT(6))
101 #define UART_LCR_PARITY_MASK    (BIT(5)|BIT(4))
102 #define UART_LCR_EPAR       (1 << 4)
103 #define UART_LCR_OPAR       (0 << 4)
104 #define UART_LCR_PARITY     (BIT(3))
105 #define UART_LCR_STOP       (BIT(2))
106 #define UART_LCR_DLEN_MASK  (BIT(1)|BIT(0))
107 #define UART_LCR_WLEN5      (0)
108 #define UART_LCR_WLEN6      (1)
109 #define UART_LCR_WLEN7      (2)
110 #define UART_LCR_WLEN8      (3)
111 /* Modem Control Register */
112 #define UART_MCR_MODE_MASK  (BIT(7)|BIT(6))
113 #define UART_MCR_MODE_RS485 (2 << 6)
114 #define UART_MCR_MODE_SIRE  (1 << 6)
115 #define UART_MCR_MODE_UART  (0 << 6)
116 #define UART_MCR_AFE        (BIT(5))
117 #define UART_MCR_LOOP       (BIT(4))
118 #define UART_MCR_RTS        (BIT(1))
119 #define UART_MCR_DTR        (BIT(0))
120 /* Line Status Rigster */
121 #define UART_LSR_RXFIFOE    (BIT(7))
122 #define UART_LSR_TEMT       (BIT(6))
123 #define UART_LSR_THRE       (BIT(5))
124 #define UART_LSR_BI     (BIT(4))
125 #define UART_LSR_FE     (BIT(3))
126 #define UART_LSR_PE     (BIT(2))
127 #define UART_LSR_OE     (BIT(1))
128 #define UART_LSR_DR     (BIT(0))
129 #define UART_LSR_BRK_ERROR_BITS (0x1E) /* BI, FE, PE, OE bits */
130 /* Modem Status Register */
131 #define UART_MSR_DCD        (BIT(7))
132 #define UART_MSR_RI     (BIT(6))
133 #define UART_MSR_DSR        (BIT(5))
134 #define UART_MSR_CTS        (BIT(4))
135 #define UART_MSR_DDCD       (BIT(3))
136 #define UART_MSR_TERI       (BIT(2))
137 #define UART_MSR_DDSR       (BIT(1))
138 #define UART_MSR_DCTS       (BIT(0))
139 #define UART_MSR_ANY_DELTA  (0x0F)
140 #define MSR_SAVE_FLAGS      (UART_MSR_ANY_DELTA)
141 /* Status Register */
142 #define UART_USR_RFF        (BIT(4))
143 #define UART_USR_RFNE       (BIT(3))
144 #define UART_USR_TFE        (BIT(2))
145 #define UART_USR_TFNF       (BIT(1))
146 #define UART_USR_BUSY       (BIT(0))
147 /* Halt Register */
148 #define UART_HALT_LCRUP     (BIT(2))
149 #define UART_HALT_FORCECFG  (BIT(1))
150 #define UART_HALT_HTX       (BIT(0))
151 /* RS485 Control and Status Register */
152 #define UART_RS485_RXBFA    (BIT(3))
153 #define UART_RS485_RXAFA    (BIT(2))
154 
155 #ifdef __cplusplus
156 }
157 #endif
158 #endif /* __UART_I_H__ */
159