1 /*
2 * Copyright (c) 2001 by David Brownell
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19 /* this file is part of ehci-hcd.c */
20
21 /*-------------------------------------------------------------------------*/
22
23 /*
24 * There's basically three types of memory:
25 * - data used only by the HCD ... kmalloc is fine
26 * - async and periodic schedules, shared by HC and HCD ... these
27 * need to use dma_pool or dma_alloc_coherent
28 * - driver buffers, read/written by HC ... single shot DMA mapped
29 *
30 * There's also "register" data (e.g. PCI or SOC), which is memory mapped.
31 * No memory seen by this driver is pageable.
32 */
33
34 /*-------------------------------------------------------------------------*/
35
36 /* Allocate the key transfer structures from the previously allocated pool */
37
ehci_qtd_init(struct ehci_hcd * ehci,struct ehci_qtd * qtd,dma_addr_t dma)38 static inline void ehci_qtd_init(struct ehci_hcd *ehci, struct ehci_qtd *qtd,
39 dma_addr_t dma)
40 {
41 memset(qtd, 0, sizeof *qtd);
42 qtd->qtd_dma = dma;
43 qtd->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
44 qtd->hw_next = EHCI_LIST_END(ehci);
45 qtd->hw_alt_next = EHCI_LIST_END(ehci);
46 INIT_LIST_HEAD(&qtd->qtd_list);
47 }
48
ehci_qtd_alloc(struct ehci_hcd * ehci,gfp_t flags)49 static struct ehci_qtd *ehci_qtd_alloc (struct ehci_hcd *ehci, gfp_t flags)
50 {
51 struct ehci_qtd *qtd;
52 dma_addr_t dma;
53
54 //qtd = dma_pool_alloc (ehci->qtd_pool, flags, &dma);
55 qtd = usb_dma_malloc(sizeof(struct ehci_qtd), &dma);
56 if (qtd != NULL) {
57 EHCI_DEBUG_PRINTF("qtd virt = %p, phys = 0x%lx", qtd, dma);
58 ehci_qtd_init(ehci, qtd, dma);
59 }
60 return qtd;
61 }
62
ehci_qtd_free(struct ehci_hcd * ehci,struct ehci_qtd * qtd)63 static inline void ehci_qtd_free (struct ehci_hcd *ehci, struct ehci_qtd *qtd)
64 {
65 //dma_pool_free (ehci->qtd_pool, qtd, qtd->qtd_dma);
66 usb_dma_free(qtd, qtd->qtd_dma);
67 }
68
69
qh_destroy(struct ehci_hcd * ehci,struct ehci_qh * qh)70 static void qh_destroy(struct ehci_hcd *ehci, struct ehci_qh *qh)
71 {
72 /* clean qtds first, and know this is not linked */
73 if (!list_empty (&qh->qtd_list) || qh->qh_next.ptr) {
74 ehci_dbg ("unused qh not empty!\n");
75 }
76 if (qh->dummy)
77 ehci_qtd_free (ehci, qh->dummy);
78 //dma_pool_free(ehci->qh_pool, qh->hw, qh->qh_dma);
79 usb_dma_free((void *)qh->hw, qh->qh_dma);
80 hal_free(qh);
81 }
82
ehci_qh_alloc(struct ehci_hcd * ehci)83 static struct ehci_qh *ehci_qh_alloc (struct ehci_hcd *ehci)
84 {
85 struct ehci_qh *qh;
86 dma_addr_t dma;
87
88 qh = hal_malloc(sizeof *qh);
89 if (!qh)
90 goto done;
91 //qh->hw = (struct ehci_qh_hw *)
92 // dma_pool_alloc(ehci->qh_pool, flags, &dma);
93 qh->hw = (struct ehci_qh_hw *)
94 usb_dma_malloc(sizeof(struct ehci_qh_hw), &dma);
95 if (!qh->hw)
96 goto fail;
97 memset(qh->hw, 0, sizeof *qh->hw);
98 qh->qh_dma = dma;
99 INIT_LIST_HEAD (&qh->qtd_list);
100 INIT_LIST_HEAD(&qh->unlink_node);
101
102 /* dummy td enables safe urb queuing */
103 qh->dummy = ehci_qtd_alloc (ehci, 0);
104 if (qh->dummy == NULL) {
105 ehci_dbg ("no dummy td\n");
106 goto fail1;
107 }
108 done:
109 return qh;
110 fail1:
111 //dma_pool_free(ehci->qh_pool, qh->hw, qh->qh_dma);
112 usb_dma_free(qh->hw, qh->qh_dma);
113 fail:
114 //kfree(qh);
115 hal_free(qh);
116 return NULL;
117 }
118
119 /*-------------------------------------------------------------------------*/
120
121 /* The queue heads and transfer descriptors are managed from pools tied
122 * to each of the "per device" structures.
123 * This is the initialisation and cleanup code.
124 */
125
ehci_mem_cleanup(struct ehci_hcd * ehci)126 static void ehci_mem_cleanup (struct ehci_hcd *ehci)
127 {
128 if (ehci->async)
129 qh_destroy(ehci, ehci->async);
130 ehci->async = NULL;
131
132 //if (ehci->dummy)
133 // qh_destroy(ehci, ehci->dummy);
134 //ehci->dummy = NULL;
135
136 /* DMA consistent memory and pools */
137 //dma_pool_destroy(ehci->qtd_pool);
138 //ehci->qtd_pool = NULL;
139 //dma_pool_destroy(ehci->qh_pool);
140 //ehci->qh_pool = NULL;
141 //dma_pool_destroy(ehci->itd_pool);
142 //ehci->itd_pool = NULL;
143 //dma_pool_destroy(ehci->sitd_pool);
144 //ehci->sitd_pool = NULL;
145
146 if (ehci->periodic)
147 usb_dma_free(ehci->periodic, ehci->periodic_dma);
148 //dma_free_coherent (ehci_to_hcd(ehci)->self.controller,
149 // ehci->periodic_size * sizeof (u32),
150 // ehci->periodic, ehci->periodic_dma);
151 ehci->periodic = NULL;
152
153 /* shadow periodic table */
154 hal_free(ehci->pshadow);
155 ehci->pshadow = NULL;
156 }
157
158 /* remember to add cleanup code (above) if you add anything here */
ehci_mem_init(struct ehci_hcd * ehci)159 static int ehci_mem_init (struct ehci_hcd *ehci)
160 {
161 int i;
162
163 /* QTDs for control/bulk/intr transfers */
164 //ehci->qtd_pool = dma_pool_create ("ehci_qtd",
165 // ehci_to_hcd(ehci)->self.controller,
166 // sizeof (struct ehci_qtd),
167 // 32 /* byte alignment (for hw parts) */,
168 // 4096 /* can't cross 4K */);
169 //if (!ehci->qtd_pool) {
170 // goto fail;
171 //}
172
173 ///* QHs for control/bulk/intr transfers */
174 //ehci->qh_pool = dma_pool_create ("ehci_qh",
175 // ehci_to_hcd(ehci)->self.controller,
176 // sizeof(struct ehci_qh_hw),
177 // 32 /* byte alignment (for hw parts) */,
178 // 4096 /* can't cross 4K */);
179 //if (!ehci->qh_pool) {
180 // goto fail;
181 //}
182 ehci->async = ehci_qh_alloc (ehci);
183 if (!ehci->async) {
184 goto fail;
185 }
186
187 /* ITD for high speed ISO transfers */
188 //ehci->itd_pool = dma_pool_create ("ehci_itd",
189 // ehci_to_hcd(ehci)->self.controller,
190 // sizeof (struct ehci_itd),
191 // 32 /* byte alignment (for hw parts) */,
192 // 4096 /* can't cross 4K */);
193 //if (!ehci->itd_pool) {
194 // goto fail;
195 //}
196
197 ///* SITD for full/low speed split ISO transfers */
198 //ehci->sitd_pool = dma_pool_create ("ehci_sitd",
199 // ehci_to_hcd(ehci)->self.controller,
200 // sizeof (struct ehci_sitd),
201 // 32 /* byte alignment (for hw parts) */,
202 // 4096 /* can't cross 4K */);
203 //if (!ehci->sitd_pool) {
204 // goto fail;
205 //}
206
207 /* Hardware periodic table */
208 //ehci->periodic = (__le32 *)
209 // dma_alloc_coherent (ehci_to_hcd(ehci)->self.controller,
210 // ehci->periodic_size * sizeof(__le32),
211 // &ehci->periodic_dma, flags);
212 ehci->periodic = usb_dma_malloc(ehci->periodic_size * sizeof(uint32_t),
213 (dma_addr_t *)&ehci->periodic_dma);
214 if (ehci->periodic == NULL) {
215 goto fail;
216 }
217
218 //if (ehci->use_dummy_qh) {
219 // struct ehci_qh_hw *hw;
220 // ehci->dummy = ehci_qh_alloc(ehci, flags);
221 // if (!ehci->dummy)
222 // goto fail;
223
224 // hw = ehci->dummy->hw;
225 // hw->hw_next = EHCI_LIST_END(ehci);
226 // hw->hw_qtd_next = EHCI_LIST_END(ehci);
227 // hw->hw_alt_next = EHCI_LIST_END(ehci);
228 // ehci->dummy->hw = hw;
229
230 // for (i = 0; i < ehci->periodic_size; i++)
231 // ehci->periodic[i] = cpu_to_hc32(ehci,
232 // ehci->dummy->qh_dma);
233 //} else {
234 for (i = 0; i < ehci->periodic_size; i++)
235 ehci->periodic[i] = EHCI_LIST_END(ehci);
236 //}
237
238 /* software shadow of hardware table */
239 //ehci->pshadow = kcalloc(ehci->periodic_size, sizeof(void *), flags);
240 ehci->pshadow = hal_malloc((ehci->periodic_size) * (sizeof(void *)));
241 memset(ehci->pshadow, 0, (ehci->periodic_size) * (sizeof(void *)));
242 if (ehci->pshadow != NULL)
243 return 0;
244
245 fail:
246 ehci_dbg ("couldn't init memory\n");
247 ehci_mem_cleanup (ehci);
248 return -ENOMEM;
249 }
250