1 #if 0 2 /* 3 * OHCI HCD (Host Controller Driver) for USB. 4 * 5 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> 6 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net> 7 * 8 * This file is licenced under the GPL. 9 */ 10 11 /* 12 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to 13 * __leXX (normally) or __beXX (given OHCI_BIG_ENDIAN), depending on the 14 * host controller implementation. 15 */ 16 typedef __u32 __bitwise __hc32; 17 typedef __u16 __bitwise __hc16; 18 19 /* 20 * OHCI Endpoint Descriptor (ED) ... holds TD queue 21 * See OHCI spec, section 4.2 22 * 23 * This is a "Queue Head" for those transfers, which is why 24 * both EHCI and UHCI call similar structures a "QH". 25 */ 26 struct ed { 27 /* first fields are hardware-specified */ 28 __hc32 hwINFO; /* endpoint config bitmap */ 29 /* info bits defined by hcd */ 30 #define ED_DEQUEUE (1 << 27) 31 /* info bits defined by the hardware */ 32 #define ED_ISO (1 << 15) 33 #define ED_SKIP (1 << 14) 34 #define ED_LOWSPEED (1 << 13) 35 #define ED_OUT (0x01 << 11) 36 #define ED_IN (0x02 << 11) 37 __hc32 hwTailP; /* tail of TD list */ 38 __hc32 hwHeadP; /* head of TD list (hc r/w) */ 39 #define ED_C (0x02) /* toggle carry */ 40 #define ED_H (0x01) /* halted */ 41 __hc32 hwNextED; /* next ED in list */ 42 43 /* rest are purely for the driver's use */ 44 dma_addr_t dma; /* addr of ED */ 45 struct td *dummy; /* next TD to activate */ 46 47 /* host's view of schedule */ 48 struct ed *ed_next; /* on schedule or rm_list */ 49 struct ed *ed_prev; /* for non-interrupt EDs */ 50 struct list_head td_list; /* "shadow list" of our TDs */ 51 struct list_head in_use_list; 52 53 /* create --> IDLE --> OPER --> ... --> IDLE --> destroy 54 * usually: OPER --> UNLINK --> (IDLE | OPER) --> ... 55 */ 56 u8 state; /* ED_{IDLE,UNLINK,OPER} */ 57 #define ED_IDLE 0x00 /* NOT linked to HC */ 58 #define ED_UNLINK 0x01 /* being unlinked from hc */ 59 #define ED_OPER 0x02 /* IS linked to hc */ 60 61 u8 type; /* PIPE_{BULK,...} */ 62 63 /* periodic scheduling params (for intr and iso) */ 64 u8 branch; 65 u16 interval; 66 u16 load; 67 u16 last_iso; /* iso only */ 68 69 /* HC may see EDs on rm_list until next frame (frame_no == tick) */ 70 u16 tick; 71 72 /* Detect TDs not added to the done queue */ 73 unsigned takeback_wdh_cnt; 74 struct td *pending_td; 75 #define OKAY_TO_TAKEBACK(ohci, ed) \ 76 ((int) (ohci->wdh_cnt - ed->takeback_wdh_cnt) >= 0) 77 78 } __attribute__ ((aligned(16))); 79 80 #define ED_MASK ((u32)~0x0f) /* strip hw status in low addr bits */ 81 82 83 /* 84 * OHCI Transfer Descriptor (TD) ... one per transfer segment 85 * See OHCI spec, sections 4.3.1 (general = control/bulk/interrupt) 86 * and 4.3.2 (iso) 87 */ 88 struct td { 89 /* first fields are hardware-specified */ 90 __hc32 hwINFO; /* transfer info bitmask */ 91 92 /* hwINFO bits for both general and iso tds: */ 93 #define TD_CC 0xf0000000 /* condition code */ 94 #define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) 95 //#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) 96 #define TD_DI 0x00E00000 /* frames before interrupt */ 97 #define TD_DI_SET(X) (((X) & 0x07)<< 21) 98 /* these two bits are available for definition/use by HCDs in both 99 * general and iso tds ... others are available for only one type 100 */ 101 #define TD_DONE 0x00020000 /* retired to donelist */ 102 #define TD_ISO 0x00010000 /* copy of ED_ISO */ 103 104 /* hwINFO bits for general tds: */ 105 #define TD_EC 0x0C000000 /* error count */ 106 #define TD_T 0x03000000 /* data toggle state */ 107 #define TD_T_DATA0 0x02000000 /* DATA0 */ 108 #define TD_T_DATA1 0x03000000 /* DATA1 */ 109 #define TD_T_TOGGLE 0x00000000 /* uses ED_C */ 110 #define TD_DP 0x00180000 /* direction/pid */ 111 #define TD_DP_SETUP 0x00000000 /* SETUP pid */ 112 #define TD_DP_IN 0x00100000 /* IN pid */ 113 #define TD_DP_OUT 0x00080000 /* OUT pid */ 114 /* 0x00180000 rsvd */ 115 #define TD_R 0x00040000 /* round: short packets OK? */ 116 117 /* (no hwINFO #defines yet for iso tds) */ 118 119 __hc32 hwCBP; /* Current Buffer Pointer (or 0) */ 120 __hc32 hwNextTD; /* Next TD Pointer */ 121 __hc32 hwBE; /* Memory Buffer End Pointer */ 122 123 /* PSW is only for ISO. Only 1 PSW entry is used, but on 124 * big-endian PPC hardware that's the second entry. 125 */ 126 #define MAXPSW 2 127 __hc16 hwPSW [MAXPSW]; 128 129 /* rest are purely for the driver's use */ 130 __u8 index; 131 struct ed *ed; 132 struct td *td_hash; /* dma-->td hashtable */ 133 struct td *next_dl_td; 134 struct urb *urb; 135 136 dma_addr_t td_dma; /* addr of this TD */ 137 dma_addr_t data_dma; /* addr of data it points to */ 138 139 struct list_head td_list; /* "shadow list", TDs on same ED */ 140 } __attribute__ ((aligned(32))); /* c/b/i need 16; only iso needs 32 */ 141 142 #define TD_MASK ((u32)~0x1f) /* strip hw status in low addr bits */ 143 144 /* 145 * Hardware transfer status codes -- CC from td->hwINFO or td->hwPSW 146 */ 147 #define TD_CC_NOERROR 0x00 148 #define TD_CC_CRC 0x01 149 #define TD_CC_BITSTUFFING 0x02 150 #define TD_CC_DATATOGGLEM 0x03 151 #define TD_CC_STALL 0x04 152 #define TD_DEVNOTRESP 0x05 153 #define TD_PIDCHECKFAIL 0x06 154 #define TD_UNEXPECTEDPID 0x07 155 #define TD_DATAOVERRUN 0x08 156 #define TD_DATAUNDERRUN 0x09 157 /* 0x0A, 0x0B reserved for hardware */ 158 #define TD_BUFFEROVERRUN 0x0C 159 #define TD_BUFFERUNDERRUN 0x0D 160 /* 0x0E, 0x0F reserved for HCD */ 161 #define TD_NOTACCESSED 0x0F 162 163 164 /* map OHCI TD status codes (CC) to errno values */ 165 static const int cc_to_error [16] = { 166 /* No Error */ 0, 167 /* CRC Error */ -EILSEQ, 168 /* Bit Stuff */ -EPROTO, 169 /* Data Togg */ -EILSEQ, 170 /* Stall */ -EPIPE, 171 /* DevNotResp */ -ETIME, 172 /* PIDCheck */ -EPROTO, 173 /* UnExpPID */ -EPROTO, 174 /* DataOver */ -EOVERFLOW, 175 /* DataUnder */ -EREMOTEIO, 176 /* (for hw) */ -EIO, 177 /* (for hw) */ -EIO, 178 /* BufferOver */ -ECOMM, 179 /* BuffUnder */ -ENOSR, 180 /* (for HCD) */ -EALREADY, 181 /* (for HCD) */ -EALREADY 182 }; 183 184 185 /* 186 * The HCCA (Host Controller Communications Area) is a 256 byte 187 * structure defined section 4.4.1 of the OHCI spec. The HC is 188 * told the base address of it. It must be 256-byte aligned. 189 */ 190 struct ohci_hcca { 191 #define NUM_INTS 32 192 __hc32 int_table [NUM_INTS]; /* periodic schedule */ 193 194 /* 195 * OHCI defines u16 frame_no, followed by u16 zero pad. 196 * Since some processors can't do 16 bit bus accesses, 197 * portable access must be a 32 bits wide. 198 */ 199 __hc32 frame_no; /* current frame number */ 200 __hc32 done_head; /* info returned for an interrupt */ 201 u8 reserved_for_hc [116]; 202 u8 what [4]; /* spec only identifies 252 bytes :) */ 203 } __attribute__ ((aligned(256))); 204 205 /* 206 * This is the structure of the OHCI controller's memory mapped I/O region. 207 * You must use readl() and writel() (in <asm/io.h>) to access these fields!! 208 * Layout is in section 7 (and appendix B) of the spec. 209 */ 210 struct ohci_regs { 211 /* control and status registers (section 7.1) */ 212 __hc32 revision; 213 __hc32 control; 214 __hc32 cmdstatus; 215 __hc32 intrstatus; 216 __hc32 intrenable; 217 __hc32 intrdisable; 218 219 /* memory pointers (section 7.2) */ 220 __hc32 hcca; 221 __hc32 ed_periodcurrent; 222 __hc32 ed_controlhead; 223 __hc32 ed_controlcurrent; 224 __hc32 ed_bulkhead; 225 __hc32 ed_bulkcurrent; 226 __hc32 donehead; 227 228 /* frame counters (section 7.3) */ 229 __hc32 fminterval; 230 __hc32 fmremaining; 231 __hc32 fmnumber; 232 __hc32 periodicstart; 233 __hc32 lsthresh; 234 235 /* Root hub ports (section 7.4) */ 236 struct ohci_roothub_regs { 237 __hc32 a; 238 __hc32 b; 239 __hc32 status; 240 #define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports (RH_A_NDP) */ 241 __hc32 portstatus [MAX_ROOT_PORTS]; 242 } roothub; 243 244 /* and optional "legacy support" registers (appendix B) at 0x0100 */ 245 246 } __attribute__ ((aligned(32))); 247 248 249 /* OHCI CONTROL AND STATUS REGISTER MASKS */ 250 251 /* 252 * HcControl (control) register masks 253 */ 254 #define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ 255 #define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ 256 #define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ 257 #define OHCI_CTRL_CLE (1 << 4) /* control list enable */ 258 #define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ 259 #define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ 260 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ 261 #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ 262 #define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ 263 264 /* pre-shifted values for HCFS */ 265 # define OHCI_USB_RESET (0 << 6) 266 # define OHCI_USB_RESUME (1 << 6) 267 # define OHCI_USB_OPER (2 << 6) 268 # define OHCI_USB_SUSPEND (3 << 6) 269 270 /* 271 * HcCommandStatus (cmdstatus) register masks 272 */ 273 #define OHCI_HCR (1 << 0) /* host controller reset */ 274 #define OHCI_CLF (1 << 1) /* control list filled */ 275 #define OHCI_BLF (1 << 2) /* bulk list filled */ 276 #define OHCI_OCR (1 << 3) /* ownership change request */ 277 #define OHCI_SOC (3 << 16) /* scheduling overrun count */ 278 279 /* 280 * masks used with interrupt registers: 281 * HcInterruptStatus (intrstatus) 282 * HcInterruptEnable (intrenable) 283 * HcInterruptDisable (intrdisable) 284 */ 285 #define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ 286 #define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ 287 #define OHCI_INTR_SF (1 << 2) /* start frame */ 288 #define OHCI_INTR_RD (1 << 3) /* resume detect */ 289 #define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ 290 #define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ 291 #define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ 292 #define OHCI_INTR_OC (1 << 30) /* ownership change */ 293 #define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ 294 295 296 /* OHCI ROOT HUB REGISTER MASKS */ 297 298 /* roothub.portstatus [i] bits */ 299 #define RH_PS_CCS 0x00000001 /* current connect status */ 300 #define RH_PS_PES 0x00000002 /* port enable status*/ 301 #define RH_PS_PSS 0x00000004 /* port suspend status */ 302 #define RH_PS_POCI 0x00000008 /* port over current indicator */ 303 #define RH_PS_PRS 0x00000010 /* port reset status */ 304 #define RH_PS_PPS 0x00000100 /* port power status */ 305 #define RH_PS_LSDA 0x00000200 /* low speed device attached */ 306 #define RH_PS_CSC 0x00010000 /* connect status change */ 307 #define RH_PS_PESC 0x00020000 /* port enable status change */ 308 #define RH_PS_PSSC 0x00040000 /* port suspend status change */ 309 #define RH_PS_OCIC 0x00080000 /* over current indicator change */ 310 #define RH_PS_PRSC 0x00100000 /* port reset status change */ 311 312 /* roothub.status bits */ 313 #define RH_HS_LPS 0x00000001 /* local power status */ 314 #define RH_HS_OCI 0x00000002 /* over current indicator */ 315 #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ 316 #define RH_HS_LPSC 0x00010000 /* local power status change */ 317 #define RH_HS_OCIC 0x00020000 /* over current indicator change */ 318 #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ 319 320 /* roothub.b masks */ 321 #define RH_B_DR 0x0000ffff /* device removable flags */ 322 #define RH_B_PPCM 0xffff0000 /* port power control mask */ 323 324 /* roothub.a masks */ 325 #define RH_A_NDP (0xff << 0) /* number of downstream ports */ 326 #define RH_A_PSM (1 << 8) /* power switching mode */ 327 #define RH_A_NPS (1 << 9) /* no power switching */ 328 #define RH_A_DT (1 << 10) /* device type (mbz) */ 329 #define RH_A_OCPM (1 << 11) /* over current protection mode */ 330 #define RH_A_NOCP (1 << 12) /* no over current protection */ 331 #define RH_A_POTPGT (0xff << 24) /* power on to power good time */ 332 333 334 /* hcd-private per-urb state */ 335 typedef struct urb_priv { 336 struct ed *ed; 337 u16 length; // # tds in this request 338 u16 td_cnt; // tds already serviced 339 struct list_head pending; 340 struct td *td [0]; // all TDs in this request 341 342 } urb_priv_t; 343 344 #define TD_HASH_SIZE 64 /* power'o'two */ 345 // sizeof (struct td) ~= 64 == 2^6 ... 346 #define TD_HASH_FUNC(td_dma) ((td_dma ^ (td_dma >> 6)) % TD_HASH_SIZE) 347 348 349 /* 350 * This is the full ohci controller description 351 * 352 * Note how the "proper" USB information is just 353 * a subset of what the full implementation needs. (Linus) 354 */ 355 356 enum ohci_rh_state { 357 OHCI_RH_HALTED, 358 OHCI_RH_SUSPENDED, 359 OHCI_RH_RUNNING 360 }; 361 362 struct ohci_hcd { 363 spinlock_t lock; 364 365 /* 366 * I/O memory used to communicate with the HC (dma-consistent) 367 */ 368 struct ohci_regs __iomem *regs; 369 370 /* 371 * main memory used to communicate with the HC (dma-consistent). 372 * hcd adds to schedule for a live hc any time, but removals finish 373 * only at the start of the next frame. 374 */ 375 struct ohci_hcca *hcca; 376 dma_addr_t hcca_dma; 377 378 struct ed *ed_rm_list; /* to be removed */ 379 380 struct ed *ed_bulktail; /* last in bulk list */ 381 struct ed *ed_controltail; /* last in ctrl list */ 382 struct ed *periodic [NUM_INTS]; /* shadow int_table */ 383 384 void (*start_hnp)(struct ohci_hcd *ohci); 385 386 /* 387 * memory management for queue data structures 388 */ 389 struct dma_pool *td_cache; 390 struct dma_pool *ed_cache; 391 struct td *td_hash [TD_HASH_SIZE]; 392 struct td *dl_start, *dl_end; /* the done list */ 393 struct list_head pending; 394 struct list_head eds_in_use; /* all EDs with at least 1 TD */ 395 396 /* 397 * driver state 398 */ 399 enum ohci_rh_state rh_state; 400 int num_ports; 401 int load [NUM_INTS]; 402 u32 hc_control; /* copy of hc control reg */ 403 unsigned long next_statechange; /* suspend/resume */ 404 u32 fminterval; /* saved register */ 405 unsigned autostop:1; /* rh auto stopping/stopped */ 406 unsigned working:1; 407 unsigned restart_work:1; 408 409 unsigned long flags; /* for HC bugs */ 410 #define OHCI_QUIRK_AMD756 0x01 /* erratum #4 */ 411 #define OHCI_QUIRK_SUPERIO 0x02 /* natsemi */ 412 #define OHCI_QUIRK_INITRESET 0x04 /* SiS, OPTi, ... */ 413 #define OHCI_QUIRK_BE_DESC 0x08 /* BE descriptors */ 414 #define OHCI_QUIRK_BE_MMIO 0x10 /* BE registers */ 415 #define OHCI_QUIRK_ZFMICRO 0x20 /* Compaq ZFMicro chipset*/ 416 #define OHCI_QUIRK_NEC 0x40 /* lost interrupts */ 417 #define OHCI_QUIRK_FRAME_NO 0x80 /* no big endian frame_no shift */ 418 #define OHCI_QUIRK_HUB_POWER 0x100 /* distrust firmware power/oc setup */ 419 #define OHCI_QUIRK_AMD_PLL 0x200 /* AMD PLL quirk*/ 420 #define OHCI_QUIRK_AMD_PREFETCH 0x400 /* pre-fetch for ISO transfer */ 421 #define OHCI_QUIRK_GLOBAL_SUSPEND 0x800 /* must suspend ports */ 422 #define OHCI_QUIRK_QEMU 0x1000 /* relax timing expectations */ 423 424 // there are also chip quirks/bugs in init logic 425 426 unsigned prev_frame_no; 427 unsigned wdh_cnt, prev_wdh_cnt; 428 u32 prev_donehead; 429 struct timer_list io_watchdog; 430 431 struct work_struct nec_work; /* Worker for NEC quirk */ 432 433 struct dentry *debug_dir; 434 struct dentry *debug_async; 435 struct dentry *debug_periodic; 436 struct dentry *debug_registers; 437 438 /* platform-specific data -- must come last */ 439 unsigned long priv[0] __aligned(sizeof(s64)); 440 441 }; 442 443 #ifdef CONFIG_PCI 444 static inline int quirk_nec(struct ohci_hcd *ohci) 445 { 446 return ohci->flags & OHCI_QUIRK_NEC; 447 } 448 static inline int quirk_zfmicro(struct ohci_hcd *ohci) 449 { 450 return ohci->flags & OHCI_QUIRK_ZFMICRO; 451 } 452 static inline int quirk_amdiso(struct ohci_hcd *ohci) 453 { 454 return ohci->flags & OHCI_QUIRK_AMD_PLL; 455 } 456 static inline int quirk_amdprefetch(struct ohci_hcd *ohci) 457 { 458 return ohci->flags & OHCI_QUIRK_AMD_PREFETCH; 459 } 460 #else 461 static inline int quirk_nec(struct ohci_hcd *ohci) 462 { 463 return 0; 464 } 465 static inline int quirk_zfmicro(struct ohci_hcd *ohci) 466 { 467 return 0; 468 } 469 static inline int quirk_amdiso(struct ohci_hcd *ohci) 470 { 471 return 0; 472 } 473 static inline int quirk_amdprefetch(struct ohci_hcd *ohci) 474 { 475 return 0; 476 } 477 #endif 478 479 /* convert between an hcd pointer and the corresponding ohci_hcd */ 480 static inline struct ohci_hcd *hcd_to_ohci (struct usb_hcd *hcd) 481 { 482 return (struct ohci_hcd *) (hcd->hcd_priv); 483 } 484 static inline struct usb_hcd *ohci_to_hcd (const struct ohci_hcd *ohci) 485 { 486 return container_of ((void *) ohci, struct usb_hcd, hcd_priv); 487 } 488 489 /*-------------------------------------------------------------------------*/ 490 491 #define ohci_dbg(ohci, fmt, args...) \ 492 dev_dbg (ohci_to_hcd(ohci)->self.controller , fmt , ## args ) 493 #define ohci_err(ohci, fmt, args...) \ 494 dev_err (ohci_to_hcd(ohci)->self.controller , fmt , ## args ) 495 #define ohci_info(ohci, fmt, args...) \ 496 dev_info (ohci_to_hcd(ohci)->self.controller , fmt , ## args ) 497 #define ohci_warn(ohci, fmt, args...) \ 498 dev_warn (ohci_to_hcd(ohci)->self.controller , fmt , ## args ) 499 500 /*-------------------------------------------------------------------------*/ 501 502 /* 503 * While most USB host controllers implement their registers and 504 * in-memory communication descriptors in little-endian format, 505 * a minority (notably the IBM STB04XXX and the Motorola MPC5200 506 * processors) implement them in big endian format. 507 * 508 * In addition some more exotic implementations like the Toshiba 509 * Spider (aka SCC) cell southbridge are "mixed" endian, that is, 510 * they have a different endianness for registers vs. in-memory 511 * descriptors. 512 * 513 * This attempts to support either format at compile time without a 514 * runtime penalty, or both formats with the additional overhead 515 * of checking a flag bit. 516 * 517 * That leads to some tricky Kconfig rules howevber. There are 518 * different defaults based on some arch/ppc platforms, though 519 * the basic rules are: 520 * 521 * Controller type Kconfig options needed 522 * --------------- ---------------------- 523 * little endian CONFIG_USB_OHCI_LITTLE_ENDIAN 524 * 525 * fully big endian CONFIG_USB_OHCI_BIG_ENDIAN_DESC _and_ 526 * CONFIG_USB_OHCI_BIG_ENDIAN_MMIO 527 * 528 * mixed endian CONFIG_USB_OHCI_LITTLE_ENDIAN _and_ 529 * CONFIG_USB_OHCI_BIG_ENDIAN_{MMIO,DESC} 530 * 531 * (If you have a mixed endian controller, you -must- also define 532 * CONFIG_USB_OHCI_LITTLE_ENDIAN or things will not work when building 533 * both your mixed endian and a fully big endian controller support in 534 * the same kernel image). 535 */ 536 537 #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_DESC 538 #ifdef CONFIG_USB_OHCI_LITTLE_ENDIAN 539 #define big_endian_desc(ohci) (ohci->flags & OHCI_QUIRK_BE_DESC) 540 #else 541 #define big_endian_desc(ohci) 1 /* only big endian */ 542 #endif 543 #else 544 #define big_endian_desc(ohci) 0 /* only little endian */ 545 #endif 546 547 #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO 548 #ifdef CONFIG_USB_OHCI_LITTLE_ENDIAN 549 #define big_endian_mmio(ohci) (ohci->flags & OHCI_QUIRK_BE_MMIO) 550 #else 551 #define big_endian_mmio(ohci) 1 /* only big endian */ 552 #endif 553 #else 554 #define big_endian_mmio(ohci) 0 /* only little endian */ 555 #endif 556 557 /* 558 * Big-endian read/write functions are arch-specific. 559 * Other arches can be added if/when they're needed. 560 * 561 */ 562 static inline unsigned int _ohci_readl (const struct ohci_hcd *ohci, 563 __hc32 __iomem * regs) 564 { 565 #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO 566 return big_endian_mmio(ohci) ? 567 readl_be (regs) : 568 readl (regs); 569 #else 570 return readl (regs); 571 #endif 572 } 573 574 static inline void _ohci_writel (const struct ohci_hcd *ohci, 575 const unsigned int val, __hc32 __iomem *regs) 576 { 577 #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO 578 big_endian_mmio(ohci) ? 579 writel_be (val, regs) : 580 writel (val, regs); 581 #else 582 writel (val, regs); 583 #endif 584 } 585 586 #define ohci_readl(o,r) _ohci_readl(o,r) 587 #define ohci_writel(o,v,r) _ohci_writel(o,v,r) 588 589 590 /*-------------------------------------------------------------------------*/ 591 592 /* cpu to ohci */ 593 static inline __hc16 cpu_to_hc16 (const struct ohci_hcd *ohci, const u16 x) 594 { 595 return big_endian_desc(ohci) ? 596 (__force __hc16)cpu_to_be16(x) : 597 (__force __hc16)cpu_to_le16(x); 598 } 599 600 static inline __hc16 cpu_to_hc16p (const struct ohci_hcd *ohci, const u16 *x) 601 { 602 return big_endian_desc(ohci) ? 603 cpu_to_be16p(x) : 604 cpu_to_le16p(x); 605 } 606 607 static inline __hc32 cpu_to_hc32 (const struct ohci_hcd *ohci, const u32 x) 608 { 609 return big_endian_desc(ohci) ? 610 (__force __hc32)cpu_to_be32(x) : 611 (__force __hc32)cpu_to_le32(x); 612 } 613 614 static inline __hc32 cpu_to_hc32p (const struct ohci_hcd *ohci, const u32 *x) 615 { 616 return big_endian_desc(ohci) ? 617 cpu_to_be32p(x) : 618 cpu_to_le32p(x); 619 } 620 621 /* ohci to cpu */ 622 static inline u16 hc16_to_cpu (const struct ohci_hcd *ohci, const __hc16 x) 623 { 624 return big_endian_desc(ohci) ? 625 be16_to_cpu((__force __be16)x) : 626 le16_to_cpu((__force __le16)x); 627 } 628 629 static inline u16 hc16_to_cpup (const struct ohci_hcd *ohci, const __hc16 *x) 630 { 631 return big_endian_desc(ohci) ? 632 be16_to_cpup((__force __be16 *)x) : 633 le16_to_cpup((__force __le16 *)x); 634 } 635 636 static inline u32 hc32_to_cpu (const struct ohci_hcd *ohci, const __hc32 x) 637 { 638 return big_endian_desc(ohci) ? 639 be32_to_cpu((__force __be32)x) : 640 le32_to_cpu((__force __le32)x); 641 } 642 643 static inline u32 hc32_to_cpup (const struct ohci_hcd *ohci, const __hc32 *x) 644 { 645 return big_endian_desc(ohci) ? 646 be32_to_cpup((__force __be32 *)x) : 647 le32_to_cpup((__force __le32 *)x); 648 } 649 650 /*-------------------------------------------------------------------------*/ 651 652 /* 653 * The HCCA frame number is 16 bits, but is accessed as 32 bits since not all 654 * hardware handles 16 bit reads. Depending on the SoC implementation, the 655 * frame number can wind up in either bits [31:16] (default) or 656 * [15:0] (OHCI_QUIRK_FRAME_NO) on big endian hosts. 657 * 658 * Somewhat similarly, the 16-bit PSW fields in a transfer descriptor are 659 * reordered on BE. 660 */ 661 662 static inline u16 ohci_frame_no(const struct ohci_hcd *ohci) 663 { 664 u32 tmp; 665 if (big_endian_desc(ohci)) { 666 tmp = be32_to_cpup((__force __be32 *)&ohci->hcca->frame_no); 667 if (!(ohci->flags & OHCI_QUIRK_FRAME_NO)) 668 tmp >>= 16; 669 } else 670 tmp = le32_to_cpup((__force __le32 *)&ohci->hcca->frame_no); 671 672 return (u16)tmp; 673 } 674 675 static inline __hc16 *ohci_hwPSWp(const struct ohci_hcd *ohci, 676 const struct td *td, int index) 677 { 678 return (__hc16 *)(big_endian_desc(ohci) ? 679 &td->hwPSW[index ^ 1] : &td->hwPSW[index]); 680 } 681 682 static inline u16 ohci_hwPSW(const struct ohci_hcd *ohci, 683 const struct td *td, int index) 684 { 685 return hc16_to_cpup(ohci, ohci_hwPSWp(ohci, td, index)); 686 } 687 688 /*-------------------------------------------------------------------------*/ 689 690 #define FI 0x2edf /* 12000 bits per frame (-1) */ 691 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7)) 692 #define FIT (1 << 31) 693 #define LSTHRESH 0x628 /* lowspeed bit threshold */ 694 695 static inline void periodic_reinit (struct ohci_hcd *ohci) 696 { 697 u32 fi = ohci->fminterval & 0x03fff; 698 u32 fit = ohci_readl(ohci, &ohci->regs->fminterval) & FIT; 699 700 ohci_writel (ohci, (fit ^ FIT) | ohci->fminterval, 701 &ohci->regs->fminterval); 702 ohci_writel (ohci, ((9 * fi) / 10) & 0x3fff, 703 &ohci->regs->periodicstart); 704 } 705 706 /* AMD-756 (D2 rev) reports corrupt register contents in some cases. 707 * The erratum (#4) description is incorrect. AMD's workaround waits 708 * till some bits (mostly reserved) are clear; ok for all revs. 709 */ 710 #define read_roothub(hc, register, mask) ({ \ 711 u32 temp = ohci_readl (hc, &hc->regs->roothub.register); \ 712 if (temp == -1) \ 713 hc->rh_state = OHCI_RH_HALTED; \ 714 else if (hc->flags & OHCI_QUIRK_AMD756) \ 715 while (temp & mask) \ 716 temp = ohci_readl (hc, &hc->regs->roothub.register); \ 717 temp; }) 718 719 static inline u32 roothub_a (struct ohci_hcd *hc) 720 { return read_roothub (hc, a, 0xfc0fe000); } 721 static inline u32 roothub_b (struct ohci_hcd *hc) 722 { return ohci_readl (hc, &hc->regs->roothub.b); } 723 static inline u32 roothub_status (struct ohci_hcd *hc) 724 { return ohci_readl (hc, &hc->regs->roothub.status); } 725 static inline u32 roothub_portstatus (struct ohci_hcd *hc, int i) 726 { return read_roothub (hc, portstatus [i], 0xffe0fce0); } 727 728 /* Declarations of things exported for use by ohci platform drivers */ 729 730 struct ohci_driver_overrides { 731 const char *product_desc; 732 size_t extra_priv_size; 733 int (*reset)(struct usb_hcd *hcd); 734 }; 735 736 extern void ohci_init_driver(struct hc_driver *drv, 737 const struct ohci_driver_overrides *over); 738 extern int ohci_restart(struct ohci_hcd *ohci); 739 extern int ohci_setup(struct usb_hcd *hcd); 740 extern int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup); 741 extern int ohci_resume(struct usb_hcd *hcd, bool hibernated); 742 extern int ohci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, 743 u16 wIndex, char *buf, u16 wLength); 744 extern int ohci_hub_status_data(struct usb_hcd *hcd, char *buf); 745 #endif 746