1 /* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved. 2 3 * Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in 4 * the the People's Republic of China and other countries. 5 * All Allwinner Technology Co.,Ltd. trademarks are used with permission. 6 7 * DISCLAIMER 8 * THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT. 9 * IF YOU NEED TO INTEGRATE THIRD PART'S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.) 10 * IN ALLWINNER'SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN 11 * ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES. 12 * ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS 13 * COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE. 14 * YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PART'S TECHNOLOGY. 15 16 17 * THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT 18 * PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND, 19 * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING 20 * THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE 21 * OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. 22 * IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 29 * OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef __UDC_H__ 33 #define __UDC_H__ 34 35 #include <usb/ch9.h> 36 #include <usb/sunxi_hal_udc.h> 37 #include <hal_clk.h> 38 39 //#define UDC_LOG_DEBUG 40 #define log_udc_info(fmt, ...) hal_log_info("udc: "fmt, ##__VA_ARGS__) 41 #define log_udc_err(fmt, ...) hal_log_err("udc: "fmt, ##__VA_ARGS__) 42 #ifdef UDC_LOG_DEBUG 43 #define log_udc_dbg(fmt, ...) hal_log_debug("[%s %d]"fmt, __func__, __LINE__, ##__VA_ARGS__) 44 #else 45 #define log_udc_dbg(fmt, ...) 46 #endif 47 48 #define UDC_MAX_NUM_EP_TX 4 49 #define UDC_MAX_NUM_EP_RX 4 50 #define UDC_MAX_PACKET_SIZE_EP0 64 51 #define UDC_MAX_PACKET_SIZE_EP_BULK 512 52 #define UDC_MAX_PACKET_SIZE_EP_ISO 1024 53 #define UDC_MAX_PACKET_SIZE_EP_INT 512 54 #define UDC_MAX_NUM_STRING_DESC 12 55 56 57 typedef enum { 58 UDC_IO_TYPE_PIO = 0, 59 UDC_IO_TYPE_DMA, 60 } udc_io_type_t; 61 62 typedef enum { 63 UDC_EP_TYPE_EP0 = 0, 64 UDC_EP_TYPE_TX, 65 UDC_EP_TYPE_RX, 66 } udc_ep_type_t; 67 68 typedef enum { 69 UDC_EP0_IDLE = 0, 70 UDC_EP0_IN_DATA_PHASE, 71 UDC_EP0_OUT_DATA_PHASE, 72 UDC_EP0_END_XFER, 73 UDC_EP0_STALL, 74 } udc_ep0_state_t; 75 76 typedef enum { 77 UDC_SPEED_UNKNOWN = 0, /* enumerating */ 78 UDC_SPEED_LOW, UDC_SPEED_FULL, /* usb 1.1 */ 79 UDC_SPEED_HIGH, /* usb 2.0 */ 80 UDC_SPEED_WIRELESS, /* wireless (usb 2.5) */ 81 UDC_SPEED_SUPER, /* usb 3.0 */ 82 UDC_SPEED_SUPER_PLUS, /* usb 3.1 */ 83 } udc_speed_t; 84 85 typedef struct { 86 uint8_t ep_addr; 87 uint32_t fifo_addr; 88 uint32_t fifo_size; 89 uint8_t double_fifo; 90 } udc_fifo_t; 91 92 typedef struct { 93 uint8_t ep_addr; 94 void *pdata; 95 uint32_t data_len; 96 uint32_t data_actual; 97 uint32_t maxpacket; 98 } udc_ep_t; 99 100 typedef struct { 101 uint8_t ep0state; 102 uint8_t address; 103 udc_speed_t speed; 104 105 struct usb_ctrlrequest crq; 106 uint8_t req_std; 107 struct usb_device_descriptor *device_desc; 108 void *config_desc; 109 uint32_t config_desc_len; 110 struct usb_string_descriptor *string_desc[UDC_MAX_NUM_STRING_DESC]; 111 uint32_t string_desc_num; 112 113 udc_ep_t ep0; 114 udc_ep_t epin[UDC_MAX_NUM_EP_TX]; 115 udc_ep_t epout[UDC_MAX_NUM_EP_RX]; 116 117 udc_callback_t callback; 118 } udc_priv_t; 119 120 typedef struct { 121 uint32_t *usb_vbus; 122 123 uint32_t irq_no; 124 uint32_t irq_flag; 125 uint32_t drive_level; 126 127 hal_clk_id_t otg_clk_id; 128 hal_clk_id_t phy_clk_id; 129 uint32_t reset_phy_clk; 130 uint32_t reset_otg_clk; 131 hal_clk_t phy_clk; 132 hal_clk_t otg_clk; 133 134 struct reset_control *reset_phy; 135 struct reset_control *reset_otg; 136 } sunxi_udc_io_t; 137 138 #endif /*__UDC_H__*/ 139