1 /* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved. 2 3 * Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in 4 * the the People's Republic of China and other countries. 5 * All Allwinner Technology Co.,Ltd. trademarks are used with permission. 6 7 * DISCLAIMER 8 * THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT. 9 * IF YOU NEED TO INTEGRATE THIRD PART'S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.) 10 * IN ALLWINNER'SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN 11 * ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES. 12 * ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS 13 * COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE. 14 * YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PART'S TECHNOLOGY. 15 16 17 * THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT 18 * PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND, 19 * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING 20 * THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE 21 * OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. 22 * IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 29 * OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef __UDC_PLATFORM_H__ 33 #define __UDC_PLATFORM_H__ 34 35 #include <stdint.h> 36 37 #include <sunxi_hal_common.h> 38 #include <usb/ch9.h> 39 40 /* USB_POWER */ 41 #define USB_POWER_ENABLESUSPENDM (0x01) /* RW */ 42 #define USB_POWER_SUSPENDMODE (0x02) /* P: RO ; H: WO */ /*Read clear by the intr. register*/ 43 #define USB_POWER_RESUME (0x04) /* RW */ 44 #define USB_POWER_RESET (0x08) /* P: RO ; H: RW */ 45 #define USB_POWER_HSMODE (0x10) /* RO */ 46 #define USB_POWER_HSENAB (0x20) /* RW */ 47 #define USB_POWER_SOFTCONN (0x40) /* RW */ 48 #define USB_POWER_ISOUPDATE (0x80) /* RW */ 49 50 /* USB_INTRTX */ 51 #define USB_INTRTX_EP0 (0x01) /*RO*/ 52 #define USB_INTRTX_EP1 (0x02) /*RO*/ 53 #define USB_INTRTX_EP2 (0x04) /*RO*/ 54 #define USB_INTRTX_EP3 (0x08) /*RO*/ 55 #define USB_INTRTX_EP4 (0x10) /*RO*/ 56 57 /* USB_INTRRX */ 58 #define USB_INTRRX_EP1 (0x02) /*RO*/ 59 #define USB_INTRRX_EP2 (0x04) /*RO*/ 60 #define USB_INTRRX_EP3 (0x08) /*RO*/ 61 #define USB_INTRRX_EP4 (0x10) /*RO*/ 62 63 /* USB_INTRTXE & USB_INTRRXE */ 64 #define USB_INTRE_EPEN (0x01) /* RW */ 65 #define USB_INTRE_EPDIS (0x00) /* RW */ 66 67 /* USB_INTRUSB */ 68 #define USB_INTRUSB_SUSPEND (0x01) /*RO*/ 69 #define USB_INTRUSB_RESUME (0x02) /*RO*/ 70 #define USB_INTRUSB_RESET (0x04) /*RO*/ 71 #define USB_INTRUSB_BABBLE (0x04) /*RO*/ 72 #define USB_INTRUSB_SOF (0x08) /*RO*/ 73 #define USB_INTRUSB_CONN (0x10) /*RO*/ 74 #define USB_INTRUSB_DISCON (0x20) /*RO*/ 75 #define USB_INTRUSB_SESSREQ (0x40) /*RO*/ 76 #define USB_INTRUSB_VBUSERROR (0x80) /*RO*/ 77 78 /* USB_INTRUSBE */ 79 #define USB_INTRUSBE_SUSPEND (0x01) /*RW*/ 80 #define USB_INTRUSBE_RESUME (0x02) /*RW*/ 81 #define USB_INTRUSBE_RESET (0x04) /*RW*/ 82 #define USB_INTRUSBE_BABBLE (0x04) /*RW*/ 83 #define USB_INTRUSBE_SOF (0x08) /*RW*/ 84 #define USB_INTRUSBE_CONN (0x10) /*RW*/ 85 #define USB_INTRUSBE_DISCON (0x20) /*RW*/ 86 #define USB_INTRUSBE_SESSREQ (0x40) /*RW*/ 87 #define USB_INTRUSBE_VBUSERROR (0x80) /*RW*/ 88 89 /* USB_TESTMODE */ 90 #define USB_TESTMODE_TESTSE0NAK (0x01) /* RW */ 91 #define USB_TESTMODE_TESTJ (0x02) /* RW */ 92 #define USB_TESTMODE_TESTK (0x04) /* RW */ 93 #define USB_TESTMODE_TESTPACKET (0x08) /* RW */ 94 #define USB_TESTMODE_FORCEHS (0x10) /* RW */ 95 #define USB_TESTMODE_FORCEFS (0x20) /* RW */ 96 #define USB_TESTMODE_FIFOACCESS (0x40) /* WO, AC */ 97 #define USB_TESTMODE_FORCEHOST (0x80) /* RW */ 98 99 /* USB_DEVCTL */ 100 #define USB_DEVCTL_SESSION (0x01) /* RW */ 101 #define USB_DEVCTL_HOSTREQ (0x02) /* RW */ 102 #define USB_DEVCTL_HOSTMODE (0x04) /* RO */ 103 #define USB_DEVCTL_VBUS (0x18) /* RO */ 104 #define USB_DEVCTL_LSDEV (0x20) /* RO */ 105 #define USB_DEVCTL_FSDEV (0x40) /* RO */ 106 #define USB_DEVCTL_BDEVICE (0x80) /* RO */ 107 108 #define USB_DEVCTL_ABOVE_VBUS_VALID (0x18) 109 #define USB_DEVCTL_ABOVE_A_VALID (0x10) 110 #define USB_DEVCTL_ABOVE_SESSION_END (0x01) 111 #define USB_DEVCTL_BELOW_SESSION_END (0x00) 112 113 /* USB_VEND0 */ 114 #define USB_VEND0_DRQ_SEL (1) 115 #define USB_VEND0_BUS_SEL (0) 116 117 /* USB_CSR0 */ 118 #define USB_CSR0_RXPKTRDY (0x0001) /* RO */ 119 #define USB_CSR0_TXPKTRDY (0x0002) /* RW, AC */ 120 #define USB_CSR0_SENTSTALL (0x0004) /* RC */ 121 #define USB_CSR0_DATAEND (0x0008) /* WO, AC */ 122 #define USB_CSR0_SETUPEND (0x0010) /* RO */ 123 #define USB_CSR0_SENDSTALL (0x0020) /* WO, AC */ 124 #define USB_CSR0_SERVICEDRXPKTRDY (0x0040) /* WO, AC */ 125 #define USB_CSR0_SERVICEDSETUPEND (0x0080) /* WO, AC */ 126 #define USB_CSR0_FLUSHFIFO (0x0100) /* WO, AC */ 127 /* in Host mode */ 128 #define USB_CSR0_RXSTALL (0x0004) 129 #define USB_CSR0_SETUPPKT (0x0008) 130 #define USB_CSR0_ERROR (0x0010) 131 #define USB_CSR0_REQPKT (0x0020) 132 #define USB_CSR0_STATUSPKT (0x0040) 133 #define USB_CSR0_NAKTIMEOUT (0x0080) 134 #define USB_CSR0_FLUSHFIFO (0x0100) 135 #define USB_CSR0_DISPING (0x0800) 136 137 /* USB_TXMAXP */ 138 #define USB_TXMAXP_MAXPAYLOAD_MASK (0x07FF) 139 #define USB_TXMAXP_HIGHSPEED_MASK (0xF800) 140 141 /* USB_TXCSR */ 142 #define USB_TXCSR_TXPKTRDY (0x0001) /* RW */ 143 #define USB_TXCSR_FIFONOTEMPTY (0x0002) /* RO */ 144 #define USB_TXCSR_UNDERRUN (0x0004) /* RW */ 145 #define USB_TXCSR_FLUSHFIFO (0x0008) /* WO */ 146 #define USB_TXCSR_SENDSTALL (0x0010) /* RW */ 147 #define USB_TXCSR_SENTSTALL (0x0020) /* RC */ 148 #define USB_TXCSR_CLRDATATOG (0x0040) /* WO */ 149 #define USB_TXCSR_INCOMPTX (0x0080) /* RC */ 150 #define USB_TXCSR_SETTXPKTRDY_TWICE (0x0100) /* RC */ 151 #define USB_TXCSR_DMAREQMODE (0x0400) /* RW */ 152 #define USB_TXCSR_FRCDATATOG (0x0800) /* RW */ 153 #define USB_TXCSR_DMAREQENAB (0x1000) /* RW */ 154 #define USB_TXCSR_MODE (0x2000) /* RW */ 155 #define USB_TXCSR_ISO (0x4000) /* RW */ 156 #define USB_TXCSR_AUTOSET (0x8000) /* RW */ 157 /* in Host mode */ 158 #define USB_TXCSR_ERROR (0x0004) 159 #define USB_TXCSR_RXSTALL (0x0020) 160 #define USB_TXCSR_NAKTIMEOUT (0x0080) 161 162 /* USB_RXMAXP */ 163 #define USB_RXMAXP_MAXPAYLOAD_MASK (0x07FF) 164 #define USB_RXMAXP_HIGHSPEED_MASK (0xF800) 165 166 /* USB_RXCSR */ 167 #define USB_RXCSR_RXPKTRDY (0x0001) /* RC */ 168 #define USB_RXCSR_FIFOFULL (0x0002) /* RO, AC */ 169 #define USB_RXCSR_OVERRUN (0x0004) /* RC */ 170 #define USB_RXCSR_DATAERROR (0x0008) /* RO */ 171 #define USB_RXCSR_FLUSHFIFO (0x0010) /* WO, AC */ 172 #define USB_RXCSR_SENDSTALL (0x0020) /* RW */ 173 #define USB_RXCSR_SENTSTALL (0x0040) /* RC */ 174 #define USB_RXCSR_CLRDATATOG (0x0080) /* WO */ 175 #define USB_RXCSR_INCOMPRX (0x0100) /* RC */ 176 #define USB_RXCSR_KEEPERRCTATUS (0x0200) /* RC */ 177 #define USB_RXCSR_DMAREQMODE (0x0800) /* RW */ 178 #define USB_RXCSR_DISNYET (0x1000) /* RW */ 179 #define USB_RXCSR_PIDERROR (0x1000) /* RO */ 180 #define USB_RXCSR_DMAREQENAB (0x2000) /* RW */ 181 #define USB_RXCSR_ISO (0x4000) /* RW */ 182 #define USB_RXCSR_AUTOCLEAR (0x8000) /* RW */ 183 /* in Host mode */ 184 #define USB_RXCSR_ERROR (0x0004) 185 #define USB_RXCSR_NAKTIMEOUT (0x0008) 186 #define USB_RXCSR_REQPKT (0x0020) 187 #define USB_RXCSR_RXSTALL (0x0040) 188 #define USB_RXCSR_SETPEQPKT_TWICE (0x0400) 189 #define USB_RXCSR_AUTOREQ (0x4000) 190 191 /* USB_TXTYPE */ 192 #define USB_TXTYPE_EPNUM_MASK (0x0f) 193 #define USB_TXTYPE_ISO (0x10) 194 #define USB_TXTYPE_BULK (0x20) 195 #define USB_TXTYPE_INTR (0x30) 196 #define USB_TXTYPE_PROTOCOL_MASK (0x30) 197 198 /* USB_RXTYPE */ 199 #define USB_RXTYPE_EPNUM_MASK (0x0f) 200 #define USB_RXTYPE_ISO (0x10) 201 #define USB_RXTYPE_BULK (0x20) 202 #define USB_RXTYPE_INTR (0x30) 203 #define USB_RXTYPE_PROTOCOL_MASK (0x30) 204 205 /* USB_PWRUPCNT */ 206 #define USB_PWRUPCNT_MASK (0x0f) 207 208 /* USB_FIFOSZ */ 209 #define USB_FIFOSZ_SIZE_MASK (0x0F) 210 #define USB_FIFOSZ_DPB (0x10) 211 #define USB_FIFOSZ_SIZE_8 (0x00) 212 #define USB_FIFOSZ_SIZE_16 (0x01) 213 #define USB_FIFOSZ_SIZE_32 (0x02) 214 #define USB_FIFOSZ_SIZE_64 (0x03) 215 #define USB_FIFOSZ_SIZE_128 (0x04) 216 #define USB_FIFOSZ_SIZE_256 (0x05) 217 #define USB_FIFOSZ_SIZE_512 (0x06) 218 #define USB_FIFOSZ_SIZE_1024 (0x07) 219 #define USB_FIFOSZ_SIZE_2048 (0x08) 220 #define USB_FIFOSZ_SIZE_4096 (0x09) 221 222 /* USB_FIFOADD */ 223 #define USB_FIFOADD_MASK (0x1FFF) 224 225 /* USB_RXFIFOADD */ 226 #define USB_RXFIFOADD_DATAERRINTREN (0x8000) 227 #define USB_RXFIFOADD_OVERRUNINTREN (0x4000) 228 229 /* USB_FIFO2ADD */ 230 #define USB_FIFO2ADD_MASK (0x1FFF) 231 #define USB_FIFO2ADD_EN (0x8000) 232 233 /* -------------------- USB PHY Registers -------------------- */ 234 #define USB_PHY_BASE_OFFSET (0x400) 235 236 /* USB_ISCR */ 237 #define USB_ISCR_VBUS_VALID_FROM_DATA (0x40000000) 238 #define USB_ISCR_VBUS_VALID_FROM_VBUS (0x20000000) 239 #define USB_ISCR_EXT_ID_STATUS (0x10000000) 240 #define USB_ISCR_EXT_DM_STATUS (0x08000000) 241 #define USB_ISCR_EXT_DP_STATUS (0x04000000) 242 #define USB_ISCR_MERGED_VBUS_STATUS (0x02000000) 243 #define USB_ISCR_MERGED_ID_STATUS (0x01000000) 244 #define USB_ISCR_ID_PULLUP_EN (0x00020000) 245 #define USB_ISCR_DPDM_PULLUP_EN (0x00010000) 246 #define USB_ISCR_FORCE_ID_LOW (0x8000) 247 #define USB_ISCR_FORCE_ID_HIGH (0xc000) 248 #define USB_ISCR_FORCE_ID_DISABLED (0x0) 249 #define USB_ISCR_FORCE_ID_MASK (0xc000) 250 #define USB_ISCR_FORCE_VBUS_LOW (0x2000) 251 #define USB_ISCR_FORCE_VBUS_HIGH (0x3000) 252 #define USB_ISCR_FORCE_VBUS_DISABLED (0x0) 253 #define USB_ISCR_FORCE_VBUS_MASK (0x3000) 254 #define USB_ISCR_VBUS_VALID_SRC_DPDM (0X0800) 255 #define USB_ISCR_VBUS_VALID_SRC_ALL (0X0c00) 256 #define USB_ISCR_VBUS_VALID_SRC_MASK (0X0c00) 257 #define USB_ISCR_HOSC_EN (0X0080) 258 #define USB_ISCR_VBUS_CHANGE_DETECT (0X0040) 259 #define USB_ISCR_ID_CHANGE_DETECT (0X0020) 260 #define USB_ISCR_DPDM_CHANGE_DETECT (0X0010) 261 #define USB_ISCR_IRQ_ENABLE (0X0008) 262 #define USB_ISCR_VBUS_CHANGE_DETECT_EN (0X0004) 263 #define USB_ISCR_ID_CHANGE_DETECT_EN (0X0002) 264 #define USB_ISCR_DPDM_CHANGE_DETECT_EN (0X0001) 265 266 /* USB_PHY_CTL 28nm */ 267 #define USB_PHYCTL28NM_SIDDQ (0X0008) 268 #define USB_PHYCTL28NM_VBUSVLDEXT (0X0020) 269 270 /* USB_PHY_SEL */ 271 #define USB_PHYSEL_OTG_SEL (0x0001) 272 273 /* Register operations */ 274 #define DRV_WriteReg(addr, data) hal_writew(data, addr) 275 #define DRV_Reg(addr) hal_readw(addr) 276 #define DRV_WriteReg32(addr, data) hal_writel(data, addr) 277 #define DRV_Reg32(addr) hal_readl(addr) 278 #define DRV_WriteReg8(addr, data) hal_writeb(data, addr) 279 #define DRV_Reg8(addr) hal_readb(addr) 280 #define USB_DRV_WriteReg(addr, data) hal_writew(data, addr) 281 #define USB_DRV_Reg(addr) hal_readw(addr) 282 #define USB_DRV_WriteReg32(addr, data) hal_writel(data, addr) 283 #define USB_DRV_Reg32(addr) hal_readl(addr) 284 #define USB_DRV_WriteReg8(addr, data) hal_writeb(data, addr) 285 #define USB_DRV_Reg8(addr) hal_readb(addr) 286 287 #define USB_DRV_ClearBits(addr,data) { \ 288 uint16_t temp; \ 289 temp = DRV_Reg(addr); \ 290 temp &=~(data); \ 291 DRV_WriteReg(addr,temp); \ 292 } 293 294 #define USB_DRV_SetBits(addr,data) { \ 295 uint16_t temp; \ 296 temp = DRV_Reg(addr); \ 297 temp |= (data); \ 298 DRV_WriteReg(addr,temp); \ 299 } 300 301 #define USB_DRV_SetData(addr, bitmask, value) { \ 302 uint16_t temp; \ 303 temp = (~(bitmask)) & DRV_Reg(addr); \ 304 temp |= ((value) & (bitmask)); \ 305 DRV_WriteReg(addr,temp); \ 306 } 307 308 #define USB_DRV_ClearBits32(addr,data) { \ 309 uint32_t temp; \ 310 temp = DRV_Reg32(addr); \ 311 temp &=~(data); \ 312 DRV_WriteReg32(addr,temp); \ 313 } 314 315 #define USB_DRV_SetBits32(addr,data) { \ 316 uint32_t temp; \ 317 temp = DRV_Reg32(addr); \ 318 temp |= (data); \ 319 DRV_WriteReg32(addr,temp); \ 320 } 321 322 #define USB_DRV_SetData32(addr, bitmask, value) { \ 323 uint32_t temp; \ 324 temp = (~(bitmask)) & DRV_Reg32(addr); \ 325 temp |= ((value) & (bitmask)); \ 326 DRV_WriteReg32(addr,temp); \ 327 } 328 329 #define USB_DRV_ClearBits8(addr,data) { \ 330 uint8_t temp; \ 331 temp = DRV_Reg8(addr); \ 332 temp &=~(data); \ 333 DRV_WriteReg8(addr,temp); \ 334 } 335 336 #define USB_DRV_SetBits8(addr,data) { \ 337 uint8_t temp; \ 338 temp = DRV_Reg8(addr); \ 339 temp |= (data); \ 340 DRV_WriteReg8(addr,temp); \ 341 } 342 343 #define USB_DRV_SetData8(addr, bitmask, value) { \ 344 uint8_t temp; \ 345 temp = (~(bitmask)) & DRV_Reg8(addr); \ 346 temp |= ((value) & (bitmask)); \ 347 DRV_WriteReg8(addr,temp); \ 348 } 349 350 typedef struct { 351 /* common registers */ 352 /* fifo */ 353 uint32_t fifo0; /* USBEndpoint0FIFORegister */ 354 uint32_t fifo1; /* USBEndpoint1FIFORegister */ 355 uint8_t revered1[56]; /* 0x0000 + N*4 */ 356 uint8_t power; /* 0x0040 */ 357 uint8_t devctl; /* 0x0041 */ 358 uint8_t index; /* 0x0042 */ 359 uint8_t vend0; /* 0x0043 */ 360 uint16_t intrtx; /* 0x0044 */ 361 uint16_t intrrx; /* 0x0046 */ 362 uint16_t intrtxe; /* 0x0048 */ 363 uint16_t intrrxe; /* 0x004a */ 364 uint32_t intrusb; /* 0x004c */ 365 uint32_t intrusbe; /* 0x0050 */ 366 uint32_t frame; /* 0x0054 */ 367 uint32_t reserved1[9]; 368 uint32_t testmode; /* 0x007c */ 369 /* indexed registers */ 370 uint16_t txmap; /* 0x0080 */ 371 uint16_t txcsr; /* 0x0082 */ 372 uint16_t rxmap; /* 0x0084 */ 373 uint16_t rxcsr; /* 0x0086 */ 374 uint32_t rxcount; /* 0x0088 */ 375 uint8_t txtype; /* 0x008c */ 376 uint8_t txinterval; /* 0x008d */ 377 uint8_t rxtype; /* 0x008e */ 378 uint8_t rxinterval; /* 0x008f */ 379 /* OTG, dynamic FIFO, version & vendor registers */ 380 uint16_t txfifosz; /* 0x0090 */ 381 uint16_t txfifoadd; /* 0x0092 */ 382 uint16_t rxfifosz; /* 0x0094 */ 383 uint16_t rxfifoadd; /* 0x0096 */ 384 uint8_t faddr; /* 0x0098 */ 385 } UDC_REGISTER_T; 386 387 typedef struct { 388 uint32_t iscr; /* 0x0400 */ 389 uint32_t phyctrl40nm; /* 0x0404 */ 390 uint32_t phybist; /* 0x0408 */ 391 uint32_t reserved1; 392 uint32_t phyctrl28nm; /* 0x0410 */ 393 uint32_t phytest; /* 0x0414 */ 394 uint32_t phytune; /* 0x0418 */ 395 uint32_t reserved2; 396 uint32_t physel; /* 0x0420 */ 397 uint32_t physta; /* 0x0424 */ 398 } USBPHY_REGISTER_T; 399 400 #endif /*__UDC_PLATFORM_H__*/ 401