1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2018-02-08 RT-Thread the first version 9 */ 10 #ifndef __DRV_CLOCK_H__ 11 #define __DRV_CLOCK_H__ 12 13 /* PLL state */ 14 #define PLL_ENBALE (0x1) 15 #define PLL_STABLE (0x2) 16 17 /* Clock source selection */ 18 #define CLK_LOSC_SRC (0x00) 19 #define CLK_OSC24M_SRC (0x01) 20 #define CLK_PLL_SRC (0x02) 21 #define PRE_DIV_SRC (0x03) 22 23 24 /* */ 25 #define TCON_PLL_VIDEO_X1 (0x000) 26 #define TCON_PLL_VIDEO_X2 (0x002) 27 28 29 #define PLL_CPU_ENABLE_STATE (0x1<<31) 30 #define PLL_CPU_HAS_BEEN_STABLE (0x1<<28) 31 #define PLL_CPU_DIV_P(reg) ((reg>>16)&0x3) 32 #define PLL_CPU_FACTOR_N(reg) ((reg>>8)&0x1f) 33 #define PLL_CPU_FACTOR_K(reg) ((reg>>4)&0x3) 34 #define PLL_CPU_FACTOR_M(reg) ((reg)&0x3) 35 36 #define PLL_AUDIO_ENABLE_STATE (0x1<<31) 37 #define PLL_AUDIO_HAS_BEEN_STABLE (0x1<<28) 38 #define PLL_AUDIO_FACTOR_N(reg) ((reg>>8)&0x7f) 39 #define PLL_AUDIO_PREDIV_M(reg) ((reg)&0x1f) 40 41 #define PLL_VIDEO_ENABLE_STATE (0x1<<31) 42 #define PLL_VIDEO_MODE (0x1<<30) 43 #define PLL_VIDEO_HAS_BEEN_STABLE (0x1<<28) 44 #define PLL_VIDEO_FRAC_CLK_OUT (0x1<<25) 45 #define PLL_VIDEO_MODE_SEL (0x1<<24) 46 #define PLL_VIDEO_SDM_EN (0x1<<20) 47 #define PLL_VIDEO_FACTOR_N(reg) ((reg>>8)&0x7f) 48 #define PLL_VIDEO_PREDIV_M(reg) (reg&0xf) 49 50 #define PLL_VE_ENABLE_STATE (0x1<<31) 51 #define PLL_VE_HAS_BEEN_STABLE (0x1<<28) 52 #define PLL_VE_FRAC_CLK_OUT (0x1<<25) 53 #define PLL_VE_MODE_SEL (0x1<<24) 54 #define PLL_VE_FACTOR_N(reg) ((reg>>8)&0x7f) 55 #define PLL_VE_PREDIV_M(reg) (reg&0xf) 56 57 #define PLL_DDR_ENABLE_STATE (0x1<<31) 58 #define PLL_DDR_HAS_BEEN_STABLE (0x1<<28) 59 #define SDRAM_SIGMA_DELTA_EN (0x1<<24) 60 #define PLL_DDR_CFG_UPDATE (0x1<<20) 61 #define PLL_DDR_FACTOR_N(reg) ((reg>>8)&0x1f) 62 #define PLL_DDR_FACTOR_K(reg) ((reg>>4)&0x3) 63 #define PLL_DDR_FACTOR_M(reg) ((reg)&0x3) 64 65 #define PLL_PERIPH_ENABLE_STATE (0x1<<31) 66 #define PLL_PERIPH_HAS_BEEN_STABLE (0x1<<28) 67 #define PLL_PERIPH_24M_OUT_EN (0x1<<18) 68 #define PLL_PERIPH_24M_POST_DIV(reg) ((reg>>16)&0x3) 69 #define PLL_PERIPH_FACTOR_N(reg) ((reg>>8)&0x1f) 70 #define PLL_PERIPH_FACTOR_K(reg) ((reg>>4)&0x3) 71 #define PLL_PERIPH_FACTOR_M(reg) (reg&0x3) 72 73 #define HCLKC_DIV(reg) ((reg>>16)&0x3) 74 #define AHB_SRC_SEL(reg) ((reg>>12)&0x3) 75 #define AHB_CLK_DIV(reg) ((reg>>4)&0x3) 76 #define AHB_PRE_DIV(reg) ((reg>>6)&0x3) 77 #define APH_CLK_PATIO(reg) ((reg>>8)&0x3) 78 79 80 #define CCM_MMC_CTRL_OSCM24 (0x00) 81 #define CCM_MMC_CTRL_PLL_PERIPH (0x01) 82 83 #define CCU_BASE_ADDR (0x01C20000) 84 85 #define _24MHZ_ (24000000U) 86 #define _32KHZ_ (32000U) 87 88 /* GATE */ 89 90 #define BUS_GATE_OFFSET_BIT (12) 91 92 enum bus_gate 93 { 94 USB_OTG_GATING = (0x18 | (0x0 << BUS_GATE_OFFSET_BIT)), 95 SPI1_GATING = (0x15 | (0x0 << BUS_GATE_OFFSET_BIT)), 96 SPI0_GATING = (0x14 | (0x0 << BUS_GATE_OFFSET_BIT)), 97 SDRAM_GATING = (0x0E | (0x0 << BUS_GATE_OFFSET_BIT)), 98 SD1_GATING = (0x09 | (0x0 << BUS_GATE_OFFSET_BIT)), 99 SD0_GATING = (0x08 | (0x0 << BUS_GATE_OFFSET_BIT)), 100 DMA_GATING = (0x06 | (0x0 << BUS_GATE_OFFSET_BIT)), 101 102 DEFE_GATING = (0x0E | (0x1 << BUS_GATE_OFFSET_BIT)), 103 DEBE_GATING = (0x0C | (0x1 << BUS_GATE_OFFSET_BIT)), 104 TVE_GATING = (0x0A | (0x1 << BUS_GATE_OFFSET_BIT)), 105 TVD_GATING = (0x09 | (0x1 << BUS_GATE_OFFSET_BIT)), 106 CSI_GATING = (0x08 | (0x1 << BUS_GATE_OFFSET_BIT)), 107 DEINTERLACE_GATING = (0x05 | (0x1 << BUS_GATE_OFFSET_BIT)), 108 LCD_GATING = (0x04 | (0x1 << BUS_GATE_OFFSET_BIT)), 109 VE_GATING = (0x00 | (0x1 << BUS_GATE_OFFSET_BIT)), 110 111 UART2_GATING = (0x16 | (0x2 << BUS_GATE_OFFSET_BIT)), 112 UART1_GATING = (0x15 | (0x2 << BUS_GATE_OFFSET_BIT)), 113 UART0_GATING = (0x14 | (0x2 << BUS_GATE_OFFSET_BIT)), 114 TWI2_GATING = (0x12 | (0x2 << BUS_GATE_OFFSET_BIT)), 115 TWI1_GATING = (0x11 | (0x2 << BUS_GATE_OFFSET_BIT)), 116 TWI0_GATING = (0x10 | (0x2 << BUS_GATE_OFFSET_BIT)), 117 DAUDIO_GATING = (0x0C | (0x2 << BUS_GATE_OFFSET_BIT)), 118 RSB_GATING = (0x03 | (0x2 << BUS_GATE_OFFSET_BIT)), 119 CIR_GATING = (0x02 | (0x2 << BUS_GATE_OFFSET_BIT)), 120 OWA_GATING = (0x01 | (0x2 << BUS_GATE_OFFSET_BIT)), 121 AUDIO_CODEC_GATING = (0x00 | (0x2 << BUS_GATE_OFFSET_BIT)), 122 }; 123 124 enum dram_gate 125 { 126 BE_GATING_DRAM = 26, 127 FE_GATING_DRAM = 24, 128 TVD_GATING_DRAM = 3, 129 DEINTERLACE_GATING_DRAM = 2, 130 CSI_GATING_DRAM = 1, 131 VE_GATING_DRAM = 0 132 }; 133 enum mmc_clk_id 134 { 135 SDMMC0, 136 SDMMC1, 137 }; 138 139 struct tina_ccu 140 { 141 volatile rt_uint32_t pll_cpu_ctrl; /* 0x000 */ 142 volatile rt_uint32_t reserved0; 143 volatile rt_uint32_t pll_audio_ctrl; /* 0x008 */ 144 volatile rt_uint32_t reserved1; 145 volatile rt_uint32_t pll_video_ctrl; /* 0x010 */ 146 volatile rt_uint32_t reserved2; 147 volatile rt_uint32_t pll_ve_ctrl; /* 0x018 */ 148 volatile rt_uint32_t reserved3; 149 volatile rt_uint32_t pll_ddr_ctrl; /* 0x020 */ 150 volatile rt_uint32_t reserved4; 151 volatile rt_uint32_t pll_periph_ctrl; /* 0x028 */ 152 volatile rt_uint32_t reserved5[9]; 153 volatile rt_uint32_t cpu_clk_src; /* 0x050 */ 154 volatile rt_uint32_t ahb_apb_hclkc_cfg; /* 0x054 */ 155 volatile rt_uint32_t reserved6[2]; 156 volatile rt_uint32_t bus_clk_gating0; /* 0x060 */ 157 volatile rt_uint32_t bus_clk_gating1; /* 0x064 */ 158 volatile rt_uint32_t bus_clk_gating2; /* 0x068 */ 159 volatile rt_uint32_t reserved7[7]; 160 volatile rt_uint32_t sdmmc0_clk; /* 0x088 */ 161 volatile rt_uint32_t sdmmc1_clk; /* 0x08C */ 162 volatile rt_uint32_t reserved8[8]; 163 volatile rt_uint32_t daudio_clk; /* 0x0B0 */ 164 volatile rt_uint32_t owa_clk; /* 0x0B4 */ 165 volatile rt_uint32_t cir_clk; /* 0x0B8 */ 166 volatile rt_uint32_t reserved9[4]; 167 volatile rt_uint32_t usbphy_clk; /* 0x0CC */ 168 volatile rt_uint32_t reserved10[12]; 169 volatile rt_uint32_t dram_gating; /* 0x100 */ 170 volatile rt_uint32_t be_clk; /* 0x104 */ 171 volatile rt_uint32_t reserved11; 172 volatile rt_uint32_t fe_clk; /* 0x10C */ 173 volatile rt_uint32_t reserved12[2]; 174 volatile rt_uint32_t tcon_clk; /* 0x118*/ 175 volatile rt_uint32_t di_clk; /* 0x11C */ 176 volatile rt_uint32_t tve_clk; /* 0x120 */ 177 volatile rt_uint32_t tvd_clk; /* 0x124 */ 178 volatile rt_uint32_t reserved13[3]; 179 volatile rt_uint32_t csi_clk; /* 0x134 */ 180 volatile rt_uint32_t reserved14; 181 volatile rt_uint32_t ve_clk; /* 0x13C */ 182 volatile rt_uint32_t audio_codec_clk; /* 0x140 */ 183 volatile rt_uint32_t avs_clk; /* 0x144 */ 184 volatile rt_uint32_t reserved15[46]; 185 volatile rt_uint32_t pll_stable_time0; /* 0x200 */ 186 volatile rt_uint32_t pll_stable_time1; /* 0x204 */ 187 volatile rt_uint32_t reserved16[6]; 188 volatile rt_uint32_t pll_cpu_bias; /* 0x220 */ 189 volatile rt_uint32_t pll_audio_bias; /* 0x224 */ 190 volatile rt_uint32_t pll_video_bias; /* 0x228 */ 191 volatile rt_uint32_t pll_ve_bias; /* 0x22C */ 192 volatile rt_uint32_t pll_ddr_bias; /* 0x230 */ 193 volatile rt_uint32_t pll_periph_bias; /* 0x234 */ 194 volatile rt_uint32_t reserved17[6]; 195 volatile rt_uint32_t pll_cpu_tun; /* 0x250 */ 196 volatile rt_uint32_t reserved18[3]; 197 volatile rt_uint32_t pll_ddr_tun; /* 0x260 */ 198 volatile rt_uint32_t reserved19[8]; 199 volatile rt_uint32_t pll_audio_pat_ctrl; /* 0x284 */ 200 volatile rt_uint32_t pll_video_pat_ctrl; /* 0x288 */ 201 volatile rt_uint32_t reserved20; 202 volatile rt_uint32_t pll_ddr_pat_ctrl; /* 0x290 */ 203 volatile rt_uint32_t reserved21[11]; 204 volatile rt_uint32_t bus_soft_rst0; /* 0x2C0 */ 205 volatile rt_uint32_t bus_soft_rst1; /* 0x2C4 */ 206 volatile rt_uint32_t reserved22[2]; 207 volatile rt_uint32_t bus_soft_rst2; /* 0x2D0 */ 208 }; 209 210 typedef struct tina_ccu *tina_ccu_t; 211 212 #define CCU ((tina_ccu_t) CCU_BASE_ADDR) 213 214 int cpu_get_pll_clk(void); 215 int audio_get_pll_clk(void); 216 int video_get_pll_clk(void); 217 int ve_get_pll_clk(void); 218 int ddr_get_pll_clk(void); 219 int periph_get_pll_clk(void); 220 int cpu_get_clk(void); 221 int ahb_get_clk(void); 222 int apb_get_clk(void); 223 224 rt_err_t cpu_set_pll_clk(int clk); 225 rt_err_t audio_set_pll_clk(int clk); 226 rt_err_t video_set_pll_clk(int clk); 227 rt_err_t ve_set_pll_clk(int clk); 228 rt_err_t periph_set_pll_clk(int clk); 229 230 rt_err_t cpu_set_clk(int clk); 231 232 rt_err_t bus_gate_clk_enalbe(enum bus_gate bus); 233 rt_err_t bus_gate_clk_disalbe(enum bus_gate bus); 234 rt_err_t bus_software_reset_enalbe(enum bus_gate bus); 235 rt_err_t bus_software_reset_disalbe(enum bus_gate bus); 236 237 rt_err_t dram_gate_clk_enable(enum dram_gate dram_gate); 238 rt_err_t dram_gate_clk_disable(enum dram_gate dram_gate); 239 240 rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz); 241 #endif 242