1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2018-02-08 RT-Thread the first version 9 */ 10 #ifndef __DRV_SDIO_H__ 11 #define __DRV_SDIO_H__ 12 13 14 #define MMC0_BASE_ADDR 0x01C0F000 15 #define MMC1_BASE_ADDR 0x01C10000 16 17 struct tina_mmc 18 { 19 volatile rt_uint32_t gctl_reg; /* (0x000) */ 20 volatile rt_uint32_t ckcr_reg; /* (0x004) */ 21 volatile rt_uint32_t tmor_reg; /* (0x008) */ 22 volatile rt_uint32_t bwdr_reg; /* (0x00C) */ 23 volatile rt_uint32_t bksr_reg; /* (0x010) */ 24 volatile rt_uint32_t bycr_reg; /* (0x014) */ 25 volatile rt_uint32_t cmdr_reg; /* (0x018) */ 26 volatile rt_uint32_t cagr_reg; /* (0x01C) */ 27 volatile rt_uint32_t resp0_reg; /* (0x020) */ 28 volatile rt_uint32_t resp1_reg; /* (0x024) */ 29 volatile rt_uint32_t resp2_reg; /* (0x028) */ 30 volatile rt_uint32_t resp3_reg; /* (0x02C) */ 31 volatile rt_uint32_t imkr_reg; /* (0x030) */ 32 volatile rt_uint32_t misr_reg; /* (0x034) */ 33 volatile rt_uint32_t risr_reg; /* (0x038) */ 34 volatile rt_uint32_t star_reg; /* (0x03C) */ 35 volatile rt_uint32_t fwlr_reg; /* (0x040) */ 36 volatile rt_uint32_t funs_reg; /* (0x044) */ 37 volatile rt_uint32_t cbcr_reg; /* (0x048) */ 38 volatile rt_uint32_t bbcr_reg; /* (0x04C) */ 39 volatile rt_uint32_t dbgc_reg; /* (0x050) */ 40 volatile rt_uint32_t reserved0; 41 volatile rt_uint32_t a12a_reg; /* (0x058) */ 42 volatile rt_uint32_t reserved1[7]; 43 volatile rt_uint32_t hwrst_reg; /* (0x078) */ 44 volatile rt_uint32_t reserved2; 45 volatile rt_uint32_t dmac_reg; /* (0x080) */ 46 volatile rt_uint32_t dlba_reg; /* (0x084) */ 47 volatile rt_uint32_t idst_reg; /* (0x088) */ 48 volatile rt_uint32_t idie_reg; /* (0x08C) */ 49 volatile rt_uint32_t chda_reg; /* (0x090) */ 50 volatile rt_uint32_t cbda_reg; /* (0x094) */ 51 volatile rt_uint32_t reserved3[26]; 52 volatile rt_uint32_t card_thldc_reg; /* (0x100) */ 53 volatile rt_uint32_t reserved4[2]; 54 volatile rt_uint32_t emmc_dsbd_reg; /* (0x10c) */ 55 volatile rt_uint32_t reserved5[12]; 56 volatile rt_uint32_t reserved6[48]; 57 volatile rt_uint32_t fifo_reg; /* (0x200) */ 58 }; 59 60 typedef struct tina_mmc *tina_mmc_t; 61 62 #define MMC0 ((tina_mmc_t)MMC0_BASE_ADDR) 63 #define MMC1 ((tina_mmc_t)MMC1_BASE_ADDR) 64 65 66 #define BIT(x) (1UL<<(x)) 67 /* Struct for Intrrrupt Information */ 68 #define SDXC_RespErr BIT(1) //0x2 69 #define SDXC_CmdDone BIT(2) //0x4 70 #define SDXC_DataOver BIT(3) //0x8 71 #define SDXC_TxDataReq BIT(4) //0x10 72 #define SDXC_RxDataReq BIT(5) //0x20 73 #define SDXC_RespCRCErr BIT(6) //0x40 74 #define SDXC_DataCRCErr BIT(7) //0x80 75 #define SDXC_RespTimeout BIT(8) //0x100 76 #define SDXC_ACKRcv BIT(8) //0x100 77 #define SDXC_DataTimeout BIT(9) //0x200 78 #define SDXC_BootStart BIT(9) //0x200 79 #define SDXC_DataStarve BIT(10) //0x400 80 #define SDXC_VolChgDone BIT(10) //0x400 81 #define SDXC_FIFORunErr BIT(11) //0x800 82 #define SDXC_HardWLocked BIT(12) //0x1000 83 #define SDXC_StartBitErr BIT(13) //0x2000 84 #define SDXC_AutoCMDDone BIT(14) //0x4000 85 #define SDXC_EndBitErr BIT(15) //0x8000 86 #define SDXC_SDIOInt BIT(16) //0x10000 87 #define SDXC_CardInsert BIT(30) //0x40000000 88 #define SDXC_CardRemove BIT(31) //0x80000000 89 #define SDXC_IntErrBit (SDXC_RespErr | SDXC_RespCRCErr | SDXC_DataCRCErr \ 90 | SDXC_RespTimeout | SDXC_DataTimeout | SDXC_FIFORunErr \ 91 | SDXC_HardWLocked | SDXC_StartBitErr | SDXC_EndBitErr) //0xbfc2 92 93 /* 94 SD CMD reg 95 REG[0-5] : Cmd ID 96 REG[6] : Has response 97 REG[7] : Long response 98 REG[8] : Check response CRC 99 REG[9] : Has data 100 REG[10] : Write 101 REG[11] : Steam mode 102 REG[12] : Auto stop 103 REG[13] : Wait previous over 104 REG[14] : About cmd 105 REG[15] : Send initialization 106 REG[21] : Update clock 107 REG[31] : Load cmd 108 */ 109 #define SDXC_RESPONSE_CMD BIT(6) 110 #define SDXC_LONG_RESPONSE_CMD BIT(7) 111 #define SDXC_CHECK_CRC_CMD BIT(8) 112 #define SDXC_HAS_DATA_CMD BIT(9) 113 #define SDXC_WRITE_CMD BIT(10) 114 #define SDXC_STEAM_CMD BIT(11) 115 #define SDXC_AUTO_STOP_CMD BIT(12) 116 #define SDXC_WAIT_OVER_CMD BIT(13) 117 #define SDXC_ABOUT_CMD BIT(14) 118 #define SDXC_SEND_INIT_CMD BIT(15) 119 #define SDXC_UPDATE_CLOCK_CMD BIT(21) 120 #define SDXC_LOAD_CMD BIT(31) 121 122 /* 123 SD status reg 124 REG[0] : FIFO_RX_LEVEL 125 REG[1] : FIFO_TX_LEVEL 126 REG[2] : FIFO_EMPTY 127 REG[3] : FIFO_FULL 128 REG[4-7] : FSM_STA 129 REG[8] : CARD_PRESENT 130 REG[9] : CARD_BUSY 131 REG[10] : FSM_BUSY 132 REG[11-16]: RESP_IDX 133 REG[17-21]: FIFO_LEVEL 134 REG[31] : DMA_REQ 135 */ 136 137 #define SDXC_FIFO_RX_LEVEL BIT(0) 138 #define SDXC_FIFO_TX_LEVEL BIT(1) 139 #define SDXC_FIFO_EMPTY BIT(2) 140 #define SDXC_FIFO_FULL BIT(3) 141 #define SDXC_CARD_PRESENT BIT(8) 142 #define SDXC_CARD_BUSY BIT(9) 143 #define SDXC_FSM_BUSY BIT(10) 144 #define SDXC_DMA_REQ BIT(31) 145 146 struct mmc_des_v4p1 147 { 148 rt_uint32_t : 1, 149 dic : 1, /* disable interrupt on completion */ 150 last_des : 1, /* 1-this data buffer is the last buffer */ 151 first_des : 1, /* 1-data buffer is the first buffer,0-data buffer contained in the next descriptor is 1st buffer */ 152 des_chain : 1, /* 1-the 2nd address in the descriptor is the next descriptor address */ 153 end_of_ring : 1, /* 1-last descriptor flag when using dual data buffer in descriptor */ 154 : 24, 155 card_err_sum : 1, /* transfer error flag */ 156 own : 1; /* des owner:1-idma owns it, 0-host owns it */ 157 158 #define SDXC_DES_NUM_SHIFT 12 /* smhc2!! */ 159 #define SDXC_DES_BUFFER_MAX_LEN (1 << SDXC_DES_NUM_SHIFT) 160 rt_uint32_t data_buf1_sz : 16, 161 data_buf2_sz : 16; 162 rt_uint32_t buf_addr_ptr1; 163 rt_uint32_t buf_addr_ptr2; 164 }; 165 166 #endif 167