1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2018-02-08 RT-Thread the first version 9 * 2020-03-2 Howard Su Define same regsiters as an array 10 */ 11 #ifndef __INTERRUPT_H__ 12 #define __INTERRUPT_H__ 13 14 /* Max number of interruptions */ 15 #define INTERRUPTS_MAX (64) 16 /* a group num */ 17 #define GROUP_NUM (32) 18 /* Interrupt Source */ 19 #define NMI_INTERRUPT (0) 20 #define UART0_INTERRUPT (1) 21 #define UART1_INTERRUPT (2) 22 #define UART2_INTERRUPT (3) 23 #define OWA_INTERRUPT (5) 24 #define CIR_INTERRUPT (6) 25 #define TWI0_INTERRUPT (7) 26 #define TWI1_INTERRUPT (8) 27 #define TWI2_INTERRUPT (9) 28 #define SPI0_INTERRUPT (10) 29 #define SPI1_INTERRUPT (11) 30 #define TIMER0_INTERRUPT (13) 31 #define TIMER1_INTERRUPT (14) 32 #define TIMER2_INTERRUPT (15) 33 #define WATCHDOG_INTERRUPT (16) 34 #define RSB_INTERRUPT (17) 35 #define DMA_INTERRUPT (18) 36 #define TOUCHPANEL_INTERRUPT (20) 37 #define AUDIOCODEC_INTERRUPT (21) 38 #define KEYADC_INTERRUPT (22) 39 #define SDC0_INTERRUPT (23) 40 #define SDC1_INTERRUPT (24) 41 #define USB_OTG_INTERRUPT (26) 42 #define TVD_INTERRUPT (27) 43 #define TVE_INTERRUPT (28) 44 #define TCON_INTERRUPT (29) 45 #define DE_FE_INTERRUPT (30) 46 #define DE_BE_INTERRUPT (31) 47 #define CSI_INTERRUPT (32) 48 #define DE_INTERLACER_INTERRUPT (33) 49 #define VE_INTERRUPT (34) 50 #define DAUDIO_INTERRUPT (35) 51 #define PIOD_INTERRUPT (38) 52 #define PIOE_INTERRUPT (39) 53 #define PIOF_INTERRUPT (40) 54 55 /* intc register address */ 56 #define INTC_BASE_ADDR (0x01C20400) 57 58 struct tina_intc 59 { 60 volatile rt_uint32_t vector_reg; /* 0x00 */ 61 volatile rt_uint32_t base_addr_reg; /* 0x04 */ 62 volatile rt_uint32_t reserved0; 63 volatile rt_uint32_t nmi_ctrl_reg; /* 0x0C */ 64 volatile rt_uint32_t pend_reg[2]; /* 0x10, 0x14 */ 65 volatile rt_uint32_t reserved1[2]; 66 volatile rt_uint32_t en_reg[2]; /* 0x20, 0x24 */ 67 volatile rt_uint32_t reserved2[2]; 68 volatile rt_uint32_t mask_reg[2]; /* 0x30, 0x34 */ 69 volatile rt_uint32_t reserved3[2]; 70 volatile rt_uint32_t resp_reg[2]; /* 0x40, 0x44 */ 71 volatile rt_uint32_t reserved4[2]; 72 volatile rt_uint32_t ff_reg[2]; /* 0x50, 0x54 */ 73 volatile rt_uint32_t reserved5[2]; 74 volatile rt_uint32_t prio_reg[4]; /* 0x60 - 0x6c */ 75 } ; 76 77 typedef struct tina_intc *tina_intc_t; 78 79 #define INTC ((tina_intc_t)INTC_BASE_ADDR) 80 81 #endif /* __INTERRUPT_H__ */ 82