1/*###ICF### Section handled by ICF editor, don't touch! ****/
2/*-Editor annotation file-*/
3/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
4/*-Specials-*/
5//define symbol __ICFEDIT_intvec_start__ = 0x00000000;
6/**/
7/**/
8include "rom_symbol_v01_iar.icf";
9/****************************************
10 * Memory Regions                   *
11 ****************************************/
12define symbol __ICFEDIT_region_ROM_start__          = 0x00000000;
13define symbol __ICFEDIT_region_ROM_end__            = 0x0007FFFF;
14define symbol __ICFEDIT_region_ROMBSS_RAM_start__       = 0x10000000;
15define symbol __ICFEDIT_region_ROMBSS_RAM_end__         = 0x10001FFF;
16define symbol __ICFEDIT_region_BOOTLOADER_RAM_start__   = 0x10002000;
17define symbol __ICFEDIT_region_BOOTLOADER_RAM_end__     = 0x10004FFF;
18define symbol __ICFEDIT_region_BD_RAM_start__       = 0x10005000;
19define symbol __ICFEDIT_region_BD_RAM_end__         = 0x1002FFFF;
20define symbol __ICFEDIT_region_MSP_RAM_start__      = 0x1003E000;
21define symbol __ICFEDIT_region_MSP_RAM_end__        = 0x1003EFFF;
22define symbol __ICFEDIT_region_RDP_RAM_start__      = 0x1003F000;
23define symbol __ICFEDIT_region_RDP_RAM_end__        = 0x1003FFEF;
24define symbol __ICFEDIT_region_IMG2_TEMP_start__    = 0x10006000;
25define symbol __ICFEDIT_region_IMG2_TEMP_end__      = 0x1000BFFF;
26define symbol __ICFEDIT_region_XIP_BOOT_start__     = 0x08000000+0x20;
27define symbol __ICFEDIT_region_XIP_BOOT_end__       = 0x08003FFF;
28define symbol __ICFEDIT_region_XIP_OTA1_start__     = 0x0800B000+0x20;
29define symbol __ICFEDIT_region_XIP_OTA1_end__       = 0x080FFFFF;
30/****************************************
31 * Sizes                   *
32 ****************************************/
33/*define symbol __ICFEDIT_size_cstack__   = 0x400;*/
34define symbol __ICFEDIT_size_heap__     = 0x000;
35/**** End of ICF editor section. ###ICF###*/
36define memory mem with size = 4G;
37define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
38define region ROM_BSS_region   = mem:[from __ICFEDIT_region_ROMBSS_RAM_start__   to __ICFEDIT_region_ROMBSS_RAM_end__];
39define region BOOT_RAM_region   = mem:[from __ICFEDIT_region_BOOTLOADER_RAM_start__   to __ICFEDIT_region_BOOTLOADER_RAM_end__];
40define region BD_RAM_region   = mem:[from __ICFEDIT_region_BD_RAM_start__   to __ICFEDIT_region_BD_RAM_end__];
41define region IMG2_TEMP_region   = mem:[from __ICFEDIT_region_IMG2_TEMP_start__   to __ICFEDIT_region_IMG2_TEMP_end__];
42define region XIP_BOOT_region   = mem:[from __ICFEDIT_region_XIP_BOOT_start__   to __ICFEDIT_region_XIP_BOOT_end__];
43define region XIP_OTA1_region   = mem:[from __ICFEDIT_region_XIP_OTA1_start__   to __ICFEDIT_region_XIP_OTA1_end__];
44define region RDP_RAM_region   = mem:[from __ICFEDIT_region_RDP_RAM_start__   to __ICFEDIT_region_RDP_RAM_end__];
45/*define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };*/
46define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
47//initialize by copy { readwrite };
48//initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application
49//do not initialize  { section * };
50//place at address mem:__ICFEDIT_intvec_start__ { readonly section .vectors_table };
51//
52/****************************************
53 * ROM Section config                   *
54 ****************************************/
55keep { section FSymTab };
56keep { section VSymTab };
57keep { section .rti_fn* };
58keep { section .rom.text };
59keep { section .rom.rodata };
60place at start of ROM_region   { readonly, section .rom.text, section .rom.rodata};
61/****************************************
62 * ROM BSS Section config                *
63 ****************************************/
64keep { section .ram_vector_table1 };
65keep { section .ram_vector_table2 };
66keep { section .ram_vector_table3 };
67keep { section .hal.rom.bss* };
68keep { section .wlan_ram_map* };
69keep { section .libc.ram.bss* };
70keep { section .ssl_ram_map* };
71define block .hal.rom.bss with fixed order{         section .ram_vector_table1,
72                                                section .ram_vector_table2,
73                                                section .ram_vector_table3,
74                                                section .hal.rom.bss*,
75                                                section .wlan_ram_map*,
76                                                section .libc.ram.bss*,
77                                                section .ssl_ram_map*,
78                                      };
79define block ROM_BSS with fixed order { block .hal.rom.bss};
80place at start of ROM_BSS_region  { readwrite,
81                                      block ROM_BSS,
82                                      };
83/****************************************
84 * BOOT RAM Section config                *
85 ****************************************/
86keep { section .image1.entry.data* };
87keep { section .image1.validate.rodata* };
88define block .ram_image1.entry with fixed order{section .image1.entry.data*,
89                        section .image1.validate.rodata*,
90                        };
91keep { section .boot.ram.text* };
92keep { section .boot.rodata* };
93define block .ram_image1.text with fixed order{section .boot.ram.text*,
94                        section .boot.rodata*,
95                        };
96keep { section .boot.ram.data* };
97define block .ram_image1.data with fixed order{section .boot.ram.data*,
98                        };
99keep { section .boot.ram.bss* };
100define block .ram_image1.bss with fixed order{section .boot.ram.bss*,
101                        };
102define block IMAGE1 with fixed order { block .ram_image1.entry, block .ram_image1.text, block .ram_image1.data, block .ram_image1.bss};
103place at start of BOOT_RAM_region   { readwrite,
104                                    block IMAGE1,
105                                  };
106/****************************************
107 * BD RAM Section config                *
108 ****************************************/
109keep { section .image2.entry.data* };
110keep { section .image2.validate.rodata* };
111define block .ram_image2.entry with fixed order{ section .image2.entry.data*,
112                        section .image2.validate.rodata*,
113                        };
114define block SHT$$PREINIT_ARRAY { preinit_array };
115define block SHT$$INIT_ARRAY { init_array };
116define block CPP_INIT with fixed order { block SHT$$PREINIT_ARRAY,
117                    block SHT$$INIT_ARRAY };
118define block .ram.data with fixed order{ section .data*,
119                     section DATA,
120                     section .iar.init_table,
121                     section __DLIB_PERTHREAD,
122                     block CPP_INIT,
123                     section .mdns.data,
124                     section .mdns.text
125                    };
126define block .ram.text with fixed order{ section .image2.ram.text*,
127                    };
128define block IMAGE2 with fixed order {  block .ram_image2.entry,
129                    block .ram.data,
130                    block .ram.text,
131                    };
132define block .ram_image2.bss with fixed order{ section .bss*,
133                                        section COMMON,
134                                      };
135define block .ram_image2.skb.bss with fixed order{ section .bdsram.data* };
136define block .ram_heap.data with fixed order{ section .bfsram.data* };
137place in BD_RAM_region  { readwrite,
138                    block IMAGE2,
139                    block .ram_image2.bss,
140                    block .ram_image2.skb.bss,
141                    block .ram_heap.data,
142                    section .heap.stdlib,
143                    last block HEAP,
144                    };
145/****************************************
146 * XIP BOOT Section config                *
147 ****************************************/
148keep { section .flashboot.text* };
149define block .xip_image1.text with fixed order{ section .flashboot.text* };
150define block Bootloader with fixed order { section LOADER };
151place at start of XIP_BOOT_region   {   block Bootloader,
152                    readwrite,
153                     block .xip_image1.text };
154/****************************************
155 * XIP OTA1 Section config                *
156 ****************************************/
157keep { section FSymTab };
158keep { section VSymTab };
159keep { section .rti_fn* };
160define block .xip_image2.text with fixed order{ section .img2_custom_signature*,
161                        section .text*,
162                        section .rodata*,
163                        section .debug_trace,
164                        section CODE,
165                        section Veneer, // object startup.o,
166                        section FSymTab,
167                        section VSymTab,
168                        section .rti_fn*,
169                        };
170place at start of  XIP_OTA1_region   {  readwrite,
171                      block .xip_image2.text };
172/****************************************
173 * RDP Section config                    *
174 ****************************************/
175keep {  section .rdp.ram.text* };
176keep {  section .rdp.ram.data* };
177define block .RDP_RAM with fixed order {
178    section .rdp.ram.text*,
179    section .rdp.ram.data* };
180place at start of  RDP_RAM_region{
181    readwrite,
182    block .RDP_RAM };
183define exported symbol __ram_start_table_start__= 0x10002000;   // use in rom
184define exported symbol __image1_validate_code__= 0x10002018;    // needed by ram code
185define exported symbol __rom_top_4k_start_= 0x1003F000; // needed by ram code
186define exported symbol __flash_text_start__= 0x0800b020; // needed by ram code
187define exported symbol boot_export_symbol = 0x10002020;
188