1 /*!
2  * @file        apm32e10x_dmc.h
3  *
4  * @brief       This file contains all the prototypes,enumeration and macros for the DMC peripheral
5  *
6  * @version     V1.0.2
7  *
8  * @date        2022-12-31
9  *
10  * @attention
11  *
12  *  Copyright (C) 2021-2023 Geehy Semiconductor
13  *
14  *  You may not use this file except in compliance with the
15  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
16  *
17  *  The program is only for reference, which is distributed in the hope
18  *  that it will be useful and instructional for customers to develop
19  *  their software. Unless required by applicable law or agreed to in
20  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
21  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
22  *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
23  *  and limitations under the License.
24  */
25 
26 /* Define to prevent recursive inclusion */
27 #ifndef __APM32E10X_DMC_H
28 #define __APM32E10X_DMC_H
29 
30 /* Includes */
31 #include "apm32e10x.h"
32 
33 #ifdef __cplusplus
34  extern "C" {
35 #endif
36 
37 /** @addtogroup APM32E10x_StdPeriphDriver
38   @{
39 */
40 
41 /** @addtogroup DMC_Driver
42   @{
43 */
44 
45 /** @defgroup DMC_Enumerations Enumerations
46   @{
47 */
48 
49 /**
50  * @brief   Bank Address Width
51  */
52 typedef enum
53 {
54     DMC_BANK_WIDTH_1,
55     DMC_BANK_WIDTH_2
56 }DMC_BANK_WIDTH_T;
57 
58 /**
59  * @brief   Row Address Width
60  */
61 typedef enum
62 {
63     DMC_ROW_WIDTH_11 = 0x0A,
64     DMC_ROW_WIDTH_12,
65     DMC_ROW_WIDTH_13,
66     DMC_ROW_WIDTH_14,
67     DMC_ROW_WIDTH_15,
68     DMC_ROW_WIDTH_16
69 }DMC_ROW_WIDTH_T;
70 
71 /**
72  * @brief   Column Address Width
73  */
74 typedef enum
75 {
76     DMC_COL_WIDTH_8 = 0x07,
77     DMC_COL_WIDTH_9,
78     DMC_COL_WIDTH_10,
79     DMC_COL_WIDTH_11,
80     DMC_COL_WIDTH_12,
81     DMC_COL_WIDTH_13,
82     DMC_COL_WIDTH_14,
83     DMC_COL_WIDTH_15
84 }DMC_COL_WIDTH_T;
85 
86 /**
87  * @brief   CAS Latency Select
88  */
89 typedef enum
90 {
91     DMC_CAS_LATENCY_1,
92     DMC_CAS_LATENCY_2,
93     DMC_CAS_LATENCY_3,
94     DMC_CAS_LATENCY_4
95 }DMC_CAS_LATENCY_T;
96 
97 /**
98  * @brief   RAS Minimun Time Select
99  */
100 typedef enum
101 {
102     DMC_RAS_MINIMUM_1,
103     DMC_RAS_MINIMUM_2,
104     DMC_RAS_MINIMUM_3,
105     DMC_RAS_MINIMUM_4,
106     DMC_RAS_MINIMUM_5,
107     DMC_RAS_MINIMUM_6,
108     DMC_RAS_MINIMUM_7,
109     DMC_RAS_MINIMUM_8,
110     DMC_RAS_MINIMUM_9,
111     DMC_RAS_MINIMUM_10,
112     DMC_RAS_MINIMUM_11,
113     DMC_RAS_MINIMUM_12,
114     DMC_RAS_MINIMUM_13,
115     DMC_RAS_MINIMUM_14,
116     DMC_RAS_MINIMUM_15,
117     DMC_RAS_MINIMUM_16
118 }DMC_RAS_MINIMUM_T;
119 
120 /**
121  * @brief   RAS To CAS Delay Time Select
122  */
123 typedef enum
124 {
125     DMC_DELAY_TIME_1,
126     DMC_DELAY_TIME_2,
127     DMC_DELAY_TIME_3,
128     DMC_DELAY_TIME_4,
129     DMC_DELAY_TIME_5,
130     DMC_DELAY_TIME_6,
131     DMC_DELAY_TIME_7,
132     DMC_DELAY_TIME_8
133 }DMC_DELAY_TIME_T;
134 
135 /**
136  * @brief   Precharge Period Select
137  */
138 typedef enum
139 {
140     DMC_PRECHARGE_1,
141     DMC_PRECHARGE_2,
142     DMC_PRECHARGE_3,
143     DMC_PRECHARGE_4,
144     DMC_PRECHARGE_5,
145     DMC_PRECHARGE_6,
146     DMC_PRECHARGE_7,
147     DMC_PRECHARGE_8
148 }DMC_PRECHARGE_T;
149 
150 /**
151  * @brief   Last Data Next Precharge For Write Time Select
152  */
153 typedef enum
154 {
155     DMC_NEXT_PRECHARGE_1,
156     DMC_NEXT_PRECHARGE_2,
157     DMC_NEXT_PRECHARGE_3,
158     DMC_NEXT_PRECHARGE_4
159 }DMC_NEXT_PRECHARGE_T;
160 
161 /**
162  * @brief   Auto-Refresh Period Select
163  */
164 typedef enum
165 {
166     DMC_AUTO_REFRESH_1,
167     DMC_AUTO_REFRESH_2,
168     DMC_AUTO_REFRESH_3,
169     DMC_AUTO_REFRESH_4,
170     DMC_AUTO_REFRESH_5,
171     DMC_AUTO_REFRESH_6,
172     DMC_AUTO_REFRESH_7,
173     DMC_AUTO_REFRESH_8,
174     DMC_AUTO_REFRESH_9,
175     DMC_AUTO_REFRESH_10,
176     DMC_AUTO_REFRESH_11,
177     DMC_AUTO_REFRESH_12,
178     DMC_AUTO_REFRESH_13,
179     DMC_AUTO_REFRESH_14,
180     DMC_AUTO_REFRESH_15,
181     DMC_AUTO_REFRESH_16
182 }DMC_AUTO_REFRESH_T;
183 
184 /**
185  * @brief   Active-to-active Command Period Select
186  */
187 typedef enum
188 {
189     DMC_ATA_CMD_1,
190     DMC_ATA_CMD_2,
191     DMC_ATA_CMD_3,
192     DMC_ATA_CMD_4,
193     DMC_ATA_CMD_5,
194     DMC_ATA_CMD_6,
195     DMC_ATA_CMD_7,
196     DMC_ATA_CMD_8,
197     DMC_ATA_CMD_9,
198     DMC_ATA_CMD_10,
199     DMC_ATA_CMD_11,
200     DMC_ATA_CMD_12,
201     DMC_ATA_CMD_13,
202     DMC_ATA_CMD_14,
203     DMC_ATA_CMD_15,
204     DMC_ATA_CMD_16
205 }DMC_ATA_CMD_T;
206 
207 /**
208  * @brief   Clock PHASE
209  */
210 typedef enum
211 {
212     DMC_CLK_PHASE_NORMAL,
213     DMC_CLK_PHASE_REVERSE
214 }DMC_CLK_PHASE_T;
215 
216 /**
217  * @brief   DMC Memory Size
218  */
219 typedef enum
220 {
221     DMC_MEMORY_SIZE_0,
222     DMC_MEMORY_SIZE_64KB,
223     DMC_MEMORY_SIZE_128KB,
224     DMC_MEMORY_SIZE_256KB,
225     DMC_MEMORY_SIZE_512KB,
226     DMC_MEMORY_SIZE_1MB,
227     DMC_MEMORY_SIZE_2MB,
228     DMC_MEMORY_SIZE_4MB,
229     DMC_MEMORY_SIZE_8MB,
230     DMC_MEMORY_SIZE_16MB,
231     DMC_MEMORY_SIZE_32MB,
232     DMC_MEMORY_SIZE_64MB,
233     DMC_MEMORY_SIZE_128MB,
234     DMC_MEMORY_SIZE_256MB
235 }DMC_MEMORY_SIZE_T;
236 
237 /**
238  * @brief    Open Banks Of Number
239  */
240 typedef enum
241 {
242     DMC_BANK_NUMBER_1,
243     DMC_BANK_NUMBER_2,
244     DMC_BANK_NUMBER_3,
245     DMC_BANK_NUMBER_4,
246     DMC_BANK_NUMBER_5,
247     DMC_BANK_NUMBER_6,
248     DMC_BANK_NUMBER_7,
249     DMC_BANK_NUMBER_8,
250     DMC_BANK_NUMBER_9,
251     DMC_BANK_NUMBER_10,
252     DMC_BANK_NUMBER_11,
253     DMC_BANK_NUMBER_12,
254     DMC_BANK_NUMBER_13,
255     DMC_BANK_NUMBER_14,
256     DMC_BANK_NUMBER_15,
257     DMC_BANK_NUMBER_16
258 }DMC_BANK_NUMBER_T;
259 
260 /**
261  * @brief   Full refresh type
262  */
263 typedef enum
264 {
265     DMC_REFRESH_ROW_ONE,        /*!< Refresh one row */
266     DMC_REFRESH_ROW_ALL         /*!< Refresh all row */
267 }DMC_REFRESH_T;
268 
269 /**
270  * @brief   Precharge type
271  */
272 typedef enum
273 {
274     DMC_PRECHARGE_IM,        /*!< Immediate precharge */
275     DMC_PRECHARGE_DELAY      /*!< Delayed precharge */
276 }DMC_PRECHARE_T;
277 
278 /**
279  * @brief WRAP Burst Type
280  */
281 typedef enum
282 {
283     DMC_WRAPB_4,
284     DMC_WRAPB_8
285 }DMC_WRPB_T;
286 
287 /**@} end of group DMC_Enumerations */
288 
289 
290 /** @defgroup DMC_Structures Structures
291   @{
292 */
293 
294 /**
295  * @brief   Timing config definition
296  */
297 typedef struct
298 {
299     uint32_t    latencyCAS  : 2;       /*!< DMC_CAS_LATENCY_T */
300     uint32_t    tRAS        : 4;       /*!< DMC_RAS_MINIMUM_T */
301     uint32_t    tRCD        : 3;       /*!< DMC_DELAY_TIME_T */
302     uint32_t    tRP         : 3;       /*!< DMC_PRECHARGE_T */
303     uint32_t    tWR         : 2;       /*!< DMC_NEXT_PRECHARGE_T */
304     uint32_t    tARP        : 4;       /*!< DMC_AUTO_REFRESH_T */
305     uint32_t    tCMD        : 4;       /*!< DMC_ATA_CMD_T */
306     uint32_t    tXSR        : 9;       /*!< auto-refresh commands, can be 0x000 to 0x1FF */
307     uint16_t    tRFP        : 16;      /*!< Refresh period, can be 0x0000 to 0xFFFF */
308 }DMC_TimingConfig_T;
309 
310 /**
311  * @brief   Config struct definition
312  */
313 typedef struct
314 {
315     DMC_MEMORY_SIZE_T       memorySize;    /*!< Memory size(byte) */
316     DMC_BANK_WIDTH_T        bankWidth;     /*!< Number of bank bits */
317     DMC_ROW_WIDTH_T         rowWidth;      /*!< Number of row address bits */
318     DMC_COL_WIDTH_T         colWidth;      /*!< Number of col address bits */
319     DMC_CLK_PHASE_T         clkPhase;      /*!< Clock phase */
320     DMC_TimingConfig_T      timing;        /*!< Timing */
321 }DMC_Config_T;
322 
323 /**@} end of group DMC_Structures */
324 
325 
326 /** @defgroup DMC_Functions
327   @{
328 */
329 
330  /* Enable / Disable */
331 void DMC_Enable(void);
332 void DMC_Disable(void);
333 void DMC_EnableInit(void);
334 
335 /* Global config */
336 void DMC_Config(DMC_Config_T *dmcConfig);
337 void DMC_ConfigStructInit(DMC_Config_T *dmcConfig);
338 
339 /* Address */
340 void DMC_ConfigBankWidth(DMC_BANK_WIDTH_T bankWidth);
341 void DMC_ConfigAddrWidth(DMC_ROW_WIDTH_T rowWidth, DMC_COL_WIDTH_T colWidth);
342 
343 /* Timing */
344 void DMC_ConfigTiming(DMC_TimingConfig_T *timingConfig);
345 void DMC_ConfigTimingStructInit(DMC_TimingConfig_T *timingConfig);
346 void DMC_ConfigStableTimePowerup(uint16_t stableTime);
347 void DMC_ConfigAutoRefreshNumDuringInit(DMC_AUTO_REFRESH_T num);
348 void DMC_ConfigRefreshPeriod(uint16_t period);
349 
350 /* Refresh mode */
351 void DMC_EixtSlefRefreshMode(void);
352 void DMC_EnterSlefRefreshMode(void);
353 
354 /* Accelerate Module */
355 void DMC_EnableAccelerateModule(void);
356 void DMC_DisableAccelerateModule(void);
357 /* Config */
358 void DMC_ConfigOpenBank(DMC_BANK_NUMBER_T num);
359 void DMC_EnableUpdateMode(void);
360 void DMC_EnterPowerdownMode(void);
361 void DMC_ConfigFullRefreshBeforeSR(DMC_REFRESH_T refresh);
362 void DMC_ConfigFullRefreshAfterSR(DMC_REFRESH_T refresh);
363 void DMC_ConfigPrechargeType(DMC_PRECHARE_T precharge);
364 void DMC_ConfigMemorySize(DMC_MEMORY_SIZE_T memorySize);
365 void DMC_ConfigClockPhase(DMC_CLK_PHASE_T clkPhase);
366 void DMC_ConfigWRAPB(DMC_WRPB_T burst);
367 
368 /* read flag */
369 uint8_t DMC_ReadSelfRefreshStatus(void);
370 
371 /**@} end of group DMC_Functions */
372 /**@} end of group DMC_Driver*/
373 /**@} end of group APM32E10x_StdPeriphDriver*/
374 
375 #ifdef __cplusplus
376 }
377 #endif
378 
379 #endif  /* __APM32E10X_DMC_H */
380