1 /*! 2 * @file apm32e10x_rcm.h 3 * 4 * @brief This file contains all the functions prototypes for the RCM firmware library 5 * 6 * @version V1.0.2 7 * 8 * @date 2022-12-31 9 * 10 * @attention 11 * 12 * Copyright (C) 2021-2023 Geehy Semiconductor 13 * 14 * You may not use this file except in compliance with the 15 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). 16 * 17 * The program is only for reference, which is distributed in the hope 18 * that it will be useful and instructional for customers to develop 19 * their software. Unless required by applicable law or agreed to in 20 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT 21 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions 23 * and limitations under the License. 24 */ 25 26 /* Define to prevent recursive inclusion */ 27 #ifndef __APM32E10X_RCM_H 28 #define __APM32E10X_RCM_H 29 30 /* Includes */ 31 #include "apm32e10x.h" 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 /** @addtogroup APM32E10x_StdPeriphDriver 38 @{ 39 */ 40 41 /** @addtogroup RCM_Driver 42 @{ 43 */ 44 45 /** @defgroup RCM_Enumerations Enumerations 46 @{ 47 */ 48 49 /** 50 * @brief HSE state 51 */ 52 typedef enum 53 { 54 RCM_HSE_CLOSE, /*!< CLOSE HSE */ 55 RCM_HSE_OPEN, /*!< OPEN HSE */ 56 RCM_HSE_BYPASS, /*!< HSE BYPASS */ 57 } RCM_HSE_T; 58 59 /** 60 * @brief PLL multiplication factor 61 */ 62 typedef enum 63 { 64 RCM_PLLMF_2, 65 RCM_PLLMF_3, 66 RCM_PLLMF_4, 67 RCM_PLLMF_5, 68 RCM_PLLMF_6, 69 RCM_PLLMF_7, 70 RCM_PLLMF_8, 71 RCM_PLLMF_9, 72 RCM_PLLMF_10, 73 RCM_PLLMF_11, 74 RCM_PLLMF_12, 75 RCM_PLLMF_13, 76 RCM_PLLMF_14, 77 RCM_PLLMF_15, 78 RCM_PLLMF_16 79 } RCM_PLLMF_T; 80 81 /** 82 * @brief System clock select 83 */ 84 typedef enum 85 { 86 RCM_SYSCLK_SEL_HSI, 87 RCM_SYSCLK_SEL_HSE, 88 RCM_SYSCLK_SEL_PLL 89 } RCM_SYSCLK_SEL_T; 90 91 /** 92 * @brief AHB divider Number 93 */ 94 typedef enum 95 { 96 RCM_AHB_DIV_1 = 7, 97 RCM_AHB_DIV_2, 98 RCM_AHB_DIV_4, 99 RCM_AHB_DIV_8, 100 RCM_AHB_DIV_16, 101 RCM_AHB_DIV_64, 102 RCM_AHB_DIV_128, 103 RCM_AHB_DIV_256, 104 RCM_AHB_DIV_512 105 } RCM_AHB_DIV_T; 106 107 /** 108 * @brief APB divider Number 109 */ 110 typedef enum 111 { 112 RCM_APB_DIV_1 = 3, 113 RCM_APB_DIV_2, 114 RCM_APB_DIV_4, 115 RCM_APB_DIV_8, 116 RCM_APB_DIV_16 117 } RCM_APB_DIV_T; 118 119 /** 120 * @brief USB divider Number 121 */ 122 typedef enum 123 { 124 RCM_USB_DIV_1_5, 125 RCM_USB_DIV_1, 126 RCM_USB_DIV_2, 127 RCM_USB_DIV_2_5 128 } RCM_USB_DIV_T; 129 130 /** 131 * @brief FPU divider Number 132 */ 133 typedef enum 134 { 135 RCM_FPU_DIV_1, 136 RCM_FPU_DIV_2 137 } RCM_FPU_DIV_T; 138 139 /** 140 * @brief ADC divider Number 141 */ 142 typedef enum 143 { 144 RCM_PCLK2_DIV_2, 145 RCM_PCLK2_DIV_4, 146 RCM_PCLK2_DIV_6, 147 RCM_PCLK2_DIV_8 148 } RCM_PCLK2_DIV_T; 149 150 /** 151 * @brief LSE State 152 */ 153 typedef enum 154 { 155 RCM_LSE_CLOSE, 156 RCM_LSE_OPEN, 157 RCM_LSE_BYPASS 158 } RCM_LSE_T; 159 160 /** 161 * @brief RTC clock select 162 */ 163 typedef enum 164 { 165 RCM_RTCCLK_LSE = 1, 166 RCM_RTCCLK_LSI, 167 RCM_RTCCLK_HSE_DIV_128 168 } RCM_RTCCLK_T; 169 170 /** 171 * @brief Clock output control 172 */ 173 typedef enum 174 { 175 RCM_MCOCLK_NO_CLOCK = 3, 176 RCM_MCOCLK_SYSCLK, 177 RCM_MCOCLK_HSI, 178 RCM_MCOCLK_HSE, 179 RCM_MCOCLK_PLLCLK_DIV_2 180 } RCM_MCOCLK_T; 181 182 /** 183 * @brief PLL entry clock select 184 */ 185 typedef enum 186 { 187 RCM_PLLSEL_HSI_DIV_2 = 0, 188 RCM_PLLSEL_HSE = 1, 189 RCM_PLLSEL_HSE_DIV2 = 3, 190 } RCM_PLLSEL_T; 191 192 /** 193 * @brief RCM Interrupt Source 194 */ 195 typedef enum 196 { 197 RCM_INT_LSIRDY = BIT0, /*!< LSI ready interrupt */ 198 RCM_INT_LSERDY = BIT1, /*!< LSE ready interrupt */ 199 RCM_INT_HSIRDY = BIT2, /*!< HSI ready interrupt */ 200 RCM_INT_HSERDY = BIT3, /*!< HSE ready interrupt */ 201 RCM_INT_PLLRDY = BIT4, /*!< PLL ready interrupt */ 202 RCM_INT_CSS = BIT7 /*!< Clock security system interrupt */ 203 } RCM_INT_T; 204 205 /** 206 * @brief AHB peripheral 207 */ 208 typedef enum 209 { 210 RCM_AHB_PERIPH_DMA1 = BIT0, 211 RCM_AHB_PERIPH_DMA2 = BIT1, 212 RCM_AHB_PERIPH_SRAM = BIT2, 213 RCM_AHB_PERIPH_FPU = BIT3, 214 RCM_AHB_PERIPH_FMC = BIT4, 215 RCM_AHB_PERIPH_QSPI = BIT5, 216 RCM_AHB_PERIPH_CRC = BIT6, 217 RCM_AHB_PERIPH_SMC = BIT8, 218 RCM_AHB_PERIPH_SDIO = BIT10 219 } RCM_AHB_PERIPH_T; 220 221 /** 222 * @brief AHB2 peripheral 223 */ 224 typedef enum 225 { 226 RCM_APB2_PERIPH_AFIO = BIT0, 227 RCM_APB2_PERIPH_GPIOA = BIT2, 228 RCM_APB2_PERIPH_GPIOB = BIT3, 229 RCM_APB2_PERIPH_GPIOC = BIT4, 230 RCM_APB2_PERIPH_GPIOD = BIT5, 231 RCM_APB2_PERIPH_GPIOE = BIT6, 232 RCM_APB2_PERIPH_GPIOF = BIT7, 233 RCM_APB2_PERIPH_GPIOG = BIT8, 234 RCM_APB2_PERIPH_ADC1 = BIT9, 235 RCM_APB2_PERIPH_ADC2 = BIT10, 236 RCM_APB2_PERIPH_TMR1 = BIT11, 237 RCM_APB2_PERIPH_SPI1 = BIT12, 238 RCM_APB2_PERIPH_TMR8 = BIT13, 239 RCM_APB2_PERIPH_USART1 = BIT14, 240 RCM_APB2_PERIPH_ADC3 = BIT15 241 } RCM_APB2_PERIPH_T; 242 243 /** 244 * @brief AHB1 peripheral 245 */ 246 typedef enum 247 { 248 RCM_APB1_PERIPH_TMR2 = BIT0, 249 RCM_APB1_PERIPH_TMR3 = BIT1, 250 RCM_APB1_PERIPH_TMR4 = BIT2, 251 RCM_APB1_PERIPH_TMR5 = BIT3, 252 RCM_APB1_PERIPH_TMR6 = BIT4, 253 RCM_APB1_PERIPH_TMR7 = BIT5, 254 RCM_APB1_PERIPH_WWDT = BIT11, 255 RCM_APB1_PERIPH_SPI2 = BIT14, 256 RCM_APB1_PERIPH_SPI3 = BIT15, 257 RCM_APB1_PERIPH_USART2 = BIT17, 258 RCM_APB1_PERIPH_USART3 = BIT18, 259 RCM_APB1_PERIPH_UART4 = BIT19, 260 RCM_APB1_PERIPH_UART5 = BIT20, 261 RCM_APB1_PERIPH_I2C1 = BIT21, 262 RCM_APB1_PERIPH_I2C2 = BIT22, 263 RCM_APB1_PERIPH_USB = BIT23, 264 RCM_APB1_PERIPH_CAN1 = BIT25, 265 RCM_APB1_PERIPH_CAN2 = BIT26, 266 RCM_APB1_PERIPH_BAKR = BIT27, 267 RCM_APB1_PERIPH_PMU = BIT28, 268 RCM_APB1_PERIPH_DAC = BIT29 269 } RCM_APB1_PERIPH_T; 270 271 /** 272 * @brief RCM FLAG define 273 */ 274 typedef enum 275 { 276 RCM_FLAG_HSIRDY = 0x001, /*!< HSI Ready Flag */ 277 RCM_FLAG_HSERDY = 0x011, /*!< HSE Ready Flag */ 278 RCM_FLAG_PLLRDY = 0x019, /*!< PLL Ready Flag */ 279 RCM_FLAG_LSERDY = 0x101, /*!< LSE Ready Flag */ 280 RCM_FLAG_LSIRDY = 0x201, /*!< LSI Ready Flag */ 281 RCM_FLAG_PINRST = 0x21A, /*!< PIN reset flag */ 282 RCM_FLAG_PORRST = 0x21B, /*!< POR/PDR reset flag */ 283 RCM_FLAG_SWRST = 0x21C, /*!< Software reset flag */ 284 RCM_FLAG_IWDTRST = 0x21D, /*!< Independent watchdog reset flag */ 285 RCM_FLAG_WWDTRST = 0x21E, /*!< Window watchdog reset flag */ 286 RCM_FLAG_LPRRST = 0x21F /*!< Low-power reset flag */ 287 } RCM_FLAG_T; 288 289 /**@} end of group RCM_Enumerations */ 290 291 292 /** @defgroup RCM_Functions Functions 293 @{ 294 */ 295 296 /* Function description */ 297 298 /* RCM Reset */ 299 void RCM_Reset(void); 300 301 /* HSE clock */ 302 void RCM_ConfigHSE(RCM_HSE_T state); 303 uint8_t RCM_WaitHSEReady(void); 304 305 /* HSI clock */ 306 void RCM_ConfigHSITrim(uint8_t HSITrim); 307 void RCM_EnableHSI(void); 308 void RCM_DisableHSI(void); 309 310 /* LSE and LSI clock */ 311 void RCM_ConfigLSE(RCM_LSE_T state); 312 void RCM_EnableLSI(void); 313 void RCM_DisableLSI(void); 314 315 /* PLL clock */ 316 void RCM_ConfigPLL(RCM_PLLSEL_T pllSelect, RCM_PLLMF_T pllMf); 317 void RCM_EnablePLL(void); 318 void RCM_DisablePLL(void); 319 320 /* Clock Security System */ 321 void RCM_EnableCSS(void); 322 void RCM_DisableCSS(void); 323 324 void RCM_ConfigMCO(RCM_MCOCLK_T mcoClock); 325 void RCM_ConfigSYSCLK(RCM_SYSCLK_SEL_T sysClkSelect); 326 RCM_SYSCLK_SEL_T RCM_ReadSYSCLKSource(void); 327 328 /* Config clock prescaler of AHB, APB1, APB2, USB and ADC */ 329 void RCM_ConfigAHB(RCM_AHB_DIV_T AHBDiv); 330 void RCM_ConfigAPB1(RCM_APB_DIV_T APB1Div); 331 void RCM_ConfigAPB2(RCM_APB_DIV_T APB2Div); 332 void RCM_ConfigUSBCLK(RCM_USB_DIV_T USBDiv); 333 void RCM_ConfigFPUCLK(RCM_FPU_DIV_T FPUDiv); 334 void RCM_ConfigADCCLK(RCM_PCLK2_DIV_T ADCDiv); 335 336 /* RTC clock */ 337 void RCM_ConfigRTCCLK(RCM_RTCCLK_T rtcClkSelect); 338 void RCM_EnableRTCCLK(void); 339 void RCM_DisableRTCCLK(void); 340 341 /* Reads the clock frequency */ 342 uint32_t RCM_ReadSYSCLKFreq(void); 343 uint32_t RCM_ReadHCLKFreq(void); 344 void RCM_ReadPCLKFreq(uint32_t* PCLK1, uint32_t* PCLK2); 345 uint32_t RCM_ReadADCCLKFreq(void); 346 347 /* Enable or disable Periph Clock */ 348 void RCM_EnableAHBPeriphClock(uint32_t AHBPeriph); 349 void RCM_DisableAHBPeriphClock(uint32_t AHBPeriph); 350 void RCM_EnableAPB2PeriphClock(uint32_t APB2Periph); 351 void RCM_DisableAPB2PeriphClock(uint32_t APB2Periph); 352 void RCM_EnableAPB1PeriphClock(uint32_t APB1Periph); 353 void RCM_DisableAPB1PeriphClock(uint32_t APB1Periph); 354 355 /* Enable or disable Periph Reset */ 356 void RCM_EnableAPB2PeriphReset(uint32_t APB2Periph); 357 void RCM_DisableAPB2PeriphReset(uint32_t APB2Periph); 358 void RCM_EnableAPB1PeriphReset(uint32_t APB1Periph); 359 void RCM_DisableAPB1PeriphReset(uint32_t APB1Periph); 360 361 /* Backup domain reset */ 362 void RCM_EnableBackupReset(void); 363 void RCM_DisableBackupReset(void); 364 365 /* Interrupts and flags */ 366 void RCM_EnableInterrupt(uint32_t interrupt); 367 void RCM_DisableInterrupt(uint32_t interrupt); 368 uint8_t RCM_ReadStatusFlag(RCM_FLAG_T flag); 369 void RCM_ClearStatusFlag(void); 370 uint8_t RCM_ReadIntFlag(RCM_INT_T flag); 371 void RCM_ClearIntFlag(uint32_t flag); 372 373 /**@} end of group RCM_Functions */ 374 /**@} end of group RCM_Driver */ 375 /**@} end of group APM32E10x_StdPeriphDriver*/ 376 377 #ifdef __cplusplus 378 } 379 #endif 380 381 #endif /* __APM32E10X_RCM_H */ 382