1 /*! 2 * @file apm32e10x_sci2c.h 3 * 4 * @brief This file contains all the prototypes,enumeration and macros for the SCI2C(I2C3, I2C4) peripheral 5 * 6 * @version V1.0.2 7 * 8 * @date 2022-12-31 9 * 10 * @attention 11 * 12 * Copyright (C) 2021-2023 Geehy Semiconductor 13 * 14 * You may not use this file except in compliance with the 15 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). 16 * 17 * The program is only for reference, which is distributed in the hope 18 * that it will be useful and instructional for customers to develop 19 * their software. Unless required by applicable law or agreed to in 20 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT 21 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions 23 * and limitations under the License. 24 */ 25 26 /* Define to prevent recursive inclusion */ 27 #ifndef __APM32E10X_SCI2C_H 28 #define __APM32E10X_SCI2C_H 29 30 /* Includes */ 31 #include "apm32e10x.h" 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 /** @addtogroup APM32E10x_StdPeriphDriver 38 @{ 39 */ 40 41 /** @addtogroup SCI2C_Driver 42 @{ 43 */ 44 45 /** @defgroup SCI2C_Macros Macros 46 @{ 47 */ 48 49 /* Macros description */ 50 51 #define SCI2C_CTRL1_RESET_VALUE ((uint32_t)0x3E) 52 #define SCI2C_TARADDR_RESET_VALUE ((uint32_t)0x1055) 53 #define SCI2C_SLAADDR_RESET_VALUE ((uint32_t)0x55) 54 #define SCI2C_HSMC_RESET_VALUE ((uint32_t)0x07) 55 #define SCI2C_DATA_RESET_VALUE ((uint32_t)0x00) 56 #define SCI2C_SSCHC_RESET_VALUE ((uint32_t)0x190) 57 #define SCI2C_SSCLC_RESET_VALUE ((uint32_t)0x1D6) 58 #define SCI2C_FSCHC_RESET_VALUE ((uint32_t)0x3C) 59 #define SCI2C_FSCLC_RESET_VALUE ((uint32_t)0x82) 60 #define SCI2C_HSCHC_RESET_VALUE ((uint32_t)0x06) 61 #define SCI2C_HSCLC_RESET_VALUE ((uint32_t)0x10) 62 #define SCI2C_INTEN_RESET_VALUE ((uint32_t)0x00) 63 #define SCI2C_RFT_RESET_VALUE ((uint32_t)0x00) 64 #define SCI2C_TFT_RESET_VALUE ((uint32_t)0x00) 65 #define SCI2C_CTRL2_RESET_VALUE ((uint32_t)0x00) 66 #define SCI2C_TFL_RESET_VALUE ((uint32_t)0x00) 67 #define SCI2C_RFL_RESET_VALUE ((uint32_t)0x00) 68 #define SCI2C_SDAHOLD_RESET_VALUE ((uint32_t)0x01) 69 #define SCI2C_SDNO_RESET_VALUE ((uint32_t)0x00) 70 #define SCI2C_DMACTRL_RESET_VALUE ((uint32_t)0x00) 71 #define SCI2C_DTDL_RESET_VALUE ((uint32_t)0x00) 72 #define SCI2C_DRDL_RESET_VALUE ((uint32_t)0x00) 73 #define SCI2C_SDADLY_RESET_VALUE ((uint32_t)0x64) 74 #define SCI2C_GCA_RESET_VALUE ((uint32_t)0x01) 75 #define SCI2C_LSSSL_RESET_VALUE ((uint32_t)0x05) 76 #define SCI2C_HSSSL_RESET_VALUE ((uint32_t)0x01) 77 78 #define SCI2C_FIFO_DEPTH (0X08) 79 /**@} end of group SCI2C_Macros */ 80 81 /** @defgroup SCI2C_Enumerations Enumerations 82 @{ 83 */ 84 85 /** 86 * @brief SCI2C speed enumeration 87 */ 88 typedef enum 89 { 90 SCI2C_SPEED_STANDARD = 1, 91 SCI2C_SPEED_FAST, 92 SCI2C_SPEED_HIGH 93 }SCI2C_SPEED_T; 94 95 /** 96 * @brief Address mode 97 */ 98 typedef enum 99 { 100 SCI2C_ADDR_MODE_7BIT, 101 SCI2C_ADDR_MODE_10BIT 102 }SCI2C_ADDR_MODE_T; 103 104 /** 105 * @brief SCI2C mode enumeration 106 */ 107 typedef enum 108 { 109 SCI2C_MODE_MASTER, 110 SCI2C_MODE_SLAVE 111 }SCI2C_MODE_T; 112 113 /** 114 * @brief Restart enable or disable 115 */ 116 typedef enum 117 { 118 SCI2C_RESTART_DISABLE, 119 SCI2C_RESTART_ENABLE 120 }SCI2C_RESTART_T; 121 122 /** 123 * @brief Enable or disable generate stop condition 124 */ 125 typedef enum 126 { 127 SCI2C_STOP_DISABLE, 128 SCI2C_STOP_ENABLE 129 }SCI2C_STOP_T; 130 /** 131 * @brief Data direction 132 */ 133 typedef enum 134 { 135 SCI2C_DATA_DIR_WRITE, 136 SCI2C_DATA_DIR_READ, 137 }SCI2C_DATA_DIR_T; 138 139 /** 140 * @brief SCI2C interrupt 141 */ 142 typedef enum 143 { 144 SCI2C_INT_RFU = BIT0, /*!< Rx FIFO underflow interrupt */ 145 SCI2C_INT_RFO = BIT1, /*!< Rx FIFO onverflow interrupt */ 146 SCI2C_INT_RFF = BIT2, /*!< Rx FIFO full interrupt */ 147 SCI2C_INT_TFO = BIT3, /*!< Tx FIFO onverflow interrupt */ 148 SCI2C_INT_TFE = BIT4, /*!< Tx FIFO empty interrupt */ 149 SCI2C_INT_RR = BIT5, /*!< Read request interrupt */ 150 SCI2C_INT_TA = BIT6, /*!< Tx abort interrupt */ 151 SCI2C_INT_RD = BIT7, /*!< Read done interrupt */ 152 SCI2C_INT_ACT = BIT8, /*!< Activity interrupt */ 153 SCI2C_INT_STPD = BIT9, /*!< Stop detect interrupt */ 154 SCI2C_INT_STAD = BIT10, /*!< Start detect interrupt */ 155 SCI2C_INT_GC = BIT11, /*!< Gernal call interrupt */ 156 SCI2C_INT_RSTAD = BIT12, /*!< Restart detect interrupt */ 157 SCI2C_INT_MOH = BIT13, /*!< Master on hold interrupt */ 158 SCI2C_INT_ALL = BIT15 /*!< All interrupt */ 159 }SCI2C_INT_T; 160 161 /** 162 * @brief Flag enumeration 163 */ 164 typedef enum 165 { 166 SCI2C_FLAG_ACT = BIT0, /*!< Activity flag */ 167 SCI2C_FLAG_TFNF = BIT1, /*!< Tx FIFO not full flag */ 168 SCI2C_FLAG_TFE = BIT2, /*!< Tx FIFO empty flag */ 169 SCI2C_FLAG_RFNE = BIT3, /*!< Rx FIFO not empty flag */ 170 SCI2C_FLAG_RFF = BIT4, /*!< Rx FIFO full flag */ 171 SCI2C_FLAG_MA = BIT5, /*!< Master activity flag */ 172 SCI2C_FLAG_SA = BIT6, /*!< Slave activity flag */ 173 SCI2C_FLAG_I2CEN = BIT8 | BIT0, /*!< I2C enable flag */ 174 SCI2C_FLAG_SDWB = BIT8 | BIT1, /*!< Slave disable while busy flag */ 175 SCI2C_FLAG_SRDL = BIT8 | BIT2 /*!< Slave receive data lost flag */ 176 }SCI2C_FLAG_T; 177 178 /** 179 * @brief Tx abort source 180 */ 181 typedef enum 182 { 183 SCI2C_TAS_AD7NA = BIT0, /*!< 7 bit address mode NACK */ 184 SCI2C_TAS_AD10FBNA = BIT1, /*!< 10 bit address mode first byte NACK */ 185 SCI2C_TAS_AD10SBNA = BIT2, /*!< 10 bit address mode second byte NACK */ 186 SCI2C_TAS_TDNA = BIT3, /*!< Tx data NACK */ 187 SCI2C_TAS_GCNA = BIT4, /*!< Gernal call NACK */ 188 SCI2C_TAS_GCR = BIT5, /*!< Gernal call read */ 189 SCI2C_TAS_HSAD = BIT6, /*!< High speed ack detected */ 190 SCI2C_TAS_SNR = BIT7, /*!< Start byte no restart */ 191 SCI2C_TAS_RNR10B = BIT8, /*!< Read 10bit address mode when restart disable */ 192 SCI2C_TAS_MSTDIS = BIT9, /*!< Master disable */ 193 SCI2C_TAS_ARBLOST = BIT10, /*!< Arbitration lost */ 194 SCI2C_TAS_LFTF = BIT11, /*!< Slave flush tx FIFO */ 195 SCI2C_TAS_SAL = BIT12, /*!< Slave arbitration lost */ 196 SCI2C_TAS_SRI = BIT13, /*!< Slave read done */ 197 SCI2C_TAS_USRARB = BIT14, /*!< User abort */ 198 SCI2C_TAS_FLUCNT = BIT15 /*!< Tx flush counter */ 199 }SCI2C_TAS_T; 200 201 /** 202 * @brief DMA Enable 203 */ 204 typedef enum 205 { 206 SCI2C_DMA_RX = BIT0, 207 SCI2C_DMA_TX = BIT1, 208 }SCI2C_DMA_T; 209 210 /**@} end of group SCI2C_Enumerations */ 211 212 /** @defgroup SCI2C_Structures 213 @{ 214 */ 215 216 /** 217 * @brief Struct description 218 */ 219 typedef struct 220 { 221 uint16_t slaveAddr; /*!< Slave address. */ 222 SCI2C_MODE_T mode; /*!< Specifies mode, master mode or slave mode */ 223 SCI2C_SPEED_T speed; /*!< Specifies speed. Standard speed, fast speed or high speed. */ 224 uint16_t clkLowPeriod; /*!< SCL high period */ 225 uint16_t clkHighPeriod; /*!< SCL low period */ 226 uint8_t rxFifoThreshold; /*!< Rx FIFO threshold */ 227 uint8_t txFifoThreshold; /*!< Tx FIFO threshold */ 228 SCI2C_RESTART_T restart; /*!< Enable or disable restart */ 229 SCI2C_ADDR_MODE_T addrMode; /*!< Address mode. 7-bit or 10-bit mode. */ 230 }SCI2C_Config_T; 231 232 /**@} end of group SCI2C_Structures */ 233 234 235 /** @defgroup SCI2C_Functions Functions 236 @{ 237 */ 238 239 /* Reset */ 240 void SCI2C_Reset(SCI2C_T *i2c); 241 242 /* Configuration */ 243 void SCI2C_Config(SCI2C_T *i2c, SCI2C_Config_T *sci2cConfig); 244 void SCI2C_ConfigStructInit(SCI2C_Config_T *sci2cConfig); 245 246 /* Stop detect */ 247 void SCI2C_EnableStopDetectAddressed(SCI2C_T *i2c); 248 void SCI2C_DisableStopDetectAddressed(SCI2C_T *i2c); 249 void SCI2C_EnableStopDetectMasterActivity(SCI2C_T *i2c); 250 void SCI2C_DisableStopDetectMasterActivity(SCI2C_T *i2c); 251 252 /* Restart */ 253 void SCI2C_EnableRestart(SCI2C_T *i2c); 254 void SCI2C_DisableRestart(SCI2C_T *i2c); 255 256 /* Speed */ 257 void SCI2C_ConfigSpeed(SCI2C_T *i2c, SCI2C_SPEED_T speed); 258 259 /* Address */ 260 void SCI2C_ConfigMasterAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr); 261 void SCI2C_ConfigSlaveAddr(SCI2C_T *i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr); 262 263 /* Master mode and slave mode */ 264 void SCI2C_EnableMasterMode(SCI2C_T *i2c); 265 void SCI2C_DisableMasterMode(SCI2C_T *i2c); 266 void SCI2C_EnableSlaveMode(SCI2C_T *i2c); 267 void SCI2C_DisableSlaveMode(SCI2C_T *i2c); 268 void SCI2C_ConfigMasterCode(SCI2C_T *i2c, uint8_t code); 269 270 /* Data */ 271 void SCI2C_ConfigDataDir(SCI2C_T *i2c, SCI2C_DATA_DIR_T dir); 272 void SCI2C_TxData(SCI2C_T *i2c, uint8_t data); 273 uint8_t SCI2C_RxData(SCI2C_T *i2c); 274 void SCI2C_ConfigDataRegister(SCI2C_T *i2c, SCI2C_STOP_T stop, SCI2C_DATA_DIR_T dataDir, uint8_t data); 275 276 /* Rx and Tx FIFO */ 277 uint8_t SCI2C_ReadRxFifoDataCnt(SCI2C_T *i2c); 278 uint8_t SCI2C_ReadTxFifoDataCnt(SCI2C_T *i2c); 279 void SCI2C_ConfigRxFifoThreshold(SCI2C_T *i2c, uint8_t threshold); 280 void SCI2C_ConfigTxFifoThreshold(SCI2C_T *i2c, uint8_t threshold); 281 282 /* I2C Enable, disable, abort, block */ 283 void SCI2C_Enable(SCI2C_T *i2c); 284 void SCI2C_Disable(SCI2C_T *i2c); 285 void SCI2C_Abort(SCI2C_T *i2c); 286 void SCI2C_BlockTxCmd(SCI2C_T *i2c, uint8_t enable); 287 288 /* SCL and SDA */ 289 void SCI2C_ConfigClkPeriod(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint16_t highPeriod, uint16_t lowPeriod); 290 void SCI2C_ConfigSDAHoldTime(SCI2C_T *i2c, uint16_t txHold, uint8_t rxHold); 291 void SCI2C_ConfigSDADelayTime(SCI2C_T *i2c, uint8_t delay); 292 293 /* ACK and NACK */ 294 void SCI2C_GernalCallAck(SCI2C_T *i2c, uint8_t enable); 295 void SCI2C_SlaveDataNackOnly(SCI2C_T *i2c, uint8_t enable); 296 297 /* Abort */ 298 uint32_t SCI2C_ReadTxAbortSource(SCI2C_T *i2c); 299 300 /* DMA */ 301 void SCI2C_EnableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma); 302 void SCI2C_DisableDMA(SCI2C_T *i2c, SCI2C_DMA_T dma); 303 void SCI2C_ConfigDMATxDataLevel(SCI2C_T *i2c, uint8_t cnt); 304 void SCI2C_ConfigDMARxDataLevel(SCI2C_T *i2c, uint8_t cnt); 305 306 /* Spike suppression limit */ 307 void SCI2C_ConfigSpikeSuppressionLimit(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint8_t limit); 308 309 /* Ingerrupt and flag */ 310 uint8_t SCI2C_ReadStatusFlag(SCI2C_T *i2c, SCI2C_FLAG_T flag); 311 void SCI2C_ClearIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag); 312 uint8_t SCI2C_ReadIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag); 313 uint8_t SCI2C_ReadRawIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag); 314 void SCI2C_EnableInterrupt(SCI2C_T *i2c, uint16_t interrupt); 315 void SCI2C_DisableInterrupt(SCI2C_T *i2c, uint16_t interrupt); 316 317 /**@} end of group SCI2C_Functions */ 318 /**@} end of group SCI2C_Driver */ 319 /**@} end of group APM32E10x_StdPeriphDriver */ 320 321 #ifdef __cplusplus 322 } 323 #endif 324 325 #endif /* __APM32E10X_SCI2C_H */ 326