1 /*!
2  * @file        apm32e10x_sdio.h
3  *
4  * @brief       This file contains all the functions prototypes for the SDIO firmware library
5  *
6  * @version     V1.0.2
7  *
8  * @date        2022-12-31
9  *
10  * @attention
11  *
12  *  Copyright (C) 2021-2023 Geehy Semiconductor
13  *
14  *  You may not use this file except in compliance with the
15  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
16  *
17  *  The program is only for reference, which is distributed in the hope
18  *  that it will be useful and instructional for customers to develop
19  *  their software. Unless required by applicable law or agreed to in
20  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
21  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
22  *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
23  *  and limitations under the License.
24  */
25 
26 /* Define to prevent recursive inclusion */
27 #ifndef __APM32E10X_SDIO_H
28 #define __APM32E10X_SDIO_H
29 
30 /* Includes */
31 #include "apm32e10x.h"
32 
33 #ifdef __cplusplus
34  extern "C" {
35 #endif
36 
37 /** @addtogroup APM32E10x_StdPeriphDriver
38   @{
39 */
40 
41 /** @addtogroup SDIO_Driver
42   @{
43 */
44 
45 /** @defgroup SDIO_Macros Macros
46   @{
47 */
48 
49 /* ------------ SDIO registers bit address in the alias region ----------- */
50 #define SDIO_OFFSET                (SDIO_BASE - PERIPH_BASE)
51 
52 /* --- CLKCTRL Register ---*/
53 
54 /* Alias word address of CLKEN bit */
55 #define CLKCTRL_OFFSET            (SDIO_OFFSET + 0x04)
56 #define CLKEN_BitNumber            0x08
57 #define CLKCTRL_CLKEN_BB          (PERIPH_BB_BASE + (CLKCTRL_OFFSET * 32) + (CLKEN_BitNumber * 4))
58 
59 /* --- CMD Register --- */
60 
61 /* Alias word address of SDIOSC bit */
62 #define CMD_OFFSET                (SDIO_OFFSET + 0x0C)
63 #define SDIOSC_BitNumber           0x0B
64 #define CMD_SDIOSC_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSC_BitNumber * 4))
65 
66 /* Alias word address of CMDCPEN bit */
67 #define CMDCPEN_BitNumber          0x0C
68 #define CMD_CMDCPEN_BB            (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (CMDCPEN_BitNumber * 4))
69 
70 /* Alias word address of INTEN bit */
71 #define INTEN_BitNumber            0x0D
72 #define CMD_INTEN_BB              (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (INTEN_BitNumber * 4))
73 
74 /* Alias word address of ATACMD bit */
75 #define ATACMD_BitNumber           0x0E
76 #define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
77 
78 /* --- DCTRL Register --- */
79 
80 /* Alias word address of DMAEN bit */
81 #define DCTRL_OFFSET              (SDIO_OFFSET + 0x2C)
82 #define DMAEN_BitNumber            0x03
83 #define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
84 
85 /* Alias word address of RWSTR bit */
86 #define RWSTR_BitNumber            0x08
87 #define DCTRL_RWSTR_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTR_BitNumber * 4))
88 
89 /* Alias word address of RWSTOP bit */
90 #define RWSTOP_BitNumber           0x09
91 #define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
92 
93 /* Alias word address of RDWAIT bit */
94 #define RDWAIT_BitNumber           0x0A
95 #define DCTRL_RDWAIT_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RDWAIT_BitNumber * 4))
96 
97 /* Alias word address of SDIOF bit */
98 #define SDIOF_BitNumber            0x0B
99 #define DCTRL_SDIOF_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOF_BitNumber * 4))
100 
101 /**@} end of group SDIO_Macros */
102 
103 /** @defgroup SDIO_Enumerations Enumerations
104   @{
105 */
106 
107 /**
108  * @brief    SDIO clock edge
109  */
110 typedef enum
111 {
112     SDIO_CLOCK_EDGE_RISING        = 0x00000000,
113     SDIO_CLOCK_EDGE_FALLING       = 0x00002000
114 }SDIO_CLOCK_EDGE_T;
115 
116 /**
117  * @brief    SDIO clock bypass
118  */
119 typedef enum
120 {
121     SDIO_CLOCK_BYPASS_DISABLE     = 0x00000000,
122     SDIO_CLOCK_BYPASS_ENABLE      = 0x00000400
123 }SDIO_CLOCK_BYPASS_T;
124 
125 /**
126  * @brief    SDIO clock power save
127  */
128 typedef enum
129 {
130     SDIO_CLOCK_POWER_SAVE_DISABLE = 0x00000000,
131     SDIO_CLOCK_POWER_SAVE_ENABLE  = 0x00000200
132 }SDIO_CLOCK_POWER_SAVE_T;
133 
134 /**
135  * @brief    SDIO bus wide
136  */
137 typedef enum
138 {
139     SDIO_BUSWIDE_1B = 0x00000000,
140     SDIO_BUSWIDE_4B = 0x00000800,
141     SDIO_BUSWIDE_8B = 0x00001000
142 }SDIO_BUSWIDE_T;
143 
144 /**
145  * @brief    SDIO hardware flow control
146  */
147 typedef enum
148 {
149     SDIO_HARDWARE_FLOW_CONTROL_DISABLE = 0x00000000,
150     SDIO_HARDWARE_FLOW_CONTROL_ENABLE  = 0x00004000
151 }SDIO_HARDWARE_FLOW_CONTROL_T;
152 
153 /**
154  * @brief    SDIO power state
155  */
156 typedef enum
157 {
158     SDIO_POWER_STATE_OFF = 0x00000000,
159     SDIO_POWER_STATE_ON  = 0x00000003
160 }SDIO_POWER_STATE_T;
161 
162 /**
163  * @brief    SDIO interrupt sources
164  */
165 typedef enum
166 {
167     SDIO_INT_COMRESP    = 0x00000001,
168     SDIO_INT_DBDR       = 0x00000002,
169     SDIO_INT_CMDRESTO   = 0x00000004,
170     SDIO_INT_DATATO     = 0x00000008,
171     SDIO_INT_TXUDRER    = 0x00000010,
172     SDIO_INT_RXOVRER    = 0x00000020,
173     SDIO_INT_CMDRES     = 0x00000040,
174     SDIO_INT_CMDSENT    = 0x00000080,
175     SDIO_INT_DATAEND    = 0x00000100,
176     SDIO_INT_SBE        = 0x00000200,
177     SDIO_INT_DBCP       = 0x00000400,
178     SDIO_INT_CMDACT     = 0x00000800,
179     SDIO_INT_TXACT      = 0x00001000,
180     SDIO_INT_RXACT      = 0x00002000,
181     SDIO_INT_TXFHF      = 0x00004000,
182     SDIO_INT_RXFHF      = 0x00008000,
183     SDIO_INT_TXFF       = 0x00010000,
184     SDIO_INT_RXFF       = 0x00020000,
185     SDIO_INT_TXFE       = 0x00040000,
186     SDIO_INT_RXFE       = 0x00080000,
187     SDIO_INT_TXDA       = 0x00100000,
188     SDIO_INT_RXDA       = 0x00200000,
189     SDIO_INT_SDIOINT    = 0x00400000,
190     SDIO_INT_ATAEND     = 0x00800000
191 }SDIO_INT_T;
192 
193 /**
194  * @brief    SDIO response
195  */
196 typedef enum
197 {
198     SDIO_RESPONSE_NO    = 0x00000000,
199     SDIO_RESPONSE_SHORT = 0x00000040,
200     SDIO_RESPONSE_LONG  = 0x000000C0
201 }SDIO_RESPONSE_T;
202 
203 /**
204  * @brief    SDIO wait interrupt state
205  */
206 typedef enum
207 {
208     SDIO_WAIT_NO        = 0x00000000,
209     SDIO_WAIT_INT       = 0x00000100,
210     SDIO_WAIT_PEND      = 0x00000200
211 }SDIO_WAIT_T;
212 
213 /**
214  * @brief    SDIO CPSM state
215  */
216 typedef enum
217 {
218     SDIO_CPSM_DISABLE   = 0x00000000,
219     SDIO_CPSM_ENABLE    = 0x00000400
220 }SDIO_CPSM_T;
221 
222 /**
223  * @brief    SDIO response registers
224  */
225 typedef enum
226 {
227     SDIO_RES1 = 0x00000000,
228     SDIO_RES2 = 0x00000004,
229     SDIO_RES3 = 0x00000008,
230     SDIO_RES4 = 0x0000000C
231 }SDIO_RES_T;
232 
233 /**
234  * @brief    SDIO data block size
235  */
236 typedef enum
237 {
238     SDIO_DATA_BLOCKSIZE_1B     = 0x00000000,
239     SDIO_DATA_BLOCKSIZE_2B     = 0x00000010,
240     SDIO_DATA_BLOCKSIZE_4B     = 0x00000020,
241     SDIO_DATA_BLOCKSIZE_8B     = 0x00000030,
242     SDIO_DATA_BLOCKSIZE_16B    = 0x00000040,
243     SDIO_DATA_BLOCKSIZE_32B    = 0x00000050,
244     SDIO_DATA_BLOCKSIZE_64B    = 0x00000060,
245     SDIO_DATA_BLOCKSIZE_128B   = 0x00000070,
246     SDIO_DATA_BLOCKSIZE_256B   = 0x00000080,
247     SDIO_DATA_BLOCKSIZE_512B   = 0x00000090,
248     SDIO_DATA_BLOCKSIZE_1024B  = 0x000000A0,
249     SDIO_DATA_BLOCKSIZE_2048B  = 0x000000B0,
250     SDIO_DATA_BLOCKSIZE_496B   = 0x000000C0,
251     SDIO_DATA_BLOCKSIZE_8192B  = 0x000000D0,
252     SDIO_DATA_BLOCKSIZE_16384B = 0x000000E0
253 }SDIO_DATA_BLOCKSIZE_T;
254 
255 /**
256  * @brief    SDIO transfer direction
257  */
258 typedef enum
259 {
260     SDIO_TRANSFER_DIR_TOCARD   = 0x00000000,
261     SDIO_TRANSFER_DIR_TOSDIO   = 0x00000002
262 }SDIO_TRANSFER_DIR_T;
263 
264 /**
265  * @brief    SDIO transfer type
266  */
267 typedef enum
268 {
269     SDIO_TRANSFER_MODE_BLOCK   = 0x00000000,
270     SDIO_TRANSFER_MODE_STREAM  = 0x00000004
271 }SDIO_TRANSFER_MODE_T;
272 
273 /**
274  * @brief    SDIO DPSM state
275  */
276 typedef enum
277 {
278     SDIO_DPSM_DISABLE          = 0x00000000,
279     SDIO_DPSM_ENABLE           = 0x00000001
280 }SDIO_DPSM_T;
281 
282 /**
283  * @brief    SDIO flag
284  */
285 typedef enum
286 {
287     SDIO_FLAG_COMRESP   = 0x00000001,
288     SDIO_FLAG_DBDR      = 0x00000002,
289     SDIO_FLAG_CMDRESTO  = 0x00000004,
290     SDIO_FLAG_DATATO    = 0x00000008,
291     SDIO_FLAG_TXUDRER   = 0x00000010,
292     SDIO_FLAG_RXOVRER   = 0x00000020,
293     SDIO_FLAG_CMDRES    = 0x00000040,
294     SDIO_FLAG_CMDSENT   = 0x00000080,
295     SDIO_FLAG_DATAEND   = 0x00000100,
296     SDIO_FLAG_SBE       = 0x00000200,
297     SDIO_FLAG_DBCP      = 0x00000400,
298     SDIO_FLAG_CMDACT    = 0x00000800,
299     SDIO_FLAG_TXACT     = 0x00001000,
300     SDIO_FLAG_RXACT     = 0x00002000,
301     SDIO_FLAG_TXFHF     = 0x00004000,
302     SDIO_FLAG_RXFHF     = 0x00008000,
303     SDIO_FLAG_TXFF      = 0x00010000,
304     SDIO_FLAG_RXFF      = 0x00020000,
305     SDIO_FLAG_TXFE      = 0x00040000,
306     SDIO_FLAG_RXFE      = 0x00080000,
307     SDIO_FLAG_TXDA      = 0x00100000,
308     SDIO_FLAG_RXDA      = 0x00200000,
309     SDIO_FLAG_SDIOINT   = 0x00400000,
310     SDIO_FLAG_ATAEND    = 0x00800000
311 }SDIO_FLAG_T;
312 
313 /**
314  * @brief    SDIO read wait mode
315  */
316 typedef enum
317 {
318     SDIO_READ_WAIT_MODE_CLK   = 0x00000001,
319     SDIO_READ_WAIT_MODE_DATA2 = 0x00000000
320 }SDIO_READ_WAIT_MODE_T;
321 
322 /**@} end of group SDIO_Enumerations */
323 
324 
325 /** @defgroup SDIO_Structures Structures
326   @{
327 */
328 
329 /**
330  * @brief    SDIO Config structure definition
331  */
332 typedef struct
333 {
334     SDIO_CLOCK_EDGE_T            clockEdge;
335     SDIO_CLOCK_BYPASS_T          clockBypass;
336     SDIO_CLOCK_POWER_SAVE_T      clockPowerSave;
337     SDIO_BUSWIDE_T               busWide;
338     SDIO_HARDWARE_FLOW_CONTROL_T hardwareFlowControl;
339     uint8_t                      clockDiv;
340 }SDIO_Config_T;
341 
342 /**
343  * @brief    SDIO CMD Config structure definition
344  */
345 typedef struct
346 {
347     uint32_t                     argument;
348     uint32_t                     cmdIndex;
349     SDIO_RESPONSE_T              response;
350     SDIO_WAIT_T                  wait;
351     SDIO_CPSM_T                  CPSM;
352 }SDIO_CMDConfig_T;
353 
354 /**
355  * @brief    SDIO Data Config structure definition
356  */
357 typedef struct
358 {
359     uint32_t                     dataTimeOut;
360     uint32_t                     dataLength;
361     SDIO_DATA_BLOCKSIZE_T        dataBlockSize;
362     SDIO_TRANSFER_DIR_T          transferDir;
363     SDIO_TRANSFER_MODE_T         transferMode;
364     SDIO_DPSM_T                  DPSM;
365 }SDIO_DataConfig_T;
366 
367 /**@} end of group SDIO_Structures */
368 
369 
370 /** @defgroup SDIO_Functions Functions
371   @{
372 */
373 
374 /* SDIO reset and configuration */
375 void SDIO_Reset(void);
376 void SDIO_Config(SDIO_Config_T* sdioConfig);
377 void SDIO_ConfigStructInit(SDIO_Config_T* sdioConfig);
378 void SDIO_EnableClock(void);
379 void SDIO_DisableClock(void);
380 void SDIO_ConfigPowerState(SDIO_POWER_STATE_T powerState);
381 uint32_t SDIO_ReadPowerState(void);
382 
383 /* DMA */
384 void SDIO_EnableDMA(void);
385 void SDIO_DisableDMA(void);
386 
387 /* Command */
388 void SDIO_TxCommand(SDIO_CMDConfig_T *cmdConfig);
389 void SDIO_TxCommandStructInit(SDIO_CMDConfig_T* cmdconfig);
390 uint8_t SDIO_ReadCommandResponse(void);
391 uint32_t SDIO_ReadResponse(SDIO_RES_T res);
392 
393 /* SDIO data configuration */
394 void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig);
395 void SDIO_ConfigDataStructInit(SDIO_DataConfig_T* dataConfig);
396 uint32_t SDIO_ReadDataCounter(void);
397 void SDIO_WriteData(uint32_t data);
398 uint32_t SDIO_ReadData(void);
399 uint32_t SDIO_ReadFIFOCount(void);
400 
401 /* SDIO mode */
402 void SDIO_EnableStartReadWait(void);
403 void SDIO_DisableStartReadWait(void);
404 void SDIO_EnableStopReadWait(void);
405 void SDIO_DisableStopReadWait(void);
406 void SDIO_ConfigSDIOReadWaitMode(SDIO_READ_WAIT_MODE_T readWaitMode);
407 void SDIO_EnableSDIO(void);
408 void SDIO_DisableSDIO(void);
409 void SDIO_EnableTxSDIOSuspend(void);
410 void SDIO_DisableTxSDIOSuspend(void);
411 void SDIO_EnableCommandCompletion(void);
412 void SDIO_DisableCommandCompletion(void);
413 void SDIO_EnableCEATAInterrupt(void);
414 void SDIO_DisableCEATAInterrupt(void);
415 void SDIO_EnableTxCEATA(void);
416 void SDIO_DisableTxCEATA(void);
417 
418 /* Interrupt and flags */
419 void SDIO_EnableInterrupt(uint32_t interrupt);
420 void SDIO_DisableInterrupt(uint32_t interrupt);
421 uint8_t SDIO_ReadStatusFlag(SDIO_FLAG_T flag);
422 void SDIO_ClearStatusFlag(uint32_t flag);
423 uint8_t SDIO_ReadIntFlag(SDIO_INT_T flag);
424 void SDIO_ClearIntFlag(uint32_t flag);
425 
426 /**@} end of group SDIO_Functions*/
427 /**@} end of group SDIO_Driver*/
428 /**@} end of group APM32E10x_StdPeriphDriver*/
429 
430 #ifdef __cplusplus
431 }
432 #endif
433 
434 #endif /* __APM32E10X_SDIO_H */
435