1 /*! 2 * @file apm32f0xx_crs.h 3 * 4 * @brief This file contains all the functions prototypes for the CRS firmware library 5 * 6 * @note It's only for APM32F072 and APM32F091 devices 7 * 8 * @version V1.0.3 9 * 10 * @date 2022-09-20 11 * 12 * @attention 13 * 14 * Copyright (C) 2020-2022 Geehy Semiconductor 15 * 16 * You may not use this file except in compliance with the 17 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). 18 * 19 * The program is only for reference, which is distributed in the hope 20 * that it will be useful and instructional for customers to develop 21 * their software. Unless required by applicable law or agreed to in 22 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT 23 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. 24 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions 25 * and limitations under the License. 26 */ 27 28 /* Define to prevent recursive inclusion */ 29 #ifndef __APM32F0XX_CRS_H 30 #define __APM32F0XX_CRS_H 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* Includes */ 37 #include "apm32f0xx.h" 38 39 /** @addtogroup APM32F0xx_StdPeriphDriver 40 @{ 41 */ 42 43 /** @addtogroup CRS_Driver 44 @{ 45 */ 46 47 /** @defgroup CRS_Macros Macros 48 @{ 49 */ 50 51 /**@} end of group CRS_Macros */ 52 53 /** @defgroup CRS_Enumerations Enumerations 54 @{ 55 */ 56 57 /** 58 * @brief CRS_Interrupt_Sources 59 */ 60 typedef enum 61 { 62 CRS_INT_SYNCOK = ((uint32_t)0x00000001), /*!<SYNC event OK interrupt */ 63 CRS_INT_SYNCWARN = ((uint32_t)0x00000002), /*!<SYNC warning interrupt */ 64 CRS_INT_ERR = ((uint32_t)0x00000004), /*!<Synchronization or trimming error interrupt */ 65 CRS_INT_ESYNC = ((uint32_t)0x00000008), /*!<Expected SYNC interrupt */ 66 CRS_INT_SYNCERR = ((uint32_t)0x00000100), /*!<SYNC error */ 67 CRS_INT_SYNCMISS = ((uint32_t)0x00000200), /*!<SYNC missed */ 68 CRS_INT_TRIMOVF = ((uint32_t)0x00000400), /*!<Trimming overflow or underflow */ 69 } CRS_INT_T; 70 71 /** 72 * @brief CRS_Flags 73 */ 74 typedef enum 75 { 76 CRS_FLAG_SYNCOK = ((uint32_t)0x00000001), /*!<SYNC event OK flag */ 77 CRS_FLAG_SYNCWARN = ((uint32_t)0x00000002), /*!<SYNC warning flag */ 78 CRS_FLAG_ERR = ((uint32_t)0x00000004), /*!<Synchronization or trimming error flag */ 79 CRS_FLAG_ESYNC = ((uint32_t)0x00000008), /*!<Expected SYNC flag */ 80 CRS_FLAG_SYNCERR = ((uint32_t)0x00000100), /*!<SYNC error flag */ 81 CRS_FLAG_SYNCMISS = ((uint32_t)0x00000200), /*!<SYNC missed flag */ 82 CRS_FLAG_TRIMOVF = ((uint32_t)0x00000400), /*!<Trimming overflow or underflow falg */ 83 } CRS_FLAG_T; 84 85 /** 86 * @brief CRS_Synchro_Source 87 */ 88 typedef enum 89 { 90 CRS_SYNC_SOURCE_GPIO = 0x00, /*!<GPIO selected as SYNC signal source */ 91 CRS_SYNC_SOURCE_LSE = 0x01, /*!<LSE selected as SYNC signal source */ 92 CRS_SYNC_SOURCE_USB = 0x02, /*!<USB SNFLG selected as SYNC signal source (default) */ 93 } CRS_SYNC_SOURCE_T; 94 95 /** 96 * @brief CRS_Synchro_Source 97 */ 98 typedef enum 99 { 100 CRS_SYNC_DIV1 = 0x00, /*!<Synchro Signal not divided (default) */ 101 CRS_SYNC_DIV2 = 0x01, /*!<Synchro Signal divided by 2 */ 102 CRS_SYNC_DIV4 = 0x02, /*!<Synchro Signal divided by 4 */ 103 CRS_SYNC_DIV8 = 0x03, /*!<Synchro Signal divided by 8 */ 104 CRS_SYNC_DIV16 = 0x04, /*!<Synchro Signal divided by 16 */ 105 CRS_SYNC_DIV32 = 0x05, /*!<Synchro Signal divided by 32 */ 106 CRS_SYNC_DIV64 = 0x06, /*!<Synchro Signal divided by 64 */ 107 CRS_SYNC_DIV128 = 0x07, /*!<Synchro Signal divided by 128 */ 108 } CRS_SYNC_DIV_T; 109 110 /**@} end of group CRS_Enumerations */ 111 112 /** @defgroup CRS_Structures Structures 113 @{ 114 */ 115 116 /** 117 * @brief CRS_SynchroPolarity 118 */ 119 typedef enum 120 { 121 CRS_SYNC_POL_RISING, /*!<Synchro active on rising edge */ 122 CRS_SYNC_POL_FALLING /*!<Synchro active on falling edge */ 123 } CRS_SYNC_POL_T; 124 125 /**@} end of group CRS_Structures */ 126 127 /** @defgroup CRS_Variables Variables 128 @{ 129 */ 130 131 /**@} end of group CRS_Variables */ 132 133 /** @defgroup CRS_Functions Functions 134 @{ 135 */ 136 137 /* Configuration of the CRS */ 138 void CRS_Reset(void); 139 void CRS_AdjustHSI48CalibrationValue(uint8_t calibrationVal); 140 void CRS_EnableFrequencyErrorCounter(void); 141 void CRS_DisableFrequencyErrorCounter(void); 142 void CRS_EnableAutomaticCalibration(void); 143 void CRS_DisableAutomaticCalibration(void); 144 void CRS_GenerateSoftwareSynchronization(void); 145 void CRS_FrequencyErrorCounterReloadValue(uint16_t reloadVal); 146 void CRS_ConfigFrequencyErrorLimit(uint8_t errLimitVal); 147 void CRS_ConfigSynchronizationPrescaler(CRS_SYNC_DIV_T div); 148 void CRS_ConfigSynchronizationSource(CRS_SYNC_SOURCE_T source); 149 void CRS_ConfigSynchronizationPolarity(CRS_SYNC_POL_T polarity); 150 uint32_t CRS_ReadReloadValue(void); 151 uint32_t CRS_ReadHSI48CalibrationValue(void); 152 uint32_t CRS_ReadFrequencyErrorValue(void); 153 uint32_t CRS_ReadFrequencyErrorDirection(void); 154 155 /* Interrupts and flags management functions */ 156 void CRS_EnableInterrupt(CRS_INT_T interrupt); 157 void CRS_DisableInterrupt(CRS_INT_T interrupt); 158 uint8_t CRS_ReadStatusFlag(CRS_FLAG_T flag); 159 void CRS_ClearStatusFlag(CRS_FLAG_T flag); 160 uint8_t CRS_ReadIntFlag(CRS_INT_T flag); 161 void CRS_ClearIntFlag(CRS_INT_T intFlag); 162 163 #ifdef __cplusplus 164 } 165 #endif 166 167 #endif /* __APM32F0XX_CRS_H */ 168 169 /**@} end of group CRS_Functions */ 170 /**@} end of group CRS_Driver */ 171 /**@} end of group APM32F0xx_StdPeriphDriver */ 172