1 /*! 2 * @file apm32f0xx_tmr.h 3 * 4 * @brief This file contains all functions prototype and macros for the TMR peripheral 5 * 6 * @version V1.0.3 7 * 8 * @date 2022-09-20 9 * 10 * @attention 11 * 12 * Copyright (C) 2020-2022 Geehy Semiconductor 13 * 14 * You may not use this file except in compliance with the 15 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). 16 * 17 * The program is only for reference, which is distributed in the hope 18 * that it will be useful and instructional for customers to develop 19 * their software. Unless required by applicable law or agreed to in 20 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT 21 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions 23 * and limitations under the License. 24 */ 25 26 #ifndef __APM32F0XX_TMR_H 27 #define __APM32F0XX_TMR_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include "apm32f0xx.h" 34 35 /** @addtogroup APM32F0xx_StdPeriphDriver 36 @{ 37 */ 38 39 /** @addtogroup TMR_Driver TMR Driver 40 @{ 41 */ 42 43 /** @defgroup TMR_Marcos Marcos 44 @{ 45 */ 46 47 /**@} end of group TMR_Marcos */ 48 49 /** @defgroup TMR_Enumerations Enumerations 50 @{ 51 */ 52 53 /** 54 * @brief Counter_Mode 55 */ 56 typedef enum 57 { 58 TMR_COUNTER_MODE_UP = 0, /*!< Timer Up Counting Mode */ 59 TMR_COUNTER_MODE_DOWN = 1, /*!< Timer Down Counting Mode */ 60 TMR_COUNTER_MODE_CENTERALIGNED1 = 2, /*!< Timer Center Aligned Mode1 */ 61 TMR_COUNTER_MODE_CENTERALIGNED2 = 4, /*!< Timer Center Aligned Mode2 */ 62 TMR_COUNTER_MODE_CENTERALIGNED3 = 6 /*!< Timer Center Aligned Mode3 */ 63 } TMR_COUNTER_MODE_T; 64 65 /** 66 * @brief Clock_Division_CKD 67 */ 68 typedef enum 69 { 70 TMR_CKD_DIV1 = 0, /*!< TDTS = Tck_tim */ 71 TMR_CKD_DIV2 = 1, /*!< TDTS = 2 * Tck_tim */ 72 TMR_CKD_DIV4 = 2 /*!< TDTS = 4 * Tck_tim */ 73 } TMR_CKD_T; 74 75 /** 76 * @brief Prescaler_Reload_Mode 77 */ 78 typedef enum 79 { 80 TMR_PRESCALER_RELOAD_UPDATA = 0, /*!< The Prescaler reload at the update event */ 81 TMR_PRESCALER_RELOAD_IMMEDIATE = 1 /*!< The Prescaler reload immediately */ 82 } TMR_PRESCALER_RELOAD_T; 83 84 /** 85 * @brief TMR UpdateSource 86 */ 87 typedef enum 88 { 89 TMR_UPDATE_SOURCE_GLOBAL = 0, /*!< Source of update is Counter overflow/underflow. 90 - UEG bit of Control event generation register(CEG) is set. 91 - Update generation through the slave mode controller. */ 92 TMR_UPDATE_SOURCE_REGULAR = 1 /*!< Source of update is Counter overflow/underflow */ 93 } TMR_UPDATE_SOURCE_T; 94 95 /** 96 * @brief TMR OPMode 97 */ 98 typedef enum 99 { 100 TMR_OPMODE_REPETITIVE = 0, /*!< Enable repetitive pulse mode */ 101 TMR_OPMODE_SINGLE = 1 /*!< Enable single pulse mode */ 102 } TMR_OPMODE_T; 103 104 /** 105 * @brief TMR Specifies the Off-State selection used in Run mode 106 */ 107 typedef enum 108 { 109 TMR_RMOS_STATE_DISABLE = 0, /*!< Disable run mode off-state */ 110 TMR_RMOS_STATE_ENABLE = 1 /*!< Enable run mode off-state */ 111 } TMR_RMOS_STATE_T; 112 113 /** 114 * @brief TMR Closed state configuration in idle mode 115 */ 116 typedef enum 117 { 118 TMR_IMOS_STATE_DISABLE = 0, /*!< Disable idle mode off-state */ 119 TMR_IMOS_STATE_ENABLE = 1 /*!< Enable idle mode off-state */ 120 } TMR_IMOS_STATE_T; 121 122 /** 123 * @brief TMR Protect mode configuration values 124 */ 125 typedef enum 126 { 127 TMR_LOCK_LEVEL_OFF = 0, /*!< No lock write protection */ 128 TMR_LOCK_LEVEL_1 = 1, /*!< Lock write protection level 1 */ 129 TMR_LOCK_LEVEL_2 = 2, /*!< Lock write protection level 2 */ 130 TMR_LOCK_LEVEL_3 = 3 /*!< Lock write protection level 3 */ 131 } TMR_LOCK_LEVEL_T; 132 133 /** 134 * @brief TMR break state 135 */ 136 typedef enum 137 { 138 TMR_BREAK_STATE_DISABLE, /*!< Disable brake function */ 139 TMR_BREAK_STATE_ENABLE /*!< Enable brake function */ 140 } TMR_BREAK_STATE_T; 141 142 /** 143 * @brief TMR Specifies the Break Input pin polarity. 144 */ 145 typedef enum 146 { 147 TMR_BREAK_POLARITY_LOW, /*!< BREAK low level valid */ 148 TMR_BREAK_POLARITY_HIGH /*!< BREAK high level valid */ 149 } TMR_BREAK_POLARITY_T; 150 151 /** 152 * @brief TMR Automatic Output feature is enable or disable 153 */ 154 typedef enum 155 { 156 TMR_AUTOMATIC_OUTPUT_DISABLE, /*!< Disable automatic output */ 157 TMR_AUTOMATIC_OUTPUT_ENABLE /*!< Enable automatic output */ 158 } TMR_AUTOMATIC_OUTPUT_T; 159 160 /** 161 * @brief TMR_Output_Compare_and_PWM_modes 162 */ 163 typedef enum 164 { 165 TMR_OC_MODE_TMRING = 0x00, /*!< Frozen TMR output compare mode */ 166 TMR_OC_MODE_ACTIVE = 0x01, /*!< Set output to high when matching */ 167 TMR_OC_MODE_INACTIVE = 0x02, /*!< Set output to low when matching */ 168 TMR_OC_MODE_TOGGEL = 0x03, /*!< Toggle output when matching */ 169 TMR_OC_MODE_LOWLEVEL = 0x04, /*!< Force output to be low */ 170 TMR_OC_MODE_HIGHLEVEL = 0x05, /*!< Force output to be high */ 171 TMR_OC_MODE_PWM1 = 0x06, /*!< PWM1 mode */ 172 TMR_OC_MODE_PWM2 = 0x07 /*!< PWM2 mode */ 173 } TMR_OC_MODE_T; 174 175 /** 176 * @brief TMR_Output_Compare_state 177 */ 178 typedef enum 179 { 180 TMR_OUTPUT_STATE_DISABLE, /*!< Disable output compare */ 181 TMR_OUTPUT_STATE_ENABLE /*!< Enable output compare */ 182 } TMR_OC_OUTPUT_STATE_T; 183 184 /** 185 * @brief TMR_Output_Compare_N_state 186 */ 187 typedef enum 188 { 189 TMR_OUTPUT_NSTATE_DISABLE, /*!< Disable complementary output */ 190 TMR_OUTPUT_NSTATE_ENABLE /*!< Enable complementary output */ 191 } TMR_OC_OUTPUT_NSTATE_T; 192 193 /** 194 * @brief TMR_Output_Compare_Polarity 195 */ 196 typedef enum 197 { 198 TMR_OC_POLARITY_HIGH, /*!< Output Compare active high */ 199 TMR_OC_POLARITY_LOW /*!< Output Compare active low */ 200 } TMR_OC_POLARITY_T; 201 202 /** 203 * @brief TMR_Output_Compare_N_Polarity 204 */ 205 typedef enum 206 { 207 TMR_OC_NPOLARITY_HIGH, /*!< Output Compare active high */ 208 TMR_OC_NPOLARITY_LOW /*!< Output Compare active low */ 209 } TMR_OC_NPOLARITY_T; 210 211 /** 212 * @brief TMR_Output_Compare_Idle_State 213 */ 214 typedef enum 215 { 216 TMR_OCIDLESTATE_RESET, /*!< Reset output compare idle state */ 217 TMR_OCIDLESTATE_SET /*!< Set output compare idle state */ 218 } TMR_OC_IDLE_STATE_T; 219 220 /** 221 * @brief TMR_Output_Compare_N_Idle_State 222 */ 223 typedef enum 224 { 225 TMR_OCNIDLESTATE_RESET, /*!< Reset output complementary idle state */ 226 TMR_OCNIDLESTATE_SET /*!< Set output complementary idle state */ 227 } TMR_OC_NIDLE_STATE_T; 228 229 /** 230 * @brief TMR Input Capture Init structure definition 231 */ 232 typedef enum 233 { 234 TMR_CHANNEL_1 = 0x0000, /*!< Timer Channel 1 */ 235 TMR_CHANNEL_2 = 0x0004, /*!< Timer Channel 2 */ 236 TMR_CHANNEL_3 = 0x0008, /*!< Timer Channel 3 */ 237 TMR_CHANNEL_4 = 0x000C /*!< Timer Channel 4 */ 238 } TMR_CHANNEL_T; 239 240 /** 241 * @brief TMR ForcedAction 242 */ 243 typedef enum 244 { 245 TMR_FORCEDACTION_INACTIVE = 0x04, /*!< Force inactive level on OC1REF */ 246 TMR_FORCEDACTION_ACTIVE = 0x05 /*!< Force active level on OC1REF */ 247 } TMR_FORCED_ACTION_T; 248 249 /** 250 * @brief TMR Output_Compare_Preload_State 251 */ 252 typedef enum 253 { 254 TMR_OC_PRELOAD_DISABLE, /*!< Disable preload */ 255 TMR_OC_PRELOAD_ENABLE /*!< Enable preload */ 256 } TMR_OC_PRELOAD_T; 257 258 /** 259 * @brief TMR Output_Compare_Fast_State 260 */ 261 typedef enum 262 { 263 TMR_OCFAST_DISABLE, /*!< Disable fast output compare */ 264 TMR_OCFAST_ENABLE /*!< Enable fast output compare */ 265 } TMR_OCFAST_T; 266 267 /** 268 * @brief TMR Output_Compare_Clear_State 269 */ 270 typedef enum 271 { 272 TMR_OCCLER_DISABLE, /*!< Disable output compare clear */ 273 TMR_OCCLER_ENABLE /*!< Enable output compare clear */ 274 } TMR_OCCLER_T; 275 276 /** 277 * @brief TMR_OCReferenceClear Clear source 278 */ 279 typedef enum 280 { 281 TMR_OCCS_ETRF, /*!< Select ETRF as clear source */ 282 TMR_OCCS_OCREFCLR /*!< Select OCREFCLR as clear source */ 283 } TMR_OCCSEL_T; 284 285 /** 286 * @brief TMR Input_Capture_Polarity 287 */ 288 typedef enum 289 { 290 TMR_IC_POLARITY_RISING = 0x00, /*!< Rising edge */ 291 TMR_IC_POLARITY_FALLING = 0x02, /*!< Falling edge */ 292 TMR_IC_POLARITY_BOTHEDGE = 0x0A /*!< Both rising and falling edge */ 293 } TMR_IC_POLARITY_T; 294 295 /** 296 * @brief TMR Input_Capture_Selection 297 */ 298 typedef enum 299 { 300 TMR_IC_SELECTION_DIRECT_TI = 0x01, /*!< Input capture mapping in TI1 */ 301 TMR_IC_SELECTION_INDIRECT_TI = 0x02, /*!< Input capture mapping in TI2 */ 302 TMR_IC_SELECTION_TRC = 0x03 /*!< Input capture mapping in TRC */ 303 } TMR_IC_SELECTION_T; 304 305 /** 306 * @brief TMR_Input_Capture_Prescaler 307 */ 308 typedef enum 309 { 310 TMR_ICPSC_DIV1 = 0x00, /*!< No prescaler */ 311 TMR_ICPSC_DIV2 = 0x01, /*!< Capture is done once every 2 events */ 312 TMR_ICPSC_DIV4 = 0x02, /*!< capture is done once every 4 events */ 313 TMR_ICPSC_DIV8 = 0x03 /*!< capture is done once every 8 events */ 314 } TMR_IC_PRESCALER_T; 315 316 /** 317 * @brief TMR_interrupt_sources 318 */ 319 typedef enum 320 { 321 TMR_INT_UPDATE = 0x0001, /*!< Timer update Interrupt source */ 322 TMR_INT_CH1 = 0x0002, /*!< Timer Capture Compare 1 Interrupt source */ 323 TMR_INT_CH2 = 0x0004, /*!< Timer Capture Compare 2 Interrupt source */ 324 TMR_INT_CH3 = 0x0008, /*!< Timer Capture Compare 3 Interrupt source */ 325 TMR_INT_CH4 = 0x0010, /*!< Timer Capture Compare 4 Interrupt source */ 326 TMR_INT_CCU = 0x0020, /*!< Timer Commutation Interrupt */ 327 TMR_INT_TRG = 0x0040, /*!< Timer Trigger Interrupt source */ 328 TMR_INT_BRK = 0x0080 /*!< Timer Break Interrupt source */ 329 } TMR_INT_T; 330 331 /** 332 * @brief TMR_event_sources 333 */ 334 typedef enum 335 { 336 TMR_EVENT_UPDATE = 0x0001, /*!< Timer update Interrupt source */ 337 TMR_EVENT_CH1 = 0x0002, /*!< Timer Capture Compare 1 Event source */ 338 TMR_EVENT_CH2 = 0x0004, /*!< Timer Capture Compare 2 Event source */ 339 TMR_EVENT_CH3 = 0x0008, /*!< Timer Capture Compare 3 Event source */ 340 TMR_EVENT_CH4 = 0x0010, /*!< Timer Capture Compare 4 Event source */ 341 TMR_EVENT_CCU = 0x0020, /*!< Timer Commutation Event source */ 342 TMR_EVENT_TRG = 0x0040, /*!< Timer Trigger Event source */ 343 TMR_EVENT_BRK = 0x0080 /*!< Timer Break Event source */ 344 } TMR_EVENT_T; 345 346 /** 347 * @brief TMR_interrupt_flag 348 */ 349 typedef enum 350 { 351 TMR_INT_FLAG_UPDATE = 0x0001, /*!< Timer update Interrupt source */ 352 TMR_INT_FLAG_CH1 = 0x0002, /*!< Timer Capture Compare 1 Interrupt source */ 353 TMR_INT_FLAG_CH2 = 0x0004, /*!< Timer Capture Compare 2 Interrupt source */ 354 TMR_INT_FLAG_CH3 = 0x0008, /*!< Timer Capture Compare 3 Interrupt source */ 355 TMR_INT_FLAG_CH4 = 0x0010, /*!< Timer Capture Compare 4 Interrupt source */ 356 TMR_INT_FLAG_CCU = 0x0020, /*!< Timer Commutation Interrupt source */ 357 TMR_INT_FLAG_TRG = 0x0040, /*!< Timer Trigger Interrupt source */ 358 TMR_INT_FLAG_BRK = 0x0080 /*!< Timer Break Interrupt source */ 359 } TMR_INT_FLAG_T; 360 361 /** 362 * @brief TMR Flag 363 */ 364 typedef enum 365 { 366 TMR_FLAG_UPDATE = 0x0001, /*!< Timer update Flag */ 367 TMR_FLAG_CH1 = 0x0002, /*!< Timer Capture Compare 1 Flag */ 368 TMR_FLAG_CH2 = 0x0004, /*!< Timer Capture Compare 2 Flag */ 369 TMR_FLAG_CH3 = 0x0008, /*!< Timer Capture Compare 3 Flag */ 370 TMR_FLAG_CH4 = 0x0010, /*!< Timer Capture Compare 4 Flag */ 371 TMR_FLAG_CCU = 0x0020, /*!< Timer Commutation Flag */ 372 TMR_FLAG_TRG = 0x0040, /*!< Timer Trigger Flag */ 373 TMR_FLAG_BRK = 0x0080, /*!< Timer Break Flag (Only for TMR1 and TMR8) */ 374 TMR_FLAG_CH1OC = 0x0200, /*!< Timer Capture Compare 1 Repetition Flag */ 375 TMR_FLAG_CH2OC = 0x0400, /*!< Timer Capture Compare 2 Repetition Flag */ 376 TMR_FLAG_CH3OC = 0x0800, /*!< Timer Capture Compare 3 Repetition Flag */ 377 TMR_FLAG_CH4OC = 0x1000 /*!< Timer Capture Compare 4 Repetition Flag */ 378 } TMR_FLAG_T; 379 380 /** 381 * @brief TMR DMA Base Address 382 */ 383 typedef enum 384 { 385 TMR_DMABASE_CTRL1 = 0x0000, /*!< TMR CTRL1 DMA base address setup */ 386 TMR_DMABASE_CTRL2 = 0x0001, /*!< TMR CTRL2 DMA base address setup */ 387 TMR_DMABASE_SMCTRL = 0x0002, /*!< TMR SMCTRL DMA base address setup */ 388 TMR_DMABASE_DIEN = 0x0003, /*!< TMR DIEN DMA base address setup */ 389 TMR_DMABASE_STS = 0x0004, /*!< TMR STS DMA base address setup */ 390 TMR_DMABASE_CEG = 0x0005, /*!< TMR CEG DMA base address setup */ 391 TMR_DMABASE_CCM1 = 0x0006, /*!< TMR CCM1 DMA base address setup */ 392 TMR_DMABASE_CCM2 = 0x0007, /*!< TMR CCM2 DMA base address setup */ 393 TMR_DMABASE_CHCTRL = 0x0008, /*!< TMR CHCTRL DMA base address setup */ 394 TMR_DMABASE_CNT = 0x0009, /*!< TMR CNT DMA base address setup */ 395 TMR_DMABASE_DIV = 0x000A, /*!< TMR DIV DMA base address setup */ 396 TMR_DMABASE_AUTORLD = 0x000B, /*!< TMR AUTORLD DMA base address setup */ 397 TMR_DMABASE_REPCNT = 0x000C, /*!< TMR REPCNT DMA base address setup */ 398 TMR_DMABASE_CH1CC = 0x000D, /*!< TMR CH1CC DMA base address setup */ 399 TMR_DMABASE_CH2CC = 0x000E, /*!< TMR CH2CC DMA base address setup */ 400 TMR_DMABASE_CH3CC = 0x000F, /*!< TMR CH3CC DMA base address setup */ 401 TMR_DMABASE_CH4CC = 0x0010, /*!< TMR CH4CC DMA base address setup */ 402 TMR_DMABASE_BDT = 0x0011, /*!< TMR BDT DMA base address setup */ 403 TMR_DMABASE_DMAB = 0x0012 /*!< TMR DMAB DMA base address setup */ 404 } TMR_DMA_BASE_ADDERSS_T; 405 406 /** 407 * @brief TMR DMA Burst Lenght 408 */ 409 typedef enum 410 { 411 TMR_DMA_BURSTLENGHT_1TRANSFER = 0x0000, /*!< Select TMR DMA burst Length 1 */ 412 TMR_DMA_BURSTLENGHT_2TRANSFERS = 0x0100, /*!< Select TMR DMA burst Length 2 */ 413 TMR_DMA_BURSTLENGHT_3TRANSFERS = 0x0200, /*!< Select TMR DMA burst Length 3 */ 414 TMR_DMA_BURSTLENGHT_4TRANSFERS = 0x0300, /*!< Select TMR DMA burst Length 4 */ 415 TMR_DMA_BURSTLENGHT_5TRANSFERS = 0x0400, /*!< Select TMR DMA burst Length 5 */ 416 TMR_DMA_BURSTLENGHT_6TRANSFERS = 0x0500, /*!< Select TMR DMA burst Length 6 */ 417 TMR_DMA_BURSTLENGHT_7TRANSFERS = 0x0600, /*!< Select TMR DMA burst Length 7 */ 418 TMR_DMA_BURSTLENGHT_8TRANSFERS = 0x0700, /*!< Select TMR DMA burst Length 8 */ 419 TMR_DMA_BURSTLENGHT_9TRANSFERS = 0x0800, /*!< Select TMR DMA burst Length 9 */ 420 TMR_DMA_BURSTLENGHT_10TRANSFERS = 0x0900, /*!< Select TMR DMA burst Length 10 */ 421 TMR_DMA_BURSTLENGHT_11TRANSFERS = 0x0A00, /*!< Select TMR DMA burst Length 11 */ 422 TMR_DMA_BURSTLENGHT_12TRANSFERS = 0x0B00, /*!< Select TMR DMA burst Length 12 */ 423 TMR_DMA_BURSTLENGHT_13TRANSFERS = 0x0C00, /*!< Select TMR DMA burst Length 13 */ 424 TMR_DMA_BURSTLENGHT_14TRANSFERS = 0x0D00, /*!< Select TMR DMA burst Length 14 */ 425 TMR_DMA_BURSTLENGHT_15TRANSFERS = 0x0E00, /*!< Select TMR DMA burst Length 15 */ 426 TMR_DMA_BURSTLENGHT_16TRANSFERS = 0x0F00, /*!< Select TMR DMA burst Length 16 */ 427 TMR_DMA_BURSTLENGHT_17TRANSFERS = 0x1000, /*!< Select TMR DMA burst Length 17 */ 428 TMR_DMA_BURSTLENGHT_18TRANSFERS = 0x1100, /*!< Select TMR DMA burst Length 18 */ 429 } TMR_DMA_BURST_LENGHT_T; 430 431 /** 432 * @brief TMR DMA Soueces 433 */ 434 typedef enum 435 { 436 TMR_DMA_UPDATE = 0x0100, /*!< TMR update DMA souces */ 437 TMR_DMA_CH1 = 0x0200, /*!< TMR Capture Compare 1 DMA souces */ 438 TMR_DMA_CH2 = 0x0400, /*!< TMR Capture Compare 2 DMA souces */ 439 TMR_DMA_CH3 = 0x0800, /*!< TMR Capture Compare 3 DMA souces */ 440 TMR_DMA_CH4 = 0x1000, /*!< TMR Capture Compare 4 DMA souces */ 441 TMR_DMA_CCU = 0x2000, /*!< TMR Commutation DMA souces */ 442 TMR_DMA_TRG = 0x4000 /*!< TMR Trigger DMA souces */ 443 } TMR_DMA_SOUCES_T; 444 445 /** 446 * @brief TMR Internal_Trigger_Selection 447 */ 448 typedef enum 449 { 450 TMR_TS_ITR0 = 0x00, /*!< Internal Trigger 0 */ 451 TMR_TS_ITR1 = 0x01, /*!< Internal Trigger 1 */ 452 TMR_TS_ITR2 = 0x02, /*!< Internal Trigger 2 */ 453 TMR_TS_ITR3 = 0x03, /*!< Internal Trigger 3 */ 454 TMR_TS_TI1F_ED = 0x04, /*!< TI1 Edge Detector */ 455 TMR_TS_TI1FP1 = 0x05, /*!< Filtered Timer Input 1 */ 456 TMR_TS_TI2FP2 = 0x06, /*!< Filtered Timer Input 2 */ 457 TMR_TS_ETRF = 0x07 /*!< External Trigger input */ 458 } TMR_INPUT_TRIGGER_SOURCE_T; 459 460 /** 461 * @brief TMR The external Trigger Prescaler. 462 */ 463 typedef enum 464 { 465 TMR_ExtTRGPSC_OFF = 0x00, /*!< ETRP Prescaler OFF */ 466 TMR_EXTTRGPSC_DIV2 = 0x01, /*!< ETRP frequency divided by 2 */ 467 TMR_EXTTRGPSC_DIV4 = 0x02, /*!< ETRP frequency divided by 4 */ 468 TMR_EXTTRGPSC_DIV8 = 0x03 /*!< ETRP frequency divided by 8 */ 469 } TMR_EXTTRG_PRESCALER_T; 470 471 /** 472 * @brief TMR External_Trigger_Polarity 473 */ 474 typedef enum 475 { 476 TMR_EXTTRGPOLARITY_INVERTED = 0x01, /*!< Active low or falling edge active */ 477 TMR_EXTTGRPOLARITY_NONINVERTED = 0x00 /*!< Active high or rising edge active */ 478 } TMR_EXTTRG_POLARITY_T; 479 480 /** 481 * @brief TMR OPMode 482 */ 483 typedef enum 484 { 485 TMR_TRGOSOURCE_RESET, /*!< Select reset signal as TRGO source */ 486 TMR_TRGOSOURCE_ENABLE, /*!< Select enable signal as TRGO source */ 487 TMR_TRGOSOURCE_UPDATE, /*!< Select update signal as TRGO source */ 488 TMR_TRGOSOURCE_OC1, /*!< Select OC1 signal as TRGO source */ 489 TMR_TRGOSOURCE_OC1REF, /*!< Select OC1REF signal as TRGO source */ 490 TMR_TRGOSOURCE_OC2REF, /*!< Select OC2REF signal as TRGO source */ 491 TMR_TRGOSOURCE_OC3REF, /*!< Select OC3REF signal as TRGO source */ 492 TMR_TRGOSOURCE_OC4REF /*!< Select OC4REF signal as TRGO source */ 493 } TMR_TRGOSOURCE_T; 494 495 /** 496 * @brief TMR OPMode 497 */ 498 typedef enum 499 { 500 TMR_SLAVEMODE_RESET = 0x04, /*!< Reset mode */ 501 TMR_SLAVEMODE_GATED = 0x05, /*!< Gated mode */ 502 TMR_SLAVEMODE_TRIGGER = 0x06, /*!< Trigger mode */ 503 TMR_SLAVEMODE_EXTERNALL = 0x07 /*!< External 1 mode */ 504 } TMR_SLAVEMODE_T; 505 506 /** 507 * @brief TMR Encoder_Mode 508 */ 509 typedef enum 510 { 511 TMR_ENCODER_MODE_TI1 = 0x01, /*!< Encoder mode 1 */ 512 TMR_ENCODER_MODE_TI2 = 0x02, /*!< Encoder mode 2 */ 513 TMR_ENCODER_MODE_TI12 = 0x03 /*!< Encoder mode 3 */ 514 } TMR_ENCODER_MODE_T; 515 516 /** 517 * @brief TMR Remap Select 518 */ 519 typedef enum 520 { 521 TMR_REMAP_GPIO = 0x00, /*!< TMR input is connected to GPIO */ 522 TMR_REMAP_RTC_CLK = 0x01, /*!< TMR input is connected to RTC clock */ 523 TMR_REMAP_HSEDiv32 = 0x02, /*!< TMR input is connected to HSE clock/32 */ 524 TMR_REMAP_MCO = 0x03 /*!< TMR input is connected to MCO */ 525 } TMR_REMAP_T; 526 527 /**@} end of group TMR_Enumerations*/ 528 529 /** @defgroup TMR_Structures Stuctures 530 @{ 531 */ 532 533 /** 534 * @brief TMR Time Base Init structure definition 535 * @note This sturcture is used with all TMRx. 536 */ 537 typedef struct 538 { 539 uint16_t div; /*!< This must between 0x0000 and 0xFFFF */ 540 TMR_COUNTER_MODE_T counterMode; /*!< TMR counter mode selection */ 541 uint32_t period; /*!< This must between 0x0000 and 0xFFFF */ 542 TMR_CKD_T clockDivision; /*!< TMR clock division selection */ 543 uint8_t repetitionCounter; /*!< This must between 0x00 and 0xFF, only for TMR1 and TMR8. */ 544 } TMR_TimeBase_T; 545 546 /** 547 * @brief TMR BDT structure definition 548 */ 549 typedef struct 550 { 551 TMR_RMOS_STATE_T RMOS_State; /*!< TMR Specifies the Off-State selection used in Run mode selection */ 552 TMR_IMOS_STATE_T IMOS_State; /*!< TMR Closed state configuration in idle mode selection */ 553 TMR_LOCK_LEVEL_T lockLevel; /*!< TMR Protect mode configuration values selection */ 554 uint8_t deadTime; /*!< Setup dead time */ 555 TMR_BREAK_STATE_T breakState; /*!< Setup TMR BRK state */ 556 TMR_BREAK_POLARITY_T breakPolarity; /*!< Setup TMR BRK polarity */ 557 TMR_AUTOMATIC_OUTPUT_T automaticOutput; /*!< Setup break input pin polarity */ 558 } TMR_BDTInit_T; 559 /** 560 * @brief TMR Config struct definition 561 */ 562 typedef struct 563 { 564 TMR_OC_MODE_T OC_Mode; /*!< Specifies the TMR mode. */ 565 566 TMR_OC_OUTPUT_STATE_T OC_OutputState; /*!< Specifies the TMR Output Compare state. */ 567 568 TMR_OC_OUTPUT_NSTATE_T OC_OutputNState; /*!< Specifies the TMR complementary Output Compare state. @note This parameter is valid only for TMR1 and TMR8. */ 569 570 TMR_OC_POLARITY_T OC_Polarity; /*!< Specifies the output polarity. */ 571 572 TMR_OC_NPOLARITY_T OC_NPolarity; /*!< Specifies the complementary output polarity. @note This parameter is valid only for TMR1 and TMR8. */ 573 574 TMR_OC_IDLE_STATE_T OC_Idlestate; /*!< Specifies the TMR Output Compare pin state during Idle state. @note This parameter is valid only for TMR1 and TMR8. */ 575 576 TMR_OC_NIDLE_STATE_T OC_NIdlestate; /*!< Specifies the TMR Output Compare pin state during Idle state. @note This parameter is valid only for TMR1 and TMR8. */ 577 578 uint16_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. */ 579 580 } TMR_OCConfig_T; 581 582 /** 583 * @brief TMR Input Capture Config struct definition 584 */ 585 typedef struct 586 { 587 TMR_CHANNEL_T channel; /*!< Specifies the TMR channel. */ 588 589 TMR_IC_POLARITY_T ICpolarity; /*!< Specifies the active edge of the input signal. */ 590 591 TMR_IC_SELECTION_T ICselection; /*!< Specifies the input. */ 592 593 TMR_IC_PRESCALER_T ICprescaler; /*!< Specifies the Input Capture Prescaler. */ 594 595 uint16_t ICfilter; /*!< Specifies the input capture filter. */ 596 597 } TMR_ICConfig_T; 598 599 /**@} end of group TMR_Structures*/ 600 601 /** @defgroup TMR_Variables Variables 602 @{ 603 */ 604 605 /**@} end of group TMR_Variables */ 606 607 /** @defgroup TMR_Functions Functions 608 @{ 609 */ 610 /* TimeBase management */ 611 void TMR_Reset(TMR_T* TMRx); 612 void TMR_ConfigTimeBase(TMR_T* TMRx, TMR_TimeBase_T* timeBaseConfig); 613 void TMR_ConfigTimeBaseStruct(TMR_TimeBase_T* timeBaseConfig); 614 void TMR_ConfigDIV(TMR_T* TMRx, uint16_t div, TMR_PRESCALER_RELOAD_T mode); 615 void TMR_ConfigCounterMode(TMR_T* TMRx, TMR_COUNTER_MODE_T mode); 616 void TMR_SetCounter(TMR_T* TMRx, uint32_t counter); 617 void TMR_SetAutoReload(TMR_T* TMRx, uint32_t autoReload); 618 uint32_t TMR_ReadCounter(TMR_T* TMRx); 619 uint32_t TMR_ReadDiv(TMR_T* TMRx); 620 void TMR_EnableNGUpdate(TMR_T* TMRx); 621 void TMR_DisableNGUpdate(TMR_T* TMRx); 622 void TMR_ConfigUPdateRequest(TMR_T* TMRx, TMR_UPDATE_SOURCE_T source); 623 void TMR_EnableAUTOReload(TMR_T* TMRx); 624 void TMR_DisableAUTOReload(TMR_T* TMRx); 625 void TMR_SetClockDivision(TMR_T* TMRx, TMR_CKD_T clockDivision); 626 void TMR_Enable(TMR_T* TMRx); 627 void TMR_Disable(TMR_T* TMRx); 628 void TMR_ConfigBDT(TMR_T* TMRx, TMR_BDTInit_T* structure); 629 void TMR_ConfigBDTStructInit(TMR_BDTInit_T* structure); 630 631 void TMR_EnablePWMOutputs(TMR_T* TMRx); 632 void TMR_DisablePWMOutputs(TMR_T* TMRx); 633 634 void TMR_OC1Config(TMR_T* TMRx, TMR_OCConfig_T* OCcongigStruct); 635 void TMR_OC2Config(TMR_T* TMRx, TMR_OCConfig_T* OCcongigStruct); 636 void TMR_OC3Config(TMR_T* TMRx, TMR_OCConfig_T* OCcongigStruct); 637 void TMR_OC4Config(TMR_T* TMRx, TMR_OCConfig_T* OCcongigStruct); 638 void TMR_OCConfigStructInit(TMR_OCConfig_T* OCcongigStruct); 639 640 void TMR_SelectOCxMode(TMR_T* TMRx, TMR_CHANNEL_T channel, TMR_OC_MODE_T mode); 641 void TMR_SelectSlaveMode(TMR_T* TMRx, TMR_SLAVEMODE_T mode); 642 void TMR_SelectOnePulseMode(TMR_T* TMRx, TMR_OPMODE_T OPMode); 643 644 void TMR_SetCompare1(TMR_T* TMRx, uint32_t compare); 645 void TMR_SetCompare2(TMR_T* TMRx, uint32_t compare); 646 void TMR_SetCompare3(TMR_T* TMRx, uint32_t compare); 647 void TMR_SetCompare4(TMR_T* TMRx, uint32_t compare); 648 649 void TMR_ForcedOC1Config(TMR_T* TMRx, TMR_FORCED_ACTION_T action); 650 void TMR_ForcedOC2Config(TMR_T* TMRx, TMR_FORCED_ACTION_T action); 651 void TMR_ForcedOC3Config(TMR_T* TMRx, TMR_FORCED_ACTION_T action); 652 void TMR_ForcedOC4Config(TMR_T* TMRx, TMR_FORCED_ACTION_T action); 653 654 void TMR_EnableCCPreload(TMR_T* TMRx); 655 void TMR_DisableCCPreload(TMR_T* TMRx); 656 657 void TMR_OC1PreloadConfig(TMR_T* TMRx, TMR_OC_PRELOAD_T OCPreload); 658 void TMR_OC2PreloadConfig(TMR_T* TMRx, TMR_OC_PRELOAD_T OCPreload); 659 void TMR_OC3PreloadConfig(TMR_T* TMRx, TMR_OC_PRELOAD_T OCPreload); 660 void TMR_OC4PreloadConfig(TMR_T* TMRx, TMR_OC_PRELOAD_T OCPreload); 661 662 void TMR_OC1FastConfit(TMR_T* TMRx, TMR_OCFAST_T OCFast); 663 void TMR_OC2FastConfit(TMR_T* TMRx, TMR_OCFAST_T OCFast); 664 void TMR_OC3FastConfit(TMR_T* TMRx, TMR_OCFAST_T OCFast); 665 void TMR_OC4FastConfit(TMR_T* TMRx, TMR_OCFAST_T OCFast); 666 667 void TMR_OC1PolarityConfig(TMR_T* TMRx, TMR_OC_POLARITY_T OCPolarity); 668 void TMR_OC1NPolarityConfig(TMR_T* TMRx, TMR_OC_NPOLARITY_T OCNPolarity); 669 void TMR_OC2PolarityConfig(TMR_T* TMRx, TMR_OC_POLARITY_T OCPolarity); 670 void TMR_OC2NPolarityConfig(TMR_T* TMRx, TMR_OC_NPOLARITY_T OCNPolarity); 671 void TMR_OC3PolarityConfig(TMR_T* TMRx, TMR_OC_POLARITY_T OCPolarity); 672 void TMR_OC3NPolarityConfig(TMR_T* TMRx, TMR_OC_NPOLARITY_T OCNPolarity); 673 void TMR_OC4PolarityConfig(TMR_T* TMRx, TMR_OC_POLARITY_T OCPolarity); 674 675 void TMR_SelectOCREFClear(TMR_T* TMRx, TMR_OCCSEL_T OCReferenceClear); 676 677 void TMR_EnableCCxChannel(TMR_T* TMRx, TMR_CHANNEL_T channel); 678 void TMR_DisableCCxChannel(TMR_T* TMRx, TMR_CHANNEL_T channel); 679 void TMR_EnableCCxNChannel(TMR_T* TMRx, TMR_CHANNEL_T channel); 680 void TMR_DisableCCxNChannel(TMR_T* TMRx, TMR_CHANNEL_T channel); 681 682 void TMR_EnableAUTOReload(TMR_T* TMRx); 683 void TMR_DisableAUTOReload(TMR_T* TMRx); 684 void TMR_EnableSelectCOM(TMR_T* TMRx); 685 void TMR_DisableSelectCOM(TMR_T* TMRx); 686 687 void TMR_ICConfig(TMR_T* TMRx, TMR_ICConfig_T* ICconfigstruct); 688 void TMR_ICConfigStructInit(TMR_ICConfig_T* ICconfigstruct); 689 690 void TMR_PWMConfig(TMR_T* TMRx, TMR_ICConfig_T* ICconfigstruct); 691 692 uint16_t TMR_ReadCaputer1(TMR_T* TMRx); 693 uint16_t TMR_ReadCaputer2(TMR_T* TMRx); 694 uint16_t TMR_ReadCaputer3(TMR_T* TMRx); 695 uint16_t TMR_ReadCaputer4(TMR_T* TMRx); 696 697 void TMR_SetIC1Prescal(TMR_T* TMRx, TMR_IC_PRESCALER_T prescaler); 698 void TMR_SetIC2Prescal(TMR_T* TMRx, TMR_IC_PRESCALER_T prescaler); 699 void TMR_SetIC3Prescal(TMR_T* TMRx, TMR_IC_PRESCALER_T prescaler); 700 void TMR_SetIC4Prescal(TMR_T* TMRx, TMR_IC_PRESCALER_T prescaler); 701 702 /* Interrupts and Event management functions */ 703 void TMR_EnableInterrupt(TMR_T* TMRx, uint16_t interrupt); 704 void TMR_DisableInterrupt(TMR_T* TMRx, uint16_t interrupt); 705 void TMR_GenerateEvent(TMR_T* TMRx, uint16_t event); 706 707 uint16_t TMR_ReadStatusFlag(TMR_T* TMRx, TMR_FLAG_T flag); 708 void TMR_ClearStatusFlag(TMR_T* TMRx, uint16_t flag); 709 uint16_t TMR_ReadIntFlag(TMR_T* TMRx, TMR_INT_FLAG_T flag); 710 void TMR_ClearIntFlag(TMR_T* TMRx, uint16_t flag); 711 712 void TMR_ConfigDMA(TMR_T* TMRx, TMR_DMA_BASE_ADDERSS_T address, TMR_DMA_BURST_LENGHT_T lenght); 713 void TMR_EnableDMASoure(TMR_T* TMRx, uint16_t souces); 714 void TMR_DisableDMASoure(TMR_T* TMRx, uint16_t souces); 715 void TMR_EnableCCDMA(TMR_T* TMRx); 716 void TMR_DisableCCDMA(TMR_T* TMRx); 717 718 /* Clocks management */ 719 void TMR_ConfigInternalClock(TMR_T* TMRx); 720 void TMR_ConfigITRxExternalClock(TMR_T* TMRx, TMR_INPUT_TRIGGER_SOURCE_T input); 721 void TMR_ConfigTIxExternalClock(TMR_T* TMRx, TMR_INPUT_TRIGGER_SOURCE_T input, 722 TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter); 723 void TMR_ConfigExternalClockMode1(TMR_T* TMRx, TMR_EXTTRG_PRESCALER_T prescaler, 724 TMR_EXTTRG_POLARITY_T polarity, uint16_t filter); 725 void TMR_ConfigExternalClockMode2(TMR_T* TMRx, TMR_EXTTRG_PRESCALER_T prescaler, 726 TMR_EXTTRG_POLARITY_T polarity, uint16_t filter); 727 /* Synchronization management */ 728 void TMR_SelectInputTrigger(TMR_T* TMRx, TMR_INPUT_TRIGGER_SOURCE_T input); 729 void TMR_SelectOutputTrigger(TMR_T* TMRx, TMR_TRGOSOURCE_T source); 730 void TMR_EnableMasterSlaveMode(TMR_T* TMRx); 731 void TMR_DisableMasterSlaveMode(TMR_T* TMRx); 732 void TMR_ConfigExternalTrigger(TMR_T* TMRx, TMR_EXTTRG_PRESCALER_T prescaler, 733 TMR_EXTTRG_POLARITY_T polarity, uint16_t filter); 734 735 /* Specific interface management */ 736 void TMR_ConfigEncodeInterface(TMR_T* TMRx, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity, 737 TMR_IC_POLARITY_T IC2Polarity); 738 void TMR_EnableHallSensor(TMR_T* TMRx); 739 void TMR_DisableHallSensor(TMR_T* TMRx); 740 741 /* Specific remapping management */ 742 void TMR_ConfigRemap(TMR_T* TMRx, TMR_REMAP_T remap); 743 744 #ifdef __cplusplus 745 } 746 #endif 747 748 #endif /* __APM32F0XX_TMR_H */ 749 750 /**@} end of group TMR_Functions */ 751 /**@} end of group TMR_Driver */ 752 /**@} end of group APM32F0xx_StdPeriphDriver */ 753