1 /*!
2 * @file apm32f0xx_dma.c
3 *
4 * @brief This file contains all the functions for the DMA peripheral
5 *
6 * @version V1.0.3
7 *
8 * @date 2022-09-20
9 *
10 * @attention
11 *
12 * Copyright (C) 2020-2022 Geehy Semiconductor
13 *
14 * You may not use this file except in compliance with the
15 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
16 *
17 * The program is only for reference, which is distributed in the hope
18 * that it will be useful and instructional for customers to develop
19 * their software. Unless required by applicable law or agreed to in
20 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
21 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
23 * and limitations under the License.
24 */
25
26 /* Includes */
27 #include "apm32f0xx_dma.h"
28
29 /** @addtogroup APM32F0xx_StdPeriphDriver
30 @{
31 */
32
33 /** @addtogroup DMA_Driver
34 @{
35 */
36
37 /** @defgroup DMA_Macros Macros
38 @{
39 */
40
41 /**@} end of group DMA_Macros */
42
43 /** @defgroup DMA_Enumerates Enumerates
44 @{
45 */
46
47 /**@} end of group DMA_Enumerates */
48
49 /** @defgroup DMA_Structures Structures
50 @{
51 */
52
53 /**@} end of group DMA_Structures */
54
55 /** @defgroup DMA_Variables Variables
56 @{
57 */
58
59 /**@} end of group DMA_Variables */
60
61 /** @defgroup DMA_Functions Functions
62 @{
63 */
64
65 /*!
66 * @brief Set the DMA peripheral registers to their default reset values
67 *
68 * @param DMA_CHANNEL_T: Pointer to a DMA_CHANNEL_T structure that
69 * set DMA channel for the DMA peripheral
70 * This parameter can be one of the following values:
71 * @arg DMA1_CHANNEL_1
72 * @arg DMA1_CHANNEL_2
73 * @arg DMA1_CHANNEL_3
74 * @arg DMA1_CHANNEL_4
75 * @arg DMA1_CHANNEL_5
76 * @arg DMA1_CHANNEL_6(only for APM32F072 and APM32F091)
77 * @arg DMA1_CHANNEL_7(only for APM32F072 and APM32F091)
78 * @arg DMA2_CHANNEL_1(only for APM32F091)
79 * @arg DMA2_CHANNEL_2(only for APM32F091)
80 * @arg DMA2_CHANNEL_3(only for APM32F091)
81 * @arg DMA2_CHANNEL_4(only for APM32F091)
82 * @arg DMA2_CHANNEL_5(only for APM32F091)
83 * @retval None
84 */
DMA_Reset(DMA_CHANNEL_T * channel)85 void DMA_Reset(DMA_CHANNEL_T* channel)
86 {
87 channel->CHCFG_B.CHEN = 0;
88 channel->CHCFG = 0;
89 channel->CHNDATA = 0;
90 channel->CHPADDR = 0;
91 channel->CHMADDR = 0;
92
93 if (channel == DMA1_CHANNEL_1)
94 {
95 DMA1->INTFCLR = (uint32_t)0x0000000F;
96 }
97 else if (channel == DMA1_CHANNEL_2)
98 {
99 DMA1->INTFCLR = (uint32_t)0x000000F0;
100 }
101 else if (channel == DMA1_CHANNEL_3)
102 {
103 DMA1->INTFCLR = (uint32_t)0x00000F00;
104 }
105 else if (channel == DMA1_CHANNEL_4)
106 {
107 DMA1->INTFCLR = (uint32_t)0x0000F000;
108 }
109 else if (channel == DMA1_CHANNEL_5)
110 {
111 DMA1->INTFCLR = (uint32_t)0x000F0000;
112 }
113 else if (channel == DMA1_CHANNEL_6)
114 {
115 DMA1->INTFCLR = (uint32_t)0x00F00000;
116 }
117 else if (channel == DMA1_CHANNEL_7)
118 {
119 DMA1->INTFCLR = (uint32_t)0x0F000000;
120 }
121 else if (channel == DMA2_CHANNEL_1)
122 {
123 DMA2->INTFCLR = (uint32_t)0x0000000F;
124 }
125 else if (channel == DMA2_CHANNEL_2)
126 {
127 DMA2->INTFCLR = (uint32_t)0x000000F0;
128 }
129 else if (channel == DMA2_CHANNEL_3)
130 {
131 DMA2->INTFCLR = (uint32_t)0x00000F00;
132 }
133 else if (channel == DMA2_CHANNEL_4)
134 {
135 DMA2->INTFCLR = (uint32_t)0x0000F000;
136 }
137 else if (channel == DMA2_CHANNEL_5)
138 {
139 DMA2->INTFCLR = (uint32_t)0x000F0000;
140 }
141 }
142
143 /*!
144 * @brief Config the DMA peripheral according to the specified parameters in the dmaConfig
145 *
146 * @param DMA_CHANNEL_T: Pointer to a DMA_CHANNEL_T structure that
147 * set DMA channel for the DMA peripheral
148 * This parameter can be one of the following values:
149 * @arg DMA1_CHANNEL_1
150 * @arg DMA1_CHANNEL_2
151 * @arg DMA1_CHANNEL_3
152 * @arg DMA1_CHANNEL_4
153 * @arg DMA1_CHANNEL_5
154 * @arg DMA1_CHANNEL_6(only for APM32F072 and APM32F091)
155 * @arg DMA1_CHANNEL_7(only for APM32F072 and APM32F091)
156 * @arg DMA2_CHANNEL_1(only for APM32F091)
157 * @arg DMA2_CHANNEL_2(only for APM32F091)
158 * @arg DMA2_CHANNEL_3(only for APM32F091)
159 * @arg DMA2_CHANNEL_4(only for APM32F091)
160 * @arg DMA2_CHANNEL_5(only for APM32F091)
161 *
162 * @param dmaConfig: Pointer to a DMA_Config_T structure that
163 * contains the configuration information for the DMA peripheral
164 *
165 * @retval None
166 */
DMA_Config(DMA_CHANNEL_T * channel,DMA_Config_T * dmaConfig)167 void DMA_Config(DMA_CHANNEL_T* channel, DMA_Config_T* dmaConfig)
168 {
169 channel->CHCFG_B.DIRCFG = dmaConfig->direction;
170 channel->CHCFG_B.CIRMODE = dmaConfig->circular;
171 channel->CHCFG_B.M2MMODE = dmaConfig->memoryTomemory;
172 channel->CHCFG_B.CHPL = dmaConfig->priority;
173 channel->CHCFG_B.MIMODE = dmaConfig->memoryInc;
174 channel->CHCFG_B.PERIMODE = dmaConfig->peripheralInc;
175 channel->CHCFG_B.MSIZE = dmaConfig->memoryDataSize;
176 channel->CHCFG_B.PERSIZE = dmaConfig->peripheralDataSize;
177
178 channel->CHNDATA = dmaConfig->bufferSize;
179 channel->CHMADDR = dmaConfig->memoryAddress;
180 channel->CHPADDR = dmaConfig->peripheralAddress;
181
182 }
183
184 /*!
185 * @brief Fills each dmaConfig member with its default value
186 *
187 * @param dmaConfig: Pointer to a DMA_Config_T structure which will be initialized
188 *
189 * @retval None
190 */
DMA_ConfigStructInit(DMA_Config_T * dmaConfig)191 void DMA_ConfigStructInit(DMA_Config_T* dmaConfig)
192 {
193 dmaConfig->direction = DMA_DIR_PERIPHERAL;
194 dmaConfig->circular = DMA_CIRCULAR_DISABLE;
195 dmaConfig->memoryTomemory = DMA_M2M_DISABLE;
196 dmaConfig->priority = DMA_PRIORITY_LEVEL_LOW;
197 dmaConfig->memoryInc = DMA_MEMORY_INC_DISABLE;
198 dmaConfig->peripheralInc = DMA_PERIPHERAL_INC_DISABLE;
199 dmaConfig->memoryDataSize = DMA_MEMORY_DATASIZE_BYTE;
200 dmaConfig->peripheralDataSize = DMA_PERIPHERAL_DATASIZE_BYTE;
201
202 dmaConfig->bufferSize = 0;
203 dmaConfig->memoryAddress = 0;
204 dmaConfig->peripheralAddress = 0;
205 }
206
207 /*!
208 * @brief Enable the DMA peripheral
209 *
210 * @param DMA_CHANNEL_T: Pointer to a DMA_CHANNEL_T structure that
211 * set DMA channel for the DMA peripheral
212 * This parameter can be one of the following values:
213 * @arg DMA1_CHANNEL_1
214 * @arg DMA1_CHANNEL_2
215 * @arg DMA1_CHANNEL_3
216 * @arg DMA1_CHANNEL_4
217 * @arg DMA1_CHANNEL_5
218 * @arg DMA1_CHANNEL_6(only for APM32F072 and APM32F091)
219 * @arg DMA1_CHANNEL_7(only for APM32F072 and APM32F091)
220 * @arg DMA2_CHANNEL_1(only for APM32F091)
221 * @arg DMA2_CHANNEL_2(only for APM32F091)
222 * @arg DMA2_CHANNEL_3(only for APM32F091)
223 * @arg DMA2_CHANNEL_4(only for APM32F091)
224 * @arg DMA2_CHANNEL_5(only for APM32F091)
225 *
226 * @retval None
227 */
DMA_Enable(DMA_CHANNEL_T * channel)228 void DMA_Enable(DMA_CHANNEL_T* channel)
229 {
230 channel->CHCFG_B.CHEN = BIT_SET;
231 }
232
233 /*!
234 * @brief Disable the DMA peripheral
235 *
236 * @param DMA_CHANNEL_T: Pointer to a DMA_CHANNEL_T structure that
237 * set DMA channel for the DMA peripheral
238 * This parameter can be one of the following values:
239 * @arg DMA1_CHANNEL_1
240 * @arg DMA1_CHANNEL_2
241 * @arg DMA1_CHANNEL_3
242 * @arg DMA1_CHANNEL_4
243 * @arg DMA1_CHANNEL_5
244 * @arg DMA1_CHANNEL_6(only for APM32F072 and APM32F091)
245 * @arg DMA1_CHANNEL_7(only for APM32F072 and APM32F091)
246 * @arg DMA2_CHANNEL_1(only for APM32F091)
247 * @arg DMA2_CHANNEL_2(only for APM32F091)
248 * @arg DMA2_CHANNEL_3(only for APM32F091)
249 * @arg DMA2_CHANNEL_4(only for APM32F091)
250 * @arg DMA2_CHANNEL_5(only for APM32F091)
251 *
252 * @retval None
253 */
DMA_Disable(DMA_CHANNEL_T * channel)254 void DMA_Disable(DMA_CHANNEL_T* channel)
255 {
256 channel->CHCFG_B.CHEN = BIT_RESET;
257 }
258
259 /*!
260 * @brief Set the DMA Channelx transfer data of number
261 *
262 * @param DMA_CHANNEL_T: Pointer to a DMA_CHANNEL_T structure that
263 * set DMA channel for the DMA peripheral
264 * This parameter can be one of the following values:
265 * @arg DMA1_CHANNEL_1
266 * @arg DMA1_CHANNEL_2
267 * @arg DMA1_CHANNEL_3
268 * @arg DMA1_CHANNEL_4
269 * @arg DMA1_CHANNEL_5
270 * @arg DMA1_CHANNEL_6(only for APM32F072 and APM32F091)
271 * @arg DMA1_CHANNEL_7(only for APM32F072 and APM32F091)
272 * @arg DMA2_CHANNEL_1(only for APM32F091)
273 * @arg DMA2_CHANNEL_2(only for APM32F091)
274 * @arg DMA2_CHANNEL_3(only for APM32F091)
275 * @arg DMA2_CHANNEL_4(only for APM32F091)
276 * @arg DMA2_CHANNEL_5(only for APM32F091)
277 *
278 * @param dataNumber: The number of data units in the current DMA Channel transfer
279 *
280 * @retval None
281 */
DMA_SetDataNumber(DMA_CHANNEL_T * channel,uint32_t dataNumber)282 void DMA_SetDataNumber(DMA_CHANNEL_T* channel, uint32_t dataNumber)
283 {
284 channel->CHNDATA = (uint32_t)dataNumber;
285 }
286
287 /*!
288 * @brief Read the DMA Channelx transfer data of number
289 *
290 * @param DMA_CHANNEL_T: Pointer to a DMA_CHANNEL_T structure that
291 * set DMA channel for the DMA peripheral
292 * This parameter can be one of the following values:
293 * @arg DMA1_CHANNEL_1
294 * @arg DMA1_CHANNEL_2
295 * @arg DMA1_CHANNEL_3
296 * @arg DMA1_CHANNEL_4
297 * @arg DMA1_CHANNEL_5
298 * @arg DMA1_CHANNEL_6(only for APM32F072 and APM32F091)
299 * @arg DMA1_CHANNEL_7(only for APM32F072 and APM32F091)
300 * @arg DMA2_CHANNEL_1(only for APM32F091)
301 * @arg DMA2_CHANNEL_2(only for APM32F091)
302 * @arg DMA2_CHANNEL_3(only for APM32F091)
303 * @arg DMA2_CHANNEL_4(only for APM32F091)
304 * @arg DMA2_CHANNEL_5(only for APM32F091)
305 *
306 * @retval The number of data units in the current DMA Channel transfer
307 */
DMA_ReadDataNumber(DMA_CHANNEL_T * channel)308 uint32_t DMA_ReadDataNumber(DMA_CHANNEL_T* channel)
309 {
310 return ((uint32_t)channel->CHNDATA);
311 }
312
313 /*!
314 * @brief Configure the DMA channels remapping.
315 *
316 * @param dma: Select the the DMA peripheral.
317 It can be DMA1/DMA2.
318 *
319 * @param remap: Select the the DMA_CHANNEL_REMAP_T.
320 When select DMA1, the DMA channel can be 1 to 7.
321 * When select DMA2, the DMA channel can be 1 to 5.
322 *
323 * @retval It's only for APM32F091 devices.
324 */
DMA_ConfigRemap(DMA_T * dma,DMA_CHANNEL_REMAP_T remap)325 void DMA_ConfigRemap(DMA_T* dma, DMA_CHANNEL_REMAP_T remap)
326 {
327 dma->CHSEL &= ~((uint32_t)0x0F << (uint32_t)(remap >> 28) * 4);
328 dma->CHSEL |= (uint32_t)(remap & 0x0FFFFFFF);
329 }
330
331 /*!
332 * @brief Enables the specified interrupts
333 * @param DMA_CHANNEL_T: Pointer to a DMA_CHANNEL_T structure that
334 * set DMA channel for the DMA peripheral
335 * This parameter can be one of the following values:
336 * @arg DMA1_CHANNEL_1
337 * @arg DMA1_CHANNEL_2
338 * @arg DMA1_CHANNEL_3
339 * @arg DMA1_CHANNEL_4
340 * @arg DMA1_CHANNEL_5
341 * @arg DMA1_CHANNEL_6(only for APM32F072 and APM32F091)
342 * @arg DMA1_CHANNEL_7(only for APM32F072 and APM32F091)
343 * @arg DMA2_CHANNEL_1(only for APM32F091)
344 * @arg DMA2_CHANNEL_2(only for APM32F091)
345 * @arg DMA2_CHANNEL_3(only for APM32F091)
346 * @arg DMA2_CHANNEL_4(only for APM32F091)
347 * @arg DMA2_CHANNEL_5(only for APM32F091)
348 *
349 * @param interrupt: Specifies the DMA interrupts sources
350 * The parameter can be combination of following values:
351 * @arg DMA_INT_TFIE: Transfer complete interrupt
352 * @arg DMA_INT_HTIE: Half Transfer interrupt
353 * @arg DMA_INT_TEIE: Transfer error interrupt
354 *
355 * @retval None
356 */
DMA_EnableInterrupt(DMA_CHANNEL_T * channel,uint32_t interrupt)357 void DMA_EnableInterrupt(DMA_CHANNEL_T* channel, uint32_t interrupt)
358 {
359 channel->CHCFG |= (uint32_t)interrupt;
360 }
361
362 /*!
363 * @brief Disables the specified interrupts
364 * @param DMA_CHANNEL_T: Pointer to a DMA_CHANNEL_T structure that
365 * set DMA channel for the DMA peripheral
366 * This parameter can be one of the following values:
367 * @arg DMA1_CHANNEL_1
368 * @arg DMA1_CHANNEL_2
369 * @arg DMA1_CHANNEL_3
370 * @arg DMA1_CHANNEL_4
371 * @arg DMA1_CHANNEL_5
372 * @arg DMA1_CHANNEL_6(only for APM32F072 and APM32F091)
373 * @arg DMA1_CHANNEL_7(only for APM32F072 and APM32F091)
374 * @arg DMA2_CHANNEL_1(only for APM32F091)
375 * @arg DMA2_CHANNEL_2(only for APM32F091)
376 * @arg DMA2_CHANNEL_3(only for APM32F091)
377 * @arg DMA2_CHANNEL_4(only for APM32F091)
378 * @arg DMA2_CHANNEL_5(only for APM32F091)
379 *
380 * @param interrupt: Specifies the DMA interrupts sources
381 * The parameter can be combination of following values:
382 * @arg DMA_INT_TFIE: Transfer complete interrupt
383 * @arg DMA_INT_HTIE: Half Transfer interrupt
384 * @arg DMA_INT_TEIE: Transfer error interrupt
385 *
386 * @retval None
387 */
DMA_DisableInterrupt(DMA_CHANNEL_T * channel,uint32_t interrupt)388 void DMA_DisableInterrupt(DMA_CHANNEL_T* channel, uint32_t interrupt)
389 {
390 channel->CHCFG &= (uint32_t)~interrupt;
391 }
392
393 /*!
394 * @brief Checks whether the specified DMA flag is set or not
395 *
396 * @param flag: Specifies the flag to check
397 * This parameter can be one of the following values:
398 * @arg DMA1_FLAG_AL1: DMA1 Channel 1 All flag
399 * @arg DMA1_FLAG_TF1: DMA1 Channel 1 Transfer Complete flag
400 * @arg DMA1_FLAG_HT1: DMA1 Channel 1 Half Transfer Complete flag
401 * @arg DMA1_FLAG_TE1: DMA1 Channel 1 Transfer Error flag
402 * @arg DMA1_FLAG_AL2: DMA1 Channel 2 All flag
403 * @arg DMA1_FLAG_TF2: DMA1 Channel 2 Transfer Complete flag
404 * @arg DMA1_FLAG_HT2: DMA1 Channel 2 Half Transfer Complete flag
405 * @arg DMA1_FLAG_TE2: DMA1 Channel 2 Transfer Error flag
406 * @arg DMA1_FLAG_AL3: DMA1 Channel 3 All flag
407 * @arg DMA1_FLAG_TF3: DMA1 Channel 3 Transfer Complete flag
408 * @arg DMA1_FLAG_HT3: DMA1 Channel 3 Half Transfer Complete flag
409 * @arg DMA1_FLAG_TE3: DMA1 Channel 3 Transfer Error flag
410 * @arg DMA1_FLAG_AL4: DMA1 Channel 4 All flag
411 * @arg DMA1_FLAG_TF4: DMA1 Channel 4 Transfer Complete flag
412 * @arg DMA1_FLAG_HT4: DMA1 Channel 4 Half Transfer Complete flag
413 * @arg DMA1_FLAG_TE4: DMA1 Channel 4 Transfer Error flag
414 * @arg DMA1_FLAG_AL5: DMA1 Channel 5 All flag
415 * @arg DMA1_FLAG_TF5: DMA1 Channel 5 Transfer Complete flag
416 * @arg DMA1_FLAG_HT5: DMA1 Channel 5 Half Transfer Complete flag
417 * @arg DMA1_FLAG_TE5: DMA1 Channel 5 Transfer Error flag
418 * Below is only for APM32F072 and APM32F091 devices:
419 * @arg DMA1_FLAG_AL6: DMA1 Channel 6 All flag
420 * @arg DMA1_FLAG_TF6: DMA1 Channel 6 Transfer Complete flag
421 * @arg DMA1_FLAG_HT6: DMA1 Channel 6 Half Transfer Complete flag
422 * @arg DMA1_FLAG_TE6: DMA1 Channel 6 Transfer Error flag
423 * @arg DMA1_FLAG_AL7: DMA1 Channel 7 All flag
424 * @arg DMA1_FLAG_TF7: DMA1 Channel 7 Transfer Complete flag
425 * @arg DMA1_FLAG_HT7: DMA1 Channel 7 Half Transfer Complete flag
426 * @arg DMA1_FLAG_TE7: DMA1 Channel 7 Transfer Error flag
427 * Below is only for APM32F091 devices:
428 * @arg DMA2_FLAG_AL1: DMA2 Channel 1 All flag
429 * @arg DMA2_FLAG_TF1: DMA2 Channel 1 Transfer Complete flag
430 * @arg DMA2_FLAG_HT1: DMA2 Channel 1 Half Transfer Complete flag
431 * @arg DMA2_FLAG_TE1: DMA2 Channel 1 Transfer Error flag
432 * @arg DMA2_FLAG_AL2: DMA2 Channel 2 All flag
433 * @arg DMA2_FLAG_TF2: DMA2 Channel 2 Transfer Complete flag
434 * @arg DMA2_FLAG_HT2: DMA2 Channel 2 Half Transfer Complete flag
435 * @arg DMA2_FLAG_TE2: DMA2 Channel 2 Transfer Error flag
436 * @arg DMA2_FLAG_AL3: DMA2 Channel 3 All flag
437 * @arg DMA2_FLAG_TF3: DMA2 Channel 3 Transfer Complete flag
438 * @arg DMA2_FLAG_HT3: DMA2 Channel 3 Half Transfer Complete flag
439 * @arg DMA2_FLAG_TE3: DMA2 Channel 3 Transfer Error flag
440 * @arg DMA2_FLAG_AL4: DMA2 Channel 4 All flag
441 * @arg DMA2_FLAG_TF4: DMA2 Channel 4 Transfer Complete flag
442 * @arg DMA2_FLAG_HT4: DMA2 Channel 4 Half Transfer Complete flag
443 * @arg DMA2_FLAG_TE4: DMA2 Channel 4 Transfer Error flag
444 * @arg DMA2_FLAG_AL5: DMA2 Channel 5 All flag
445 * @arg DMA2_FLAG_TF5: DMA2 Channel 5 Transfer Complete flag
446 * @arg DMA2_FLAG_HT5: DMA2 Channel 5 Half Transfer Complete flag
447 * @arg DMA2_FLAG_TE5: DMA2 Channel 5 Transfer Error flag
448 *
449 * @retval The new state of flag (SET or RESET)
450 */
DMA_ReadStatusFlag(DMA_FLAG_T flag)451 uint8_t DMA_ReadStatusFlag(DMA_FLAG_T flag)
452 {
453 uint32_t status;
454
455 if ((flag & 0x10000000) == SET)
456 {
457 status = DMA2->INTSTS & ((uint32_t)flag & 0x000FFFFF);
458 }
459 else
460 {
461 status = DMA1->INTSTS & ((uint32_t)flag & 0x0FFFFFFF);
462 }
463
464 if (status == flag)
465 {
466 return SET;
467 }
468
469 return RESET;
470 }
471
472 /*!
473 * @brief Clear whether the specified DMA flag is set or not
474 *
475 * @param flag: Specifies the flag to Clear
476 * This parameter can be any combination of the following values:
477 * @arg DMA1_FLAG_AL1: DMA1 Channel 1 All flag
478 * @arg DMA1_FLAG_TF1: DMA1 Channel 1 Transfer Complete flag
479 * @arg DMA1_FLAG_HT1: DMA1 Channel 1 Half Transfer Complete flag
480 * @arg DMA1_FLAG_TE1: DMA1 Channel 1 Transfer Error flag
481 * @arg DMA1_FLAG_AL2: DMA1 Channel 2 All flag
482 * @arg DMA1_FLAG_TF2: DMA1 Channel 2 Transfer Complete flag
483 * @arg DMA1_FLAG_HT2: DMA1 Channel 2 Half Transfer Complete flag
484 * @arg DMA1_FLAG_TE2: DMA1 Channel 2 Transfer Error flag
485 * @arg DMA1_FLAG_AL3: DMA1 Channel 3 All flag
486 * @arg DMA1_FLAG_TF3: DMA1 Channel 3 Transfer Complete flag
487 * @arg DMA1_FLAG_HT3: DMA1 Channel 3 Half Transfer Complete flag
488 * @arg DMA1_FLAG_TE3: DMA1 Channel 3 Transfer Error flag
489 * @arg DMA1_FLAG_AL4: DMA1 Channel 4 All flag
490 * @arg DMA1_FLAG_TF4: DMA1 Channel 4 Transfer Complete flag
491 * @arg DMA1_FLAG_HT4: DMA1 Channel 4 Half Transfer Complete flag
492 * @arg DMA1_FLAG_TE4: DMA1 Channel 4 Transfer Error flag
493 * @arg DMA1_FLAG_AL5: DMA1 Channel 5 All flag
494 * @arg DMA1_FLAG_TF5: DMA1 Channel 5 Transfer Complete flag
495 * @arg DMA1_FLAG_HT5: DMA1 Channel 5 Half Transfer Complete flag
496 * @arg DMA1_FLAG_TE5: DMA1 Channel 5 Transfer Error flag
497 * Below is only for APM32F072 and APM32F091 devices:
498 * @arg DMA1_FLAG_AL6: DMA1 Channel 6 All flag
499 * @arg DMA1_FLAG_TF6: DMA1 Channel 6 Transfer Complete flag
500 * @arg DMA1_FLAG_HT6: DMA1 Channel 6 Half Transfer Complete flag
501 * @arg DMA1_FLAG_TE6: DMA1 Channel 6 Transfer Error flag
502 * @arg DMA1_FLAG_AL7: DMA1 Channel 7 All flag
503 * @arg DMA1_FLAG_TF7: DMA1 Channel 7 Transfer Complete flag
504 * @arg DMA1_FLAG_HT7: DMA1 Channel 7 Half Transfer Complete flag
505 * @arg DMA1_FLAG_TE7: DMA1 Channel 7 Transfer Error flag
506 * Below is only for APM32F091 devices:
507 * @arg DMA2_FLAG_AL1: DMA2 Channel 1 All flag
508 * @arg DMA2_FLAG_TF1: DMA2 Channel 1 Transfer Complete flag
509 * @arg DMA2_FLAG_HT1: DMA2 Channel 1 Half Transfer Complete flag
510 * @arg DMA2_FLAG_TE1: DMA2 Channel 1 Transfer Error flag
511 * @arg DMA2_FLAG_AL2: DMA2 Channel 2 All flag
512 * @arg DMA2_FLAG_TF2: DMA2 Channel 2 Transfer Complete flag
513 * @arg DMA2_FLAG_HT2: DMA2 Channel 2 Half Transfer Complete flag
514 * @arg DMA2_FLAG_TE2: DMA2 Channel 2 Transfer Error flag
515 * @arg DMA2_FLAG_AL3: DMA2 Channel 3 All flag
516 * @arg DMA2_FLAG_TF3: DMA2 Channel 3 Transfer Complete flag
517 * @arg DMA2_FLAG_HT3: DMA2 Channel 3 Half Transfer Complete flag
518 * @arg DMA2_FLAG_TE3: DMA2 Channel 3 Transfer Error flag
519 * @arg DMA2_FLAG_AL4: DMA2 Channel 4 All flag
520 * @arg DMA2_FLAG_TF4: DMA2 Channel 4 Transfer Complete flag
521 * @arg DMA2_FLAG_HT4: DMA2 Channel 4 Half Transfer Complete flag
522 * @arg DMA2_FLAG_TE4: DMA2 Channel 4 Transfer Error flag
523 * @arg DMA2_FLAG_AL5: DMA2 Channel 5 All flag
524 * @arg DMA2_FLAG_TF5: DMA2 Channel 5 Transfer Complete flag
525 * @arg DMA2_FLAG_HT5: DMA2 Channel 5 Half Transfer Complete flag
526 * @arg DMA2_FLAG_TE5: DMA2 Channel 5 Transfer Error flag
527 *
528 * @retval None
529 */
530
DMA_ClearStatusFlag(uint32_t flag)531 void DMA_ClearStatusFlag(uint32_t flag)
532 {
533 if ((flag & 0x10000000) == SET)
534 {
535 DMA2->INTFCLR |= (uint32_t)(flag & 0x000FFFFF);
536 }
537 else
538 {
539 DMA1->INTFCLR |= (uint32_t)(flag & 0x0FFFFFFF);
540 }
541 }
542
543 /*!
544 * @brief Checks whether the specified interrupt has occurred or not
545 *
546 * @param flag: Specifies the DMA interrupt pending bit to check
547 * The parameter can be one following values:
548 * @arg DMA1_INT_FLAG_AL1: DMA1_Channel 1 All interrupt flag
549 * @arg DMA1_INT_FLAG_TF1: DMA1_Channel 1 Transfer Complete interrupt flag
550 * @arg DMA1_INT_FLAG_HT1: DMA1_Channel 1 Half Transfer Complete interrupt flag
551 * @arg DMA1_INT_FLAG_TE1: DMA1_Channel 1 Transfer Error interrupt flag
552 * @arg DMA1_INT_FLAG_AL2: DMA1_Channel 2 All interrupt flag
553 * @arg DMA1_INT_FLAG_TF2: DMA1_Channel 2 Transfer Complete interrupt flag
554 * @arg DMA1_INT_FLAG_HT2: DMA1_Channel 2 Half Transfer Complete interrupt flag
555 * @arg DMA1_INT_FLAG_TE2: DMA1_Channel 2 Transfer Error interrupt flag
556 * @arg DMA1_INT_FLAG_AL3: DMA1_Channel 3 All interrupt flag
557 * @arg DMA1_INT_FLAG_TF3: DMA1_Channel 3 Transfer Complete interrupt flag
558 * @arg DMA1_INT_FLAG_HT3: DMA1_Channel 3 Half Transfer Complete interrupt flag
559 * @arg DMA1_INT_FLAG_TE3: DMA1_Channel 3 Transfer Error interrupt flag
560 * @arg DMA1_INT_FLAG_AL4: DMA1_Channel 4 All interrupt flag
561 * @arg DMA1_INT_FLAG_TF4: DMA1_Channel 4 Transfer Complete interrupt flag
562 * @arg DMA1_INT_FLAG_HT4: DMA1_Channel 4 Half Transfer Complete interrupt flag
563 * @arg DMA1_INT_FLAG_TE4: DMA1_Channel 4 Transfer Error interrupt flag
564 * @arg DMA1_INT_FLAG_AL5: DMA1_Channel 5 All interrupt flag
565 * @arg DMA1_INT_FLAG_TF5: DMA1_Channel 5 Transfer Complete interrupt flag
566 * @arg DMA1_INT_FLAG_HT5: DMA1_Channel 5 Half Transfer Complete interrupt flag
567 * @arg DMA1_INT_FLAG_TE5: DMA1_Channel 5 Transfer Error interrupt flag
568 * Below is only for APM32F072 and APM32F091 devices:
569 * @arg DMA1_INT_FLAG_AL6: DMA1_Channel 6 All interrupt flag
570 * @arg DMA1_INT_FLAG_TF6: DMA1_Channel 6 Transfer Complete interrupt flag
571 * @arg DMA1_INT_FLAG_HT6: DMA1_Channel 6 Half Transfer Complete interrupt flag
572 * @arg DMA1_INT_FLAG_TE6: DMA1_Channel 6 Transfer Error interrupt flag
573 * @arg DMA1_INT_FLAG_AL7: DMA1_Channel 7 All interrupt flag
574 * @arg DMA1_INT_FLAG_TF7: DMA1_Channel 7 Transfer Complete interrupt flag
575 * @arg DMA1_INT_FLAG_HT7: DMA1_Channel 7 Half Transfer Complete interrupt flag
576 * @arg DMA1_INT_FLAG_TE7: DMA1_Channel 7 Transfer Error interrupt flag
577 * Below is only for APM32F091 devices:
578 * @arg DMA2_INT_FLAG_AL1: DMA2_Channel 1 All interrupt flag
579 * @arg DMA2_INT_FLAG_TF1: DMA2_Channel 1 Transfer Complete interrupt flag
580 * @arg DMA2_INT_FLAG_HT1: DMA2_Channel 1 Half Transfer Complete interrupt flag
581 * @arg DMA2_INT_FLAG_TE1: DMA2_Channel 1 Transfer Error interrupt flag
582 * @arg DMA2_INT_FLAG_AL2: DMA2_Channel 2 All interrupt flag
583 * @arg DMA2_INT_FLAG_TF2: DMA2_Channel 2 Transfer Complete interrupt flag
584 * @arg DMA2_INT_FLAG_HT2: DMA2_Channel 2 Half Transfer Complete interrupt flag
585 * @arg DMA2_INT_FLAG_TE2: DMA2_Channel 2 Transfer Error interrupt flag
586 * @arg DMA2_INT_FLAG_AL3: DMA2_Channel 3 All interrupt flag
587 * @arg DMA2_INT_FLAG_TF3: DMA2_Channel 3 Transfer Complete interrupt flag
588 * @arg DMA2_INT_FLAG_HT3: DMA2_Channel 3 Half Transfer Complete interrupt flag
589 * @arg DMA2_INT_FLAG_TE3: DMA2_Channel 3 Transfer Error interrupt flag
590 * @arg DMA2_INT_FLAG_AL4: DMA2_Channel 4 All interrupt flag
591 * @arg DMA2_INT_FLAG_TF4: DMA2_Channel 4 Transfer Complete interrupt flag
592 * @arg DMA2_INT_FLAG_HT4: DMA2_Channel 4 Half Transfer Complete interrupt flag
593 * @arg DMA2_INT_FLAG_TE4: DMA2_Channel 4 Transfer Error interrupt flag
594 * @arg DMA2_INT_FLAG_AL5: DMA2_Channel 5 All interrupt flag
595 * @arg DMA2_INT_FLAG_TF5: DMA2_Channel 5 Transfer Complete interrupt flag
596 * @arg DMA2_INT_FLAG_HT5: DMA2_Channel 5 Half Transfer Complete interrupt flag
597 * @arg DMA2_INT_FLAG_TE5: DMA2_Channel 5 Transfer Error interrupt flag
598 *
599 * @retval The new state of flag (SET or RESET)
600 */
DMA_ReadIntFlag(DMA_INT_FLAG_T flag)601 uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag)
602 {
603 uint32_t status;
604
605 if ((flag & 0x10000000) == SET)
606 {
607 status = DMA2->INTSTS & ((uint32_t)flag & 0x000FFFFF);
608 }
609 else
610 {
611 status = DMA1->INTSTS & ((uint32_t)flag & 0x0FFFFFFF);
612 }
613
614 if (status == flag)
615 {
616 return SET;
617 }
618
619 return RESET;
620 }
621
622 /*!
623 * @brief Clears the specified interrupt pending bits
624 *
625 * @param flag: Specifies the DMA interrupt pending bit to clear
626 * The parameter can be combination of following values:
627 * @arg DMA1_INT_FLAG_AL1: DMA1_Channel 1 All interrupt flag
628 * @arg DMA1_INT_FLAG_TF1: DMA1_Channel 1 Transfer Complete interrupt flag
629 * @arg DMA1_INT_FLAG_HT1: DMA1_Channel 1 Half Transfer Complete interrupt flag
630 * @arg DMA1_INT_FLAG_TE1: DMA1_Channel 1 Transfer Error interrupt flag
631 * @arg DMA1_INT_FLAG_AL2: DMA1_Channel 2 All interrupt flag
632 * @arg DMA1_INT_FLAG_TF2: DMA1_Channel 2 Transfer Complete interrupt flag
633 * @arg DMA1_INT_FLAG_HT2: DMA1_Channel 2 Half Transfer Complete interrupt flag
634 * @arg DMA1_INT_FLAG_TE2: DMA1_Channel 2 Transfer Error interrupt flag
635 * @arg DMA1_INT_FLAG_AL3: DMA1_Channel 3 All interrupt flag
636 * @arg DMA1_INT_FLAG_TF3: DMA1_Channel 3 Transfer Complete interrupt flag
637 * @arg DMA1_INT_FLAG_HT3: DMA1_Channel 3 Half Transfer Complete interrupt flag
638 * @arg DMA1_INT_FLAG_TE3: DMA1_Channel 3 Transfer Error interrupt flag
639 * @arg DMA1_INT_FLAG_AL4: DMA1_Channel 4 All interrupt flag
640 * @arg DMA1_INT_FLAG_TF4: DMA1_Channel 4 Transfer Complete interrupt flag
641 * @arg DMA1_INT_FLAG_HT4: DMA1_Channel 4 Half Transfer Complete interrupt flag
642 * @arg DMA1_INT_FLAG_TE4: DMA1_Channel 4 Transfer Error interrupt flag
643 * @arg DMA1_INT_FLAG_AL5: DMA1_Channel 5 All interrupt flag
644 * @arg DMA1_INT_FLAG_TF5: DMA1_Channel 5 Transfer Complete interrupt flag
645 * @arg DMA1_INT_FLAG_HT5: DMA1_Channel 5 Half Transfer Complete interrupt flag
646 * @arg DMA1_INT_FLAG_TE5: DMA1_Channel 5 Transfer Error interrupt flag
647 * Below is only for APM32F072 and APM32F091 devices:
648 * @arg DMA1_INT_FLAG_AL6: DMA1_Channel 6 All interrupt flag
649 * @arg DMA1_INT_FLAG_TF6: DMA1_Channel 6 Transfer Complete interrupt flag
650 * @arg DMA1_INT_FLAG_HT6: DMA1_Channel 6 Half Transfer Complete interrupt flag
651 * @arg DMA1_INT_FLAG_TE6: DMA1_Channel 6 Transfer Error interrupt flag
652 * @arg DMA1_INT_FLAG_AL7: DMA1_Channel 7 All interrupt flag
653 * @arg DMA1_INT_FLAG_TF7: DMA1_Channel 7 Transfer Complete interrupt flag
654 * @arg DMA1_INT_FLAG_HT7: DMA1_Channel 7 Half Transfer Complete interrupt flag
655 * @arg DMA1_INT_FLAG_TE7: DMA1_Channel 7 Transfer Error interrupt flag
656 * Below is only for APM32F091 devices:
657 * @arg DMA2_INT_FLAG_AL1: DMA2_Channel 1 All interrupt flag
658 * @arg DMA2_INT_FLAG_TF1: DMA2_Channel 1 Transfer Complete interrupt flag
659 * @arg DMA2_INT_FLAG_HT1: DMA2_Channel 1 Half Transfer Complete interrupt flag
660 * @arg DMA2_INT_FLAG_TE1: DMA2_Channel 1 Transfer Error interrupt flag
661 * @arg DMA2_INT_FLAG_AL2: DMA2_Channel 2 All interrupt flag
662 * @arg DMA2_INT_FLAG_TF2: DMA2_Channel 2 Transfer Complete interrupt flag
663 * @arg DMA2_INT_FLAG_HT2: DMA2_Channel 2 Half Transfer Complete interrupt flag
664 * @arg DMA2_INT_FLAG_TE2: DMA2_Channel 2 Transfer Error interrupt flag
665 * @arg DMA2_INT_FLAG_AL3: DMA2_Channel 3 All interrupt flag
666 * @arg DMA2_INT_FLAG_TF3: DMA2_Channel 3 Transfer Complete interrupt flag
667 * @arg DMA2_INT_FLAG_HT3: DMA2_Channel 3 Half Transfer Complete interrupt flag
668 * @arg DMA2_INT_FLAG_TE3: DMA2_Channel 3 Transfer Error interrupt flag
669 * @arg DMA2_INT_FLAG_AL4: DMA2_Channel 4 All interrupt flag
670 * @arg DMA2_INT_FLAG_TF4: DMA2_Channel 4 Transfer Complete interrupt flag
671 * @arg DMA2_INT_FLAG_HT4: DMA2_Channel 4 Half Transfer Complete interrupt flag
672 * @arg DMA2_INT_FLAG_TE4: DMA2_Channel 4 Transfer Error interrupt flag
673 * @arg DMA2_INT_FLAG_AL5: DMA2_Channel 5 All interrupt flag
674 * @arg DMA2_INT_FLAG_TF5: DMA2_Channel 5 Transfer Complete interrupt flag
675 * @arg DMA2_INT_FLAG_HT5: DMA2_Channel 5 Half Transfer Complete interrupt flag
676 * @arg DMA2_INT_FLAG_TE5: DMA2_Channel 5 Transfer Error interrupt flag
677 *
678 * @retval None
679 */
DMA_ClearIntFlag(uint32_t flag)680 void DMA_ClearIntFlag(uint32_t flag)
681 {
682 if ((flag & 0x10000000) == SET)
683 {
684 DMA2->INTFCLR |= (uint32_t)(flag & 0x000FFFFF);
685 }
686 else
687 {
688 DMA1->INTFCLR |= (uint32_t)(flag & 0x0FFFFFFF);
689 }
690 }
691
692 /**@} end of group DMA_Functions */
693 /**@} end of group DMA_Driver */
694 /**@} end of group APM32F0xx_StdPeriphDriver */
695
696