1;/*! 2; * @file startup_apm32f072.s 3; * 4; * @brief CMSIS Cortex-M0 PLUS based Core Device Startup File for Device startup_apm32f072 5; * 6; * @version V1.0.2 7; * 8; * @date 2022-02-21 9; * 10; * @attention 11; * 12; * Copyright (C) 2020-2022 Geehy Semiconductor 13; * 14; * You may not use this file except in compliance with the 15; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). 16; * 17; * The program is only for reference, which is distributed in the hope 18; * that it will be useful and instructional for customers to develop 19; * their software. Unless required by applicable law or agreed to in 20; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT 21; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. 22; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions 23; * and limitations under the License. 24; */ 25 26; <h> Stack Configuration 27; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 28; </h> 29 30Stack_Size EQU 0x00000400 31 32 AREA STACK, NOINIT, READWRITE, ALIGN=3 33Stack_Mem SPACE Stack_Size 34__initial_sp 35 36 37; <h> Heap Configuration 38; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 39; </h> 40 41Heap_Size EQU 0x00000200 42 43 AREA HEAP, NOINIT, READWRITE, ALIGN=3 44__heap_base 45Heap_Mem SPACE Heap_Size 46__heap_limit 47 48 PRESERVE8 49 THUMB 50 51 52; Vector Table Mapped to Address 0 at Reset 53 AREA RESET, DATA, READONLY 54 EXPORT __Vectors 55 EXPORT __Vectors_End 56 EXPORT __Vectors_Size 57 58__Vectors DCD __initial_sp ; Top of Stack 59 DCD Reset_Handler ; Reset Handler 60 DCD NMI_Handler ; NMI Handler 61 DCD HardFault_Handler ; Hard Fault Handler 62 DCD 0 ; Reserved 63 DCD 0 ; Reserved 64 DCD 0 ; Reserved 65 DCD 0 ; Reserved 66 DCD 0 ; Reserved 67 DCD 0 ; Reserved 68 DCD 0 ; Reserved 69 DCD SVC_Handler ; SVCall Handler 70 DCD 0 ; Reserved 71 DCD 0 ; Reserved 72 DCD PendSV_Handler ; PendSV Handler 73 DCD SysTick_Handler ; SysTick Handler 74 75 ; External Interrupts 76 DCD WWDT_IRQHandler ; Window Watchdog 77 DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EINT Line detect 78 DCD RTC_IRQHandler ; RTC through EINT Line 79 DCD FLASH_IRQHandler ; FLASH 80 DCD RCM_CRS_IRQHandler ; RCM and CRS 81 DCD EINT0_1_IRQHandler ; EINT Line 0 and 1 82 DCD EINT2_3_IRQHandler ; EINT Line 2 and 3 83 DCD EINT4_15_IRQHandler ; EINT Line 4 to 15 84 DCD TSC_IRQHandler ; TSC 85 DCD DMA1_CH1_IRQHandler ; DMA1 Channel 1 86 DCD DMA1_CH2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 87 DCD DMA1_CH4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 88 DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 89 DCD TMR1_BRK_UP_TRG_COM_IRQHandler ; TMR1 Break, Update, Trigger and Commutation 90 DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare 91 DCD TMR2_IRQHandler ; TMR2 92 DCD TMR3_IRQHandler ; TMR3 93 DCD TMR6_DAC_IRQHandler ; TMR6 and DAC 94 DCD TMR7_IRQHandler ; TMR7 95 DCD TMR14_IRQHandler ; TMR14 96 DCD TMR15_IRQHandler ; TMR15 97 DCD TMR16_IRQHandler ; TMR16 98 DCD TMR17_IRQHandler ; TMR17 99 DCD I2C1_IRQHandler ; I2C1 100 DCD I2C2_IRQHandler ; I2C2 101 DCD SPI1_IRQHandler ; SPI1 102 DCD SPI2_IRQHandler ; SPI2 103 DCD USART1_IRQHandler ; USART1 104 DCD USART2_IRQHandler ; USART2 105 DCD USART3_4_IRQHandler ; USART3 and USART4 106 DCD CEC_CAN_IRQHandler ; CEC and CAN 107 DCD USBD_IRQHandler ; USB 108 109__Vectors_End 110 111__Vectors_Size EQU __Vectors_End - __Vectors 112 113 AREA |.text|, CODE, READONLY 114 115; Reset handler routine 116Reset_Handler PROC 117 EXPORT Reset_Handler [WEAK] 118 IMPORT __main 119 IMPORT SystemInit 120 LDR R0, =SystemInit 121 BLX R0 122 LDR R0, =__main 123 BX R0 124 ENDP 125 126; Dummy Exception Handlers (infinite loops which can be modified) 127 128NMI_Handler PROC 129 EXPORT NMI_Handler [WEAK] 130 B . 131 ENDP 132HardFault_Handler\ 133 PROC 134 EXPORT HardFault_Handler [WEAK] 135 B . 136 ENDP 137SVC_Handler PROC 138 EXPORT SVC_Handler [WEAK] 139 B . 140 ENDP 141PendSV_Handler PROC 142 EXPORT PendSV_Handler [WEAK] 143 B . 144 ENDP 145SysTick_Handler PROC 146 EXPORT SysTick_Handler [WEAK] 147 B . 148 ENDP 149 150Default_Handler PROC 151 152 EXPORT WWDT_IRQHandler [WEAK] 153 EXPORT PVD_VDDIO2_IRQHandler [WEAK] 154 EXPORT RTC_IRQHandler [WEAK] 155 EXPORT FLASH_IRQHandler [WEAK] 156 EXPORT RCM_CRS_IRQHandler [WEAK] 157 EXPORT EINT0_1_IRQHandler [WEAK] 158 EXPORT EINT2_3_IRQHandler [WEAK] 159 EXPORT EINT4_15_IRQHandler [WEAK] 160 EXPORT TSC_IRQHandler [WEAK] 161 EXPORT DMA1_CH1_IRQHandler [WEAK] 162 EXPORT DMA1_CH2_3_IRQHandler [WEAK] 163 EXPORT DMA1_CH4_5_6_7_IRQHandler [WEAK] 164 EXPORT ADC1_COMP_IRQHandler [WEAK] 165 EXPORT TMR1_BRK_UP_TRG_COM_IRQHandler [WEAK] 166 EXPORT TMR1_CC_IRQHandler [WEAK] 167 EXPORT TMR2_IRQHandler [WEAK] 168 EXPORT TMR3_IRQHandler [WEAK] 169 EXPORT TMR6_DAC_IRQHandler [WEAK] 170 EXPORT TMR7_IRQHandler [WEAK] 171 EXPORT TMR14_IRQHandler [WEAK] 172 EXPORT TMR15_IRQHandler [WEAK] 173 EXPORT TMR16_IRQHandler [WEAK] 174 EXPORT TMR17_IRQHandler [WEAK] 175 EXPORT I2C1_IRQHandler [WEAK] 176 EXPORT I2C2_IRQHandler [WEAK] 177 EXPORT SPI1_IRQHandler [WEAK] 178 EXPORT SPI2_IRQHandler [WEAK] 179 EXPORT USART1_IRQHandler [WEAK] 180 EXPORT USART2_IRQHandler [WEAK] 181 EXPORT USART3_4_IRQHandler [WEAK] 182 EXPORT CEC_CAN_IRQHandler [WEAK] 183 EXPORT USBD_IRQHandler [WEAK] 184 185 186WWDT_IRQHandler 187PVD_VDDIO2_IRQHandler 188RTC_IRQHandler 189FLASH_IRQHandler 190RCM_CRS_IRQHandler 191EINT0_1_IRQHandler 192EINT2_3_IRQHandler 193EINT4_15_IRQHandler 194TSC_IRQHandler 195DMA1_CH1_IRQHandler 196DMA1_CH2_3_IRQHandler 197DMA1_CH4_5_6_7_IRQHandler 198ADC1_COMP_IRQHandler 199TMR1_BRK_UP_TRG_COM_IRQHandler 200TMR1_CC_IRQHandler 201TMR2_IRQHandler 202TMR3_IRQHandler 203TMR6_DAC_IRQHandler 204TMR7_IRQHandler 205TMR14_IRQHandler 206TMR15_IRQHandler 207TMR16_IRQHandler 208TMR17_IRQHandler 209I2C1_IRQHandler 210I2C2_IRQHandler 211SPI1_IRQHandler 212SPI2_IRQHandler 213USART1_IRQHandler 214USART2_IRQHandler 215USART3_4_IRQHandler 216CEC_CAN_IRQHandler 217USBD_IRQHandler 218 219 B . 220 221 ENDP 222 223 ALIGN 224 225;******************************************************************************* 226; User Stack and Heap initialization 227;******************************************************************************* 228 IF :DEF:__MICROLIB 229 230 EXPORT __initial_sp 231 EXPORT __heap_base 232 EXPORT __heap_limit 233 234 ELSE 235 236 IMPORT __use_two_region_memory 237 EXPORT __user_initial_stackheap 238 239__user_initial_stackheap 240 241 LDR R0, = Heap_Mem 242 LDR R1, =(Stack_Mem + Stack_Size) 243 LDR R2, = (Heap_Mem + Heap_Size) 244 LDR R3, = Stack_Mem 245 BX LR 246 247 ALIGN 248 249 ENDIF 250 251 END 251