1/*! 2 * @file startup_apm32f070.S 3 * 4 * @brief CMSIS Cortex-M0 PLUS based Core Device Startup File for Device startup_apm32f070 5 * 6 * @version V1.0.0 7 * 8 * @date 2022-08-30 9 * 10 * @attention 11 * 12 * Copyright (C) 2022 Geehy Semiconductor 13 * 14 * You may not use this file except in compliance with the 15 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). 16 * 17 * The program is only for reference, which is distributed in the hope 18 * that it will be useful and instructional for customers to develop 19 * their software. Unless required by applicable law or agreed to in 20 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT 21 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions 23 * and limitations under the License. 24 */ 25 26 .syntax unified 27 .cpu cortex-m0plus 28 .fpu softvfp 29 .thumb 30 31.global g_apm32_Vectors 32.global Default_Handler 33 34.word _start_address_init_data 35.word _start_address_data 36.word _end_address_data 37.word _start_address_bss 38.word _end_address_bss 39 40 .section .text.Reset_Handler 41 .weak Reset_Handler 42 .type Reset_Handler, %function 43 44// Reset handler routine 45Reset_Handler: 46// User Stack and Heap initialization 47 ldr r0, =_end_stack 48 mov sp, r0 49 50 ldr r0, =_start_address_data 51 ldr r1, =_end_address_data 52 ldr r2, =_start_address_init_data 53 movs r3, #0 54 b L_loop0_0 55 56L_loop0: 57 ldr r4, [r2, r3] 58 str r4, [r0, r3] 59 adds r3, r3, #4 60 61L_loop0_0: 62 adds r4, r0, r3 63 cmp r4, r1 64 bcc L_loop0 65 66 ldr r2, =_start_address_bss 67 ldr r4, =_end_address_bss 68 movs r3, #0 69 b L_loop1 70 71L_loop2: 72 str r3, [r2] 73 adds r2, r2, #4 74 75L_loop1: 76 cmp r2, r4 77 bcc L_loop2 78 79 bl SystemInit 80 bl __libc_init_array 81 bl entry 82 83L_loop3: 84 b L_loop3 85 86.size Reset_Handler, .-Reset_Handler 87 88// This is the code that gets called when the processor receives an unexpected interrupt. 89 .section .text.Default_Handler,"ax",%progbits 90Default_Handler: 91L_Loop_infinite: 92 b L_Loop_infinite 93 .size Default_Handler, .-Default_Handler 94 95// The minimal vector table for a Cortex M0 Plus. 96 .section .isr_vector,"a",%progbits 97 .type g_apm32_Vectors, %object 98 .size g_apm32_Vectors, .-g_apm32_Vectors 99 100// Vector Table Mapped to Address 0 at Reset 101g_apm32_Vectors: 102 .word _end_stack 103 .word Reset_Handler // Reset Handler 104 .word NMI_Handler // NMI Handler 105 .word HardFault_Handler // Hard Fault Handler 106 .word 0 // Reserved 107 .word 0 // Reserved 108 .word 0 // Reserved 109 .word 0 // Reserved 110 .word 0 // Reserved 111 .word 0 // Reserved 112 .word 0 // Reserved 113 .word SVC_Handler // SVCall Handler 114 .word 0 // Reserved 115 .word 0 // Reserved 116 .word PendSV_Handler // PendSV Handler 117 .word SysTick_Handler // SysTick Handler 118 119 // External Interrupts 120 .word WWDT_IRQHandler // Window Watchdog 121 .word 0 // Reserved 122 .word RTC_IRQHandler // RTC through EINT Line 123 .word FLASH_IRQHandler // FLASH 124 .word RCM_IRQHandler // RCM 125 .word EINT0_1_IRQHandler // EINT Line 0 and 1 126 .word EINT2_3_IRQHandler // EINT Line 2 and 3 127 .word EINT4_15_IRQHandler // EINT Line 4 to 15 128 .word 0 // Reserved 129 .word DMA1_CH1_IRQHandler // DMA1 Channel 1 130 .word DMA1_CH2_3_IRQHandler // DMA1 Channel 2 and Channel 3 131 .word DMA1_CH4_5_IRQHandler // DMA1 Channel 4 and Channel 5 132 .word ADC1_IRQHandler // ADC1 133 .word TMR1_BRK_UP_TRG_COM_IRQHandler // TMR1 Break, Update, Trigger and Commutation 134 .word TMR1_CC_IRQHandler // TMR1 Capture Compare 135 .word 0 // Reserved 136 .word TMR3_IRQHandler // TMR3 137 .word TMR6_IRQHandler // TMR6 138 .word TMR7_IRQHandler // TMR7 139 .word TMR14_IRQHandler // TMR14 140 .word TMR15_IRQHandler // TMR15 141 .word TMR16_IRQHandler // TMR16 142 .word TMR17_IRQHandler // TMR17 143 .word I2C1_IRQHandler // I2C1 144 .word I2C2_IRQHandler // I2C2 145 .word SPI1_IRQHandler // SPI1 146 .word SPI2_IRQHandler // SPI2 147 .word USART1_IRQHandler // USART1 148 .word USART2_IRQHandler // USART2 149 .word USART3_4_IRQHandler // USART3, USART4 150 .word 0 // Reserved 151 word USBD_IRQHandler // USB 152 153// Default exception/interrupt handler 154 155 .weak NMI_Handler 156 .thumb_set NMI_Handler,Default_Handler 157 158 .weak HardFault_Handler 159 .thumb_set HardFault_Handler,Default_Handler 160 161 .weak SVC_Handler 162 .thumb_set SVC_Handler,Default_Handler 163 164 .weak PendSV_Handler 165 .thumb_set PendSV_Handler,Default_Handler 166 167 .weak SysTick_Handler 168 .thumb_set SysTick_Handler,Default_Handler 169 170 .weak WWDT_IRQHandler 171 .thumb_set WWDT_IRQHandler,Default_Handler 172 173 .weak RTC_IRQHandler 174 .thumb_set RTC_IRQHandler,Default_Handler 175 176 .weak FLASH_IRQHandler 177 .thumb_set FLASH_IRQHandler,Default_Handler 178 179 .weak RCM_IRQHandler 180 .thumb_set RCM_IRQHandler,Default_Handler 181 182 .weak EINT0_1_IRQHandler 183 .thumb_set EINT0_1_IRQHandler,Default_Handler 184 185 .weak EINT2_3_IRQHandler 186 .thumb_set EINT2_3_IRQHandler,Default_Handler 187 188 .weak EINT4_15_IRQHandler 189 .thumb_set EINT4_15_IRQHandler,Default_Handler 190 191 .weak DMA1_CH1_IRQHandler 192 .thumb_set DMA1_CH1_IRQHandler,Default_Handler 193 194 .weak DMA1_CH2_3_IRQHandler 195 .thumb_set DMA1_CH2_3_IRQHandler,Default_Handler 196 197 .weak DMA1_CH4_5_IRQHandler 198 .thumb_set DMA1_CH4_5_IRQHandler,Default_Handler 199 200 .weak ADC1_IRQHandler 201 .thumb_set ADC1_IRQHandler,Default_Handler 202 203 .weak TMR1_BRK_UP_TRG_COM_IRQHandler 204 .thumb_set TMR1_BRK_UP_TRG_COM_IRQHandler,Default_Handler 205 206 .weak TMR1_CC_IRQHandler 207 .thumb_set TMR1_CC_IRQHandler,Default_Handler 208 209 .weak TMR3_IRQHandler 210 .thumb_set TMR3_IRQHandler,Default_Handler 211 212 .weak TMR6_IRQHandler 213 .thumb_set TMR6_IRQHandler,Default_Handler 214 215 .weak TMR7_IRQHandler 216 .thumb_set TMR7_IRQHandler,Default_Handler 217 218 .weak TMR14_IRQHandler 219 .thumb_set TMR14_IRQHandler,Default_Handler 220 221 .weak TMR15_IRQHandler 222 .thumb_set TMR15_IRQHandler,Default_Handler 223 224 .weak TMR16_IRQHandler 225 .thumb_set TMR16_IRQHandler,Default_Handler 226 227 .weak TMR17_IRQHandler 228 .thumb_set TMR17_IRQHandler,Default_Handler 229 230 .weak I2C1_IRQHandler 231 .thumb_set I2C1_IRQHandler,Default_Handler 232 233 .weak I2C2_IRQHandler 234 .thumb_set I2C2_IRQHandler,Default_Handler 235 236 .weak SPI1_IRQHandler 237 .thumb_set SPI1_IRQHandler,Default_Handler 238 239 .weak SPI2_IRQHandler 240 .thumb_set SPI2_IRQHandler,Default_Handler 241 242 .weak USART1_IRQHandler 243 .thumb_set USART1_IRQHandler,Default_Handler 244 245 .weak USART2_IRQHandler 246 .thumb_set USART2_IRQHandler,Default_Handler 247 248 .weak USART3_4_IRQHandler 249 .thumb_set USART3_4_IRQHandler,Default_Handler 250 251 .weak USBD_IRQHandler 252 .thumb_set USBD_IRQHandler,Default_Handler 253