1 /*!
2  * @file        apm32f10x_dmc.h
3  *
4  * @brief       This file contains all the prototypes,enumeration and macros for the DMC peripheral
5  *
6  * @version     V1.0.4
7  *
8  * @date        2022-12-01
9  *
10  * @attention
11  *
12  *  Copyright (C) 2020-2022 Geehy Semiconductor
13  *
14  *  You may not use this file except in compliance with the
15  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
16  *
17  *  The program is only for reference, which is distributed in the hope
18  *  that it will be useful and instructional for customers to develop
19  *  their software. Unless required by applicable law or agreed to in
20  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
21  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
22  *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
23  *  and limitations under the License.
24  */
25 
26 #ifndef __APM32F10X_DMC_H
27 #define __APM32F10X_DMC_H
28 
29 /* Includes */
30 #include "apm32f10x.h"
31 
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35 
36 /** @addtogroup APM32F10x_StdPeriphDriver
37   @{
38 */
39 
40 /** @addtogroup DMC_Driver DMC Driver
41   @{
42 */
43 
44 /** @defgroup DMC_Enumerations Enumerations
45   @{
46 */
47 
48 /**
49  * @brief   Bank Address Width
50  */
51 typedef enum
52 {
53     DMC_BANK_WIDTH_1,
54     DMC_BANK_WIDTH_2
55 } DMC_BANK_WIDTH_T;
56 
57 /**
58  * @brief   Row Address Width
59  */
60 typedef enum
61 {
62     DMC_ROW_WIDTH_11 = 0x0A,
63     DMC_ROW_WIDTH_12,
64     DMC_ROW_WIDTH_13,
65     DMC_ROW_WIDTH_14,
66     DMC_ROW_WIDTH_15,
67     DMC_ROW_WIDTH_16
68 } DMC_ROW_WIDTH_T;
69 
70 /**
71  * @brief   Column Address Width
72  */
73 typedef enum
74 {
75     DMC_COL_WIDTH_8 = 0x07,
76     DMC_COL_WIDTH_9,
77     DMC_COL_WIDTH_10,
78     DMC_COL_WIDTH_11,
79     DMC_COL_WIDTH_12,
80     DMC_COL_WIDTH_13,
81     DMC_COL_WIDTH_14,
82     DMC_COL_WIDTH_15
83 } DMC_COL_WIDTH_T;
84 
85 /**
86  * @brief   CAS Latency Select
87  */
88 typedef enum
89 {
90     DMC_CAS_LATENCY_1,
91     DMC_CAS_LATENCY_2,
92     DMC_CAS_LATENCY_3,
93     DMC_CAS_LATENCY_4
94 } DMC_CAS_LATENCY_T;
95 
96 /**
97  * @brief   RAS Minimun Time Select
98  */
99 typedef enum
100 {
101     DMC_RAS_MINIMUM_1,
102     DMC_RAS_MINIMUM_2,
103     DMC_RAS_MINIMUM_3,
104     DMC_RAS_MINIMUM_4,
105     DMC_RAS_MINIMUM_5,
106     DMC_RAS_MINIMUM_6,
107     DMC_RAS_MINIMUM_7,
108     DMC_RAS_MINIMUM_8,
109     DMC_RAS_MINIMUM_9,
110     DMC_RAS_MINIMUM_10,
111     DMC_RAS_MINIMUM_11,
112     DMC_RAS_MINIMUM_12,
113     DMC_RAS_MINIMUM_13,
114     DMC_RAS_MINIMUM_14,
115     DMC_RAS_MINIMUM_15,
116     DMC_RAS_MINIMUM_16
117 } DMC_RAS_MINIMUM_T;
118 
119 /**
120  * @brief   RAS To CAS Delay Time Select
121  */
122 typedef enum
123 {
124     DMC_DELAY_TIME_1,
125     DMC_DELAY_TIME_2,
126     DMC_DELAY_TIME_3,
127     DMC_DELAY_TIME_4,
128     DMC_DELAY_TIME_5,
129     DMC_DELAY_TIME_6,
130     DMC_DELAY_TIME_7,
131     DMC_DELAY_TIME_8
132 } DMC_DELAY_TIME_T;
133 
134 /**
135  * @brief   Precharge Period Select
136  */
137 typedef enum
138 {
139     DMC_PRECHARGE_1,
140     DMC_PRECHARGE_2,
141     DMC_PRECHARGE_3,
142     DMC_PRECHARGE_4,
143     DMC_PRECHARGE_5,
144     DMC_PRECHARGE_6,
145     DMC_PRECHARGE_7,
146     DMC_PRECHARGE_8
147 } DMC_PRECHARGE_T;
148 
149 /**
150  * @brief   Last Data Next Precharge For Write Time Select
151  */
152 typedef enum
153 {
154     DMC_NEXT_PRECHARGE_1,
155     DMC_NEXT_PRECHARGE_2,
156     DMC_NEXT_PRECHARGE_3,
157     DMC_NEXT_PRECHARGE_4
158 } DMC_NEXT_PRECHARGE_T;
159 
160 /**
161  * @brief   Auto-Refresh Period Select
162  */
163 typedef enum
164 {
165     DMC_AUTO_REFRESH_1,
166     DMC_AUTO_REFRESH_2,
167     DMC_AUTO_REFRESH_3,
168     DMC_AUTO_REFRESH_4,
169     DMC_AUTO_REFRESH_5,
170     DMC_AUTO_REFRESH_6,
171     DMC_AUTO_REFRESH_7,
172     DMC_AUTO_REFRESH_8,
173     DMC_AUTO_REFRESH_9,
174     DMC_AUTO_REFRESH_10,
175     DMC_AUTO_REFRESH_11,
176     DMC_AUTO_REFRESH_12,
177     DMC_AUTO_REFRESH_13,
178     DMC_AUTO_REFRESH_14,
179     DMC_AUTO_REFRESH_15,
180     DMC_AUTO_REFRESH_16,
181 } DMC_AUTO_REFRESH_T;
182 
183 /**
184  * @brief   Active-to-active Command Period Select
185  */
186 typedef enum
187 {
188     DMC_ATA_CMD_1,
189     DMC_ATA_CMD_2,
190     DMC_ATA_CMD_3,
191     DMC_ATA_CMD_4,
192     DMC_ATA_CMD_5,
193     DMC_ATA_CMD_6,
194     DMC_ATA_CMD_7,
195     DMC_ATA_CMD_8,
196     DMC_ATA_CMD_9,
197     DMC_ATA_CMD_10,
198     DMC_ATA_CMD_11,
199     DMC_ATA_CMD_12,
200     DMC_ATA_CMD_13,
201     DMC_ATA_CMD_14,
202     DMC_ATA_CMD_15,
203     DMC_ATA_CMD_16,
204 } DMC_ATA_CMD_T;
205 
206 /**
207  * @brief   Clock PHASE
208  */
209 typedef enum
210 {
211     DMC_CLK_PHASE_NORMAL,
212     DMC_CLK_PHASE_REVERSE
213 } DMC_CLK_PHASE_T;
214 
215 /**
216  * @brief   DMC Memory Size
217  */
218 typedef enum
219 {
220     DMC_MEMORY_SIZE_0,
221     DMC_MEMORY_SIZE_64KB,
222     DMC_MEMORY_SIZE_128KB,
223     DMC_MEMORY_SIZE_256KB,
224     DMC_MEMORY_SIZE_512KB,
225     DMC_MEMORY_SIZE_1MB,
226     DMC_MEMORY_SIZE_2MB,
227     DMC_MEMORY_SIZE_4MB,
228     DMC_MEMORY_SIZE_8MB,
229     DMC_MEMORY_SIZE_16MB,
230     DMC_MEMORY_SIZE_32MB,
231     DMC_MEMORY_SIZE_64MB,
232     DMC_MEMORY_SIZE_128MB,
233     DMC_MEMORY_SIZE_256MB,
234 } DMC_MEMORY_SIZE_T;
235 
236 /**
237  * @brief    Open Banks Of Number
238  */
239 typedef enum
240 {
241     DMC_BANK_NUMBER_1,
242     DMC_BANK_NUMBER_2,
243     DMC_BANK_NUMBER_3,
244     DMC_BANK_NUMBER_4,
245     DMC_BANK_NUMBER_5,
246     DMC_BANK_NUMBER_6,
247     DMC_BANK_NUMBER_7,
248     DMC_BANK_NUMBER_8,
249     DMC_BANK_NUMBER_9,
250     DMC_BANK_NUMBER_10,
251     DMC_BANK_NUMBER_11,
252     DMC_BANK_NUMBER_12,
253     DMC_BANK_NUMBER_13,
254     DMC_BANK_NUMBER_14,
255     DMC_BANK_NUMBER_15,
256     DMC_BANK_NUMBER_16,
257 } DMC_BANK_NUMBER_T;
258 
259 /**
260  * @brief   Full refresh type
261  */
262 typedef enum
263 {
264     DMC_REFRESH_ROW_ONE,        /*!< Refresh one row */
265     DMC_REFRESH_ROW_ALL,        /*!< Refresh all row */
266 } DMC_REFRESH_T;
267 
268 /**
269  * @brief   Precharge type
270  */
271 typedef enum
272 {
273     DMC_PRECHARGE_IM,        /*!< Immediate precharge */
274     DMC_PRECHARGE_DELAY,     /*!< Delayed precharge */
275 } DMC_PRECHARE_T;
276 
277 /**
278  * @brief WRAP Burst Type
279  */
280 typedef enum
281 {
282     DMC_WRAPB_4,
283     DMC_WRAPB_8,
284 } DMC_WRPB_T;
285 
286 /**@} end of group DMC_Enumerations*/
287 
288 
289 /** @defgroup DMC_Structures Structures
290   @{
291 */
292 
293 /**
294  * @brief   Timing config definition
295  */
296 typedef struct
297 {
298     uint32_t    latencyCAS  : 2;       /*!< DMC_CAS_LATENCY_T */
299     uint32_t    tRAS        : 4;       /*!< DMC_RAS_MINIMUM_T */
300     uint32_t    tRCD        : 3;       /*!< DMC_DELAY_TIME_T */
301     uint32_t    tRP         : 3;       /*!< DMC_PRECHARGE_T */
302     uint32_t    tWR         : 2;       /*!< DMC_NEXT_PRECHARGE_T */
303     uint32_t    tARP        : 4;       /*!< DMC_AUTO_REFRESH_T */
304     uint32_t    tCMD        : 4;       /*!< DMC_ATA_CMD_T */
305     uint32_t    tXSR        : 9;       /*!< auto-refresh commands, can be 0x000 to 0x1FF */
306     uint16_t    tRFP        : 16;      /*!< Refresh period, can be 0x0000 to 0xFFFF */
307 } DMC_TimingConfig_T;
308 
309 /**
310  * @brief   Config struct definition
311  */
312 typedef struct
313 {
314     DMC_MEMORY_SIZE_T       memorySize;    /*!< Memory size(byte) */
315     DMC_BANK_WIDTH_T        bankWidth;     /*!< Number of bank bits */
316     DMC_ROW_WIDTH_T         rowWidth;      /*!< Number of row address bits */
317     DMC_COL_WIDTH_T         colWidth;      /*!< Number of col address bits */
318     DMC_CLK_PHASE_T         clkPhase;      /*!< Clock phase */
319     DMC_TimingConfig_T      timing;        /*!< Timing */
320 } DMC_Config_T;
321 
322 /**@} end of group DMC_Structures*/
323 
324 
325 /** @defgroup DMC_Functions Functions
326   @{
327 */
328 
329 /* Enable / Disable */
330 void DMC_Enable(void);
331 void DMC_Disable(void);
332 void DMC_EnableInit(void);
333 
334 /* Global config */
335 void DMC_Config(DMC_Config_T* dmcConfig);
336 void DMC_ConfigStructInit(DMC_Config_T* dmcConfig);
337 
338 /* Address */
339 void DMC_ConfigBankWidth(DMC_BANK_WIDTH_T bankWidth);
340 void DMC_ConfigAddrWidth(DMC_ROW_WIDTH_T rowWidth, DMC_COL_WIDTH_T colWidth);
341 
342 /* Timing */
343 void DMC_ConfigTiming(DMC_TimingConfig_T* timingConfig);
344 void DMC_ConfigTimingStructInit(DMC_TimingConfig_T* timingConfig);
345 void DMC_ConfigStableTimePowerup(uint16_t stableTime);
346 void DMC_ConfigAutoRefreshNumDuringInit(DMC_AUTO_REFRESH_T num);
347 void DMC_ConfigRefreshPeriod(uint16_t period);
348 
349 /* Refresh mode */
350 void DMC_EixtSlefRefreshMode(void);
351 void DMC_EnterSlefRefreshMode(void);
352 
353 /* Accelerate Module */
354 void DMC_EnableAccelerateModule(void);
355 void DMC_DisableAccelerateModule(void);
356 
357 /* Config */
358 void DMC_ConfigOpenBank(DMC_BANK_NUMBER_T num);
359 void DMC_EnableUpdateMode(void);
360 void DMC_EnterPowerdownMode(void);
361 void DMC_ConfigFullRefreshBeforeSR(DMC_REFRESH_T refresh);
362 void DMC_ConfigFullRefreshAfterSR(DMC_REFRESH_T refresh);
363 void DMC_ConfigPrechargeType(DMC_PRECHARE_T precharge);
364 void DMC_ConfigMemorySize(DMC_MEMORY_SIZE_T memorySize);
365 void DMC_ConfigClockPhase(DMC_CLK_PHASE_T clkPhase);
366 void DMC_ConfigWRAPB(DMC_WRPB_T burst);
367 
368 /* read flag */
369 uint8_t DMC_ReadSelfRefreshStatus(void);
370 
371 /**@} end of group DMC_Functions*/
372 /**@} end of group DMC_Driver*/
373 /**@} end of group APM32F10x_StdPeriphDriver*/
374 
375 #ifdef __cplusplus
376 }
377 #endif
378 
379 #endif  /* __APM32F10X_DMC_H */
380