1 /*!
2  * @file        apm32f10x_emmc.h
3  *
4  * @brief       This file contains all the functions prototypes for the EMMC firmware library
5  *
6  * @version     V1.0.2
7  *
8  * @date        2022-01-05
9  *
10  * @attention
11  *
12  *  Copyright (C) 2020-2022 Geehy Semiconductor
13  *
14  *  You may not use this file except in compliance with the
15  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
16  *
17  *  The program is only for reference, which is distributed in the hope
18  *  that it will be usefull and instructional for customers to develop
19  *  their software. Unless required by applicable law or agreed to in
20  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
21  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
22  *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
23  *  and limitations under the License.
24  */
25 
26 #ifndef __APM32F10X_EMMC_H
27 #define __APM32F10X_EMMC_H
28 
29 #ifdef __cplusplus
30   extern "C" {
31 #endif
32 
33 #include "apm32f10x.h"
34 
35 /** @addtogroup Peripherals_Library Standard Peripheral Library
36   @{
37 */
38 
39 /** @addtogroup EMMC_Driver EMMC Driver
40   @{
41 */
42 
43 /** @addtogroup EMMC_Enumerations Enumerations
44   @{
45 */
46 
47 /**
48  * @brief EMMC NORSRAM_Bank
49  */
50 typedef enum
51 {
52     EMMC_BANK1_NORSRAM_1 = 0x00000000,
53     EMMC_BANK1_NORSRAM_2 = 0x00000002,
54     EMMC_BANK1_NORSRAM_3 = 0x00000004,
55     EMMC_BANK1_NORSRAM_4 = 0x00000006
56 } EMMC_BANK1_NORSRAM_T;
57 
58 /**
59  * @brief EMMC NAND and PC Card Bank
60  */
61 typedef enum
62 {
63     EMMC_BANK2_NAND   = 0x00000010,
64     EMMC_BANK3_NAND   = 0x00000100,
65     EMMC_BANK4_PCCARD = 0x00001000
66 } EMMC_BANK_NAND_T;
67 
68 /**
69  * @brief EMMC_Data_Address_Bus_Multiplexing
70  */
71 typedef enum
72 {
73     EMMC_DATA_ADDRESS_MUX_DISABLE = 0x00000000,
74     EMMC_DATA_ADDRESS_MUX_ENABLE  = 0x00000002
75 } EMMC_DATA_ADDRESS_MUX_T;
76 
77 /**
78  * @brief EMMC_Memory_Type
79  */
80 typedef enum
81 {
82     EMMC_MEMORY_TYPE_SRAM  = 0x00000000,
83     EMMC_MEMORY_TYPE_PSRAM = 0x00000004,
84     EMMC_MEMORY_TYPE_NOR   = 0x00000008
85 } EMMC_MEMORY_TYPE_T;
86 
87 /**
88  * @brief EMMC_Data_Width
89  */
90 typedef enum
91 {
92     EMMC_MEMORY_DATA_WIDTH_8BIT  = 0x00000000,
93     EMMC_MEMORY_DATA_WIDTH_16BIT = 0x00000010
94 } EMMC_MEMORY_DATA_WIDTH_T;
95 
96 /**
97  * @brief EMMC_Burst_Access_Mode
98  */
99 typedef enum
100 {
101     EMMC_BURST_ACCESS_MODE_DISABLE = 0x00000000,
102     EMMC_BURST_ACCESS_MODE_ENABLE  = 0x00000100
103 } EMMC_BURST_ACCESS_MODE_T;
104 
105 /**
106  * @brief EMMC_AsynchronousWait
107  */
108 typedef enum
109 {
110     EMMC_ASYNCHRONOUS_WAIT_DISABLE = 0x00000000,
111     EMMC_ASYNCHRONOUS_WAIT_ENABLE  = 0x00008000
112 } EMMC_ASYNCHRONOUS_WAIT_T;
113 
114 /**
115  * @brief EMMC_Wait_Signal_Polarity
116  */
117 typedef enum
118 {
119     EMMC_WAIT_SIGNAL_POLARITY_LOW  = 0x00000000,
120     EMMC_WAIT_SIGNAL_POLARITY_HIGH = 0x00000200
121 } EMMC_WAIT_SIGNAL_POLARITY_T;
122 
123 /**
124  * @brief EMMC_Wrap_Mode
125  */
126 typedef enum
127 {
128     EMMC_WRAP_MODE_DISABLE = 0x00000000,
129     EMMC_WRAP_MODE_ENABLE  = 0x00000400
130 } EMMC_WRAP_MODE_T;
131 
132 /**
133  * @brief EMMC_Wait_Timing
134  */
135 typedef enum
136 {
137     EMMC_WAIT_SIGNAL_ACTIVE_BEFORE_WAIT = 0x00000000,
138     EMMC_WAIT_SIGNAL_ACTIVE_DURING_WAIT = 0x00000800
139 } EMMC_WAIT_SIGNAL_ACTIVE_T;
140 
141 /**
142  * @brief EMMC_Write_Operation
143  */
144 typedef enum
145 {
146     EMMC_WRITE_OPERATION_DISABLE = 0x00000000,
147     EMMC_WRITE_OPERATION_ENABLE  = 0x00001000
148 } EMMC_WRITE_OPERATION_T;
149 
150 /**
151  * @brief EMMC_Wait_Signal
152  */
153 typedef enum
154 {
155     EMMC_WAITE_SIGNAL_DISABLE = 0x00000000,
156     EMMC_WAITE_SIGNAL_ENABLE  = 0x00002000
157 } EMMC_WAITE_SIGNAL_T;
158 
159 /**
160  * @brief EMMC_Extended_Mode
161  */
162 typedef enum
163 {
164     EMMC_EXTENDEN_MODE_DISABLE = 0x00000000,
165     EMMC_EXTENDEN_MODE_ENABLE  = 0x00004000
166 } EMMC_EXTENDEN_MODE_T;
167 
168 /**
169  * @brief EMMC_Write_Burst
170  */
171 typedef enum
172 {
173     EMMC_WRITE_BURST_DISABLE = 0x00000000,
174     EMMC_WRITE_BURST_ENABLE  = 0x00080000
175 } EMMC_WRITE_BURST_T;
176 
177 /**
178  * @brief   EMMC_WAIT_FEATURE
179  */
180 typedef enum
181 {
182     EMMC_WAIT_FEATURE_DISABLE = 0x00000000,
183     EMMC_WAIT_FEATURE_ENABLE  = 0x00000002
184 } EMMC_WAIT_FEATURE_T;
185 
186 /**
187  * @brief EMMC_ECC
188  */
189 typedef enum
190 {
191     EMMC_ECC_DISABLE = 0x00000000,
192     EMMC_ECC_ENABLE  = 0x00000040
193 } EMMC_ECC_T;
194 
195 /**
196  * @brief EMMC_ECC_Page_Size
197  */
198 typedef enum
199 {
200     EMMC_ECC_PAGE_SIZE_BYTE_256  = 0x00000000,
201     EMMC_ECC_PAGE_SIZE_BYTE_512  = 0x00020000,
202     EMMC_ECC_PAGE_SIZE_BYTE_1024 = 0x00040000,
203     EMMC_ECC_PAGE_SIZE_BYTE_2048 = 0x00060000,
204     EMMC_ECC_PAGE_SIZE_BYTE_4096 = 0x00080000,
205     EMMC_ECC_PAGE_SIZE_BYTE_8192 = 0x000A0000
206 } EMMC_ECC_PAGE_SIZE_BYTE_T;
207 
208 /**
209  * @brief EMMC_Access_Mode
210  */
211 typedef enum
212 {
213     EMMC_ACCESS_MODE_A = 0x00000000,
214     EMMC_ACCESS_MODE_B = 0x10000000,
215     EMMC_ACCESS_MODE_C = 0x20000000,
216     EMMC_ACCESS_MODE_D = 0x30000000
217 } EMMC_ACCESS_MODE_T;
218 
219 /**
220  * @brief  EMMC_Interrupt_sources
221  */
222 typedef enum
223 {
224     EMMC_INT_EDGE_RISING  = 0x00000008,
225     EMMC_INT_LEVEL_HIGH   = 0x00000010,
226     EMMC_INT_EDGE_FALLING = 0x00000020
227 } EMMC_INT_T;
228 
229 /**
230  * @brief  EMMC_Flags
231  */
232 typedef enum
233 {
234     EMMC_FLAG_EDGE_RISING  = 0x00000001,
235     EMMC_FLAG_LEVEL_HIGH   = 0x00000002,
236     EMMC_FLAG_EDGE_FALLING = 0x00000004,
237     EMMC_FLAG_FIFO_EMPTY   = 0x00000040
238 } EMMC_FLAG_T;
239 
240 /**@} end of group EMMC_Enumerations*/
241 
242 
243 /** @addtogroup EMMC_Structure Data Structure
244   @{
245 */
246 
247 /**
248  * @brief Timing parameters for NOR/SRAM Banks
249  */
250 typedef struct
251 {
252     uint32_t           addressSetupTime;
253     uint32_t           addressHodeTime;
254     uint32_t           dataSetupTime;
255     uint32_t           busTurnaroundTime;
256     uint32_t           clockDivision;
257     uint32_t           dataLatency;
258     EMMC_ACCESS_MODE_T accessMode;
259 } EMMC_NORSRAMTimingConfig_T;
260 
261 /**
262  * @brief EMMC NOR/SRAM Config structure
263  */
264 typedef struct
265 {
266     EMMC_BANK1_NORSRAM_T        bank;
267     EMMC_DATA_ADDRESS_MUX_T     dataAddressMux;
268     EMMC_MEMORY_TYPE_T          memoryType;
269     EMMC_MEMORY_DATA_WIDTH_T    memoryDataWidth;
270     EMMC_BURST_ACCESS_MODE_T    burstAcceesMode;
271     EMMC_ASYNCHRONOUS_WAIT_T    asynchronousWait;
272     EMMC_WAIT_SIGNAL_POLARITY_T waitSignalPolarity;
273     EMMC_WRAP_MODE_T            wrapMode;
274     EMMC_WAIT_SIGNAL_ACTIVE_T   waitSignalActive;
275     EMMC_WRITE_OPERATION_T      writeOperation;
276     EMMC_WAITE_SIGNAL_T         waiteSignal;
277     EMMC_EXTENDEN_MODE_T        extendedMode;
278     EMMC_WRITE_BURST_T          writeBurst;
279     EMMC_NORSRAMTimingConfig_T*   readWriteTimingStruct;
280     EMMC_NORSRAMTimingConfig_T*   writeTimingStruct;
281 } EMMC_NORSRAMConfig_T;
282 
283 /**
284  * @brief Timing parameters for NAND and PCCARD Banks
285  */
286 typedef struct
287 {
288     uint32_t setupTime;
289     uint32_t waitSetupTime;
290     uint32_t holdSetupTime;
291     uint32_t HiZSetupTime;
292 } EMMC_NAND_PCCARDTimingConfig_T;
293 
294 /**
295  * @brief EMMC NAND Config structure
296  */
297 typedef struct
298 {
299     EMMC_BANK_NAND_T          bank;
300     EMMC_WAIT_FEATURE_T       waitFeature;
301     EMMC_MEMORY_DATA_WIDTH_T  memoryDataWidth;
302     EMMC_ECC_T                ECC;
303     EMMC_ECC_PAGE_SIZE_BYTE_T ECCPageSize;
304     uint32_t                  TCLRSetupTime;
305     uint32_t                  TARSetupTime;
306     EMMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct;
307     EMMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct;
308 } EMMC_NANDConfig_T;
309 
310 /**
311  * @brief EMMC PCCARD Config structure
312  */
313 typedef struct
314 {
315     EMMC_WAIT_FEATURE_T waitFeature;
316     uint32_t            TCLRSetupTime;
317     uint32_t            TARSetupTime;
318     EMMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct;
319     EMMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct;
320     EMMC_NAND_PCCARDTimingConfig_T* IOSpaceTimingStruct;
321 } EMMC_PCCARDConfig_T;
322 
323 /**@} end of group EMMC_Structure*/
324 
325 /** @addtogroup EMMC_Fuctions Fuctions
326   @{
327 */
328 
329 /** EMMC reset */
330 void EMMC_ResetNORSRAM(EMMC_BANK1_NORSRAM_T bank);
331 void EMMC_ResetNAND(EMMC_BANK_NAND_T bank);
332 void EMMC_ResetPCCard(void);
333 
334 /** EMMC Configuration */
335 void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig);
336 void EMMC_ConfigNAND(EMMC_NANDConfig_T* emmcNANDConfig);
337 void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T* emmcPCCardConfig);
338 void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig);
339 void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T* emmcNANDConfig);
340 void EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T* emmcPCCardConfig);
341 
342 /** EMMC bank control */
343 void EMMC_EnableNORSRAM(EMMC_BANK1_NORSRAM_T bank);
344 void EMMC_DisableNORSRAM(EMMC_BANK1_NORSRAM_T bank);
345 void EMMC_EnableNAND(EMMC_BANK_NAND_T bank);
346 void EMMC_DisableNAND(EMMC_BANK_NAND_T bank);
347 void EMMC_EnablePCCARD(void);
348 void EMMC_DisablePCCARD(void);
349 void EMMC_EnableNANDECC(EMMC_BANK_NAND_T bank);
350 void EMMC_DisableNANDECC(EMMC_BANK_NAND_T bank);
351 uint32_t EMMC_ReadECC(EMMC_BANK_NAND_T bank);
352 
353 /** Interrupt and flag */
354 void EMMC_EnableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt);
355 void EMMC_DisableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt);
356 uint8_t EMMC_ReadStatusFlag(EMMC_BANK_NAND_T bank, EMMC_FLAG_T flag);
357 void EMMC_ClearStatusFlag(EMMC_BANK_NAND_T bank, uint32_t flag);
358 uint8_t EMMC_ReadIntFlag(EMMC_BANK_NAND_T bank, EMMC_INT_T flag);
359 void EMMC_ClearIntFlag(EMMC_BANK_NAND_T bank, uint32_t flag);
360 
361 /**@} end of group EMMC_Fuctions*/
362 /**@} end of group EMMC_Driver*/
363 /**@} end of group Peripherals_Library*/
364 
365 #ifdef __cplusplus
366 }
367 #endif
368 
369 #endif /* __APM32F10X_EMMC_H */
370