1 /*! 2 * @file apm32f10x_qspi.h 3 * 4 * @brief This file contains all the prototypes,enumeration and macros for the QSPI peripheral 5 * 6 * @version V1.0.4 7 * 8 * @date 2022-12-01 9 * 10 * @attention 11 * 12 * Copyright (C) 2020-2022 Geehy Semiconductor 13 * 14 * You may not use this file except in compliance with the 15 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). 16 * 17 * The program is only for reference, which is distributed in the hope 18 * that it will be useful and instructional for customers to develop 19 * their software. Unless required by applicable law or agreed to in 20 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT 21 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions 23 * and limitations under the License. 24 */ 25 26 /* Define to prevent recursive inclusion */ 27 #ifndef __APM32F10X_QSPI_H 28 #define __APM32F10X_QSPI_H 29 30 /* Includes */ 31 #include "apm32f10x.h" 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 /** @addtogroup APM32F10x_StdPeriphDriver 38 @{ 39 */ 40 41 /** @addtogroup QSPI_Driver QSPI Driver 42 @{ 43 */ 44 45 /** @defgroup QSPI_Macros Macros 46 @{ 47 */ 48 49 /* CTRL1 register reset value */ 50 #define QSPI_CTRL1_RESET_VALUE ((uint32_t)0x4007) 51 /* CTRL2 register reset value */ 52 #define QSPI_CTRL2_RESET_VALUE ((uint32_t)0x00) 53 /* SSIEN register reset value */ 54 #define QSPI_SSIEN_RESET_VALUE ((uint32_t)0x00) 55 /* SLAEN register reset value */ 56 #define QSPI_SLAEN_RESET_VALUE ((uint32_t)0x00) 57 /* BR register reset value */ 58 #define QSPI_BR_RESET_VALUE ((uint32_t)0x00) 59 /* TFTL register reset value */ 60 #define QSPI_TFTL_RESET_VALUE ((uint32_t)0x00) 61 /* RFTL register reset value */ 62 #define QSPI_RFTL_RESET_VALUE ((uint32_t)0x00) 63 /* TFL register reset value */ 64 #define QSPI_TFL_RESET_VALUE ((uint32_t)0x00) 65 /* RFL register reset value */ 66 #define QSPI_RFL_RESET_VALUE ((uint32_t)0x00) 67 /* STS register reset value */ 68 #define QSPI_STS_RESET_VALUE ((uint32_t)0x06) 69 /* INTEN register reset value */ 70 #define QSPI_INTEN_RESET_VALUE ((uint32_t)0x7F) 71 /* RSD register reset value */ 72 #define QSPI_RSD_RESET_VALUE ((uint32_t)0x00) 73 /* CTRL3 register reset value */ 74 #define QSPI_CTRL3_RESET_VALUE ((uint32_t)0x200) 75 /* IOSW register reset value */ 76 #define QSPI_IOSW_RESET_VALUE ((uint32_t)0x00) 77 78 /**@} end of group QSPI_Macros*/ 79 80 /** @defgroup QSPI_Enumerations Enumerations 81 @{ 82 */ 83 84 /** 85 * @brief Frame format 86 */ 87 typedef enum 88 { 89 QSPI_FRF_STANDARD, /*!< Standard mode */ 90 QSPI_FRF_DUAL, /*!< Dual SPI */ 91 QSPI_FRF_QUAD /*!< QUAD SPI */ 92 } QSPI_FRF_T; 93 94 /** 95 * @brief Transmission mode 96 */ 97 typedef enum 98 { 99 QSPI_TRANS_MODE_TX_RX, /*!< TX and RX mode */ 100 QSPI_TRANS_MODE_TX, /*!< TX mode only */ 101 QSPI_TRANS_MODE_RX, /*!< RX mode only */ 102 QSPI_TRANS_MODE_EEPROM_READ /*!< EEPROM read mode */ 103 } QSPI_TRANS_MODE_T; 104 105 /** 106 * @brief Clock polarity 107 */ 108 typedef enum 109 { 110 QSPI_CLKPOL_LOW, 111 QSPI_CLKPOL_HIGH 112 } QSPI_CLKPOL_T; 113 114 /** 115 * @brief Clock phase 116 */ 117 typedef enum 118 { 119 QSPI_CLKPHA_1EDGE, 120 QSPI_CLKPHA_2EDGE 121 } QSPI_CLKPHA_T; 122 123 /** 124 * @brief Data format size 125 */ 126 typedef enum 127 { 128 QSPI_DFS_4BIT = 3, 129 QSPI_DFS_5BIT, 130 QSPI_DFS_6BIT, 131 QSPI_DFS_7BIT, 132 QSPI_DFS_8BIT, 133 QSPI_DFS_9BIT, 134 QSPI_DFS_10BIT, 135 QSPI_DFS_11BIT, 136 QSPI_DFS_12BIT, 137 QSPI_DFS_13BIT, 138 QSPI_DFS_14BIT, 139 QSPI_DFS_15BIT, 140 QSPI_DFS_16BIT, 141 QSPI_DFS_17BIT, 142 QSPI_DFS_18BIT, 143 QSPI_DFS_19BIT, 144 QSPI_DFS_20BIT, 145 QSPI_DFS_21BIT, 146 QSPI_DFS_22BIT, 147 QSPI_DFS_23BIT, 148 QSPI_DFS_24BIT, 149 QSPI_DFS_25BIT, 150 QSPI_DFS_26BIT, 151 QSPI_DFS_27BIT, 152 QSPI_DFS_28BIT, 153 QSPI_DFS_29BIT, 154 QSPI_DFS_30BIT, 155 QSPI_DFS_31BIT, 156 QSPI_DFS_32BIT 157 } QSPI_DFS_T; 158 159 /** 160 * @brief QSPI flag 161 */ 162 typedef enum 163 { 164 QSPI_FLAG_BUSY = BIT0, /*!< Busy flag */ 165 QSPI_FLAG_TFNF = BIT1, /*!< TX FIFO not full flag */ 166 QSPI_FLAG_TFE = BIT2, /*!< TX FIFO empty flag */ 167 QSPI_FLAG_RFNE = BIT3, /*!< RX FIFO not empty flag */ 168 QSPI_FLAG_RFF = BIT4, /*!< RX FIFO full flag */ 169 QSPI_FLAG_DCE = BIT6 /*!< Data collision error */ 170 } QSPI_FLAG_T; 171 172 /** 173 * @brief QSPI interrupt source 174 */ 175 typedef enum 176 { 177 QSPI_INT_TFE = BIT0, /*!< TX FIFO empty interrupt */ 178 QSPI_INT_TFO = BIT1, /*!< TX FIFO overflow interrupt */ 179 QSPI_INT_RFU = BIT2, /*!< RX FIFO underflow interrupt */ 180 QSPI_INT_RFO = BIT3, /*!< RX FIFO overflow interrupt */ 181 QSPI_INT_RFF = BIT4, /*!< RX FIFO full interrupt */ 182 QSPI_INT_MST = BIT5 /*!< Master interrupt */ 183 } QSPI_INT_T; 184 185 /** 186 * @brief QSPI interrupt flag 187 */ 188 typedef enum 189 { 190 QSPI_INT_FLAG_TFE = BIT0, /*!< TX FIFO empty interrupt flag */ 191 QSPI_INT_FLAG_TFO = BIT1, /*!< TX FIFO overflow interrupt flag */ 192 QSPI_INT_FLAG_RFU = BIT2, /*!< RX FIFO underflow interrupt flag */ 193 QSPI_INT_FLAG_RFO = BIT3, /*!< RX FIFO overflow interrupt flag */ 194 QSPI_INT_FLAG_RFF = BIT4, /*!< RX FIFO full interrupt flag */ 195 QSPI_INT_FLAG_MST = BIT5 /*!< Master interrupt flag */ 196 } QSPI_INT_FLAG_T; 197 198 /** 199 * @brief Reception sample edge 200 */ 201 typedef enum 202 { 203 QSPI_RSE_RISING, 204 QSPI_RSE_FALLING 205 } QSPI_RSE_T; 206 207 /** 208 * @brief Instruction length 209 */ 210 typedef enum 211 { 212 QSPI_INST_LEN_0, 213 QSPI_INST_LEN_4BIT, 214 QSPI_INST_LEN_8BIT, 215 QSPI_INST_LEN_16BIT 216 } QSPI_INST_LEN_T; 217 218 /** 219 * @brief QSPI address length 220 */ 221 typedef enum 222 { 223 QSPI_ADDR_LEN_0, 224 QSPI_ADDR_LEN_4BIT, 225 QSPI_ADDR_LEN_8BIT, 226 QSPI_ADDR_LEN_12BIT, 227 QSPI_ADDR_LEN_16BIT, 228 QSPI_ADDR_LEN_20BIT, 229 QSPI_ADDR_LEN_24BIT, 230 QSPI_ADDR_LEN_28BIT, 231 QSPI_ADDR_LEN_32BIT, 232 QSPI_ADDR_LEN_36BIT, 233 QSPI_ADDR_LEN_40BIT, 234 QSPI_ADDR_LEN_44BIT, 235 QSPI_ADDR_LEN_48BIT, 236 QSPI_ADDR_LEN_52BIT, 237 QSPI_ADDR_LEN_56BIT, 238 QSPI_ADDR_LEN_60BIT 239 } QSPI_ADDR_LEN_T; 240 241 /** 242 * @brief Instruction and address transmission mode 243 */ 244 typedef enum 245 { 246 QSPI_INST_ADDR_TYPE_STANDARD, 247 QSPI_INST_TYPE_STANDARD, 248 QSPI_INST_ADDR_TYPE_FRF 249 } QSPI_INST_ADDR_TYPE_T; 250 251 /** 252 * @brief Slave Select Toggle 253 */ 254 typedef enum 255 { 256 QSPI_SST_DISABLE, 257 QSPI_SST_ENABLE 258 } QSPI_SST_T; 259 260 /**@} end of group QSPI_Enumerations*/ 261 262 /** @defgroup QSPI_Structure Data Structure 263 @{ 264 */ 265 typedef struct 266 { 267 QSPI_SST_T selectSlaveToggle; /*!< Slave Select Toggle */ 268 QSPI_FRF_T frameFormat; /*!< Frame format */ 269 uint16_t clockDiv; /*!< Clock divider */ 270 QSPI_CLKPOL_T clockPolarity; /*!< Clock polarity */ 271 QSPI_CLKPHA_T clockPhase; /*!< Clock phase */ 272 QSPI_DFS_T dataFrameSize; /*!< Data frame size */ 273 } QSPI_Config_T; 274 275 /**@} end of group QSPI_Structure*/ 276 277 /** @defgroup QSPI_Functions Functions 278 @{ 279 */ 280 281 /* Reset */ 282 void QSPI_Reset(void); 283 284 /* Configuration */ 285 void QSPI_Config(QSPI_Config_T* qspiConfig); 286 void QSPI_ConfigStructInit(QSPI_Config_T* qspiConfig); 287 288 /* Data frame size, frame number, frame format */ 289 void QSPI_ConfigFrameNum(uint16_t num); 290 void QSPI_ConfigDataFrameSize(QSPI_DFS_T dfs); 291 void QSPI_ConfigFrameFormat(QSPI_FRF_T frameFormat); 292 293 /* Disable or Enable */ 294 void QSPI_Enable(void); 295 void QSPI_Disable(void); 296 297 /* TX and RX FIFO */ 298 uint8_t QSPI_ReadTxFifoDataNum(void); 299 uint8_t QSPI_ReadRxFifoDataNum(void); 300 void QSPI_ConfigRxFifoThreshold(uint8_t threshold); 301 void QSPI_ConfigTxFifoThreshold(uint8_t threshold); 302 void QSPI_ConfigTxFifoEmptyThreshold(uint8_t threshold); 303 304 /* RX Sample */ 305 void QSPI_ConfigRxSampleEdge(QSPI_RSE_T rse); 306 void QSPI_ConfigRxSampleDelay(uint8_t delay); 307 308 /* Clock stretch */ 309 void QSPI_EnableClockStretch(void); 310 void QSPI_DisableClockStretch(void); 311 312 /* Instruction, address, Wait cycle */ 313 void QSPI_ConfigInstLen(QSPI_INST_LEN_T len); 314 void QSPI_ConfigAddrLen(QSPI_ADDR_LEN_T len); 315 void QSPI_ConfigInstAddrType(QSPI_INST_ADDR_TYPE_T type); 316 void QSPI_ConfigWaitCycle(uint8_t cycle); 317 318 /* IO */ 319 void QSPI_OpenIO(void); 320 void QSPI_CloseIO(void); 321 322 /* Transmission mode */ 323 void QSPI_ConfigTansMode(QSPI_TRANS_MODE_T mode); 324 325 /* Rx and Tx data */ 326 uint32_t QSPI_RxData(void); 327 void QSPI_TxData(uint32_t data); 328 329 /* Slave */ 330 void QSPI_EnableSlave(void); 331 void QSPI_DisableSlave(void); 332 333 /* Interrupt */ 334 void QSPI_EnableInterrupt(uint32_t interrupt); 335 void QSPI_DisableInterrupt(uint32_t interrupt); 336 337 /* Flag */ 338 uint8_t QSPI_ReadStatusFlag(QSPI_FLAG_T flag); 339 void QSPI_ClearStatusFlag(void); 340 uint8_t QSPI_ReadIntFlag(QSPI_INT_FLAG_T flag); 341 void QSPI_ClearIntFlag(uint32_t flag); 342 343 /**@} end of group QSPI_Functions*/ 344 /**@} end of group QSPI_Driver*/ 345 /**@} end of group APM32F10x_StdPeriphDriver*/ 346 347 #ifdef __cplusplus 348 } 349 #endif 350 351 #endif /* __APM32F10X_QSPI_H */ 352