1 /*!
2  * @file        apm32f10x_rcm.h
3  *
4  * @brief       This file contains all the functions prototypes for the RCM firmware library
5  *
6  * @version     V1.0.4
7  *
8  * @date        2022-12-01
9  *
10  * @attention
11  *
12  *  Copyright (C) 2020-2022 Geehy Semiconductor
13  *
14  *  You may not use this file except in compliance with the
15  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
16  *
17  *  The program is only for reference, which is distributed in the hope
18  *  that it will be useful and instructional for customers to develop
19  *  their software. Unless required by applicable law or agreed to in
20  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
21  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
22  *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
23  *  and limitations under the License.
24  */
25 
26 /* Define to prevent recursive inclusion */
27 #ifndef __APM32F10X_RCM_H
28 #define __APM32F10X_RCM_H
29 
30 /* Includes */
31 #include "apm32f10x.h"
32 
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36 
37 /** @addtogroup APM32F10x_StdPeriphDriver
38   @{
39 */
40 
41 /** @addtogroup RCM_Driver RCM Driver
42   @{
43 */
44 
45 /** @defgroup RCM_Enumerations Enumerations
46   @{
47 */
48 
49 /**
50  * @brief   HSE state
51  */
52 typedef enum
53 {
54     RCM_HSE_CLOSE,
55     RCM_HSE_OPEN,
56     RCM_HSE_BYPASS
57 } RCM_HSE_T;
58 
59 /**
60  * @brief   PLL multiplication factor
61  */
62 typedef enum
63 {
64 #if defined(APM32F10X_CL)
65     RCM_PLLMF_4 = 2,
66     RCM_PLLMF_5,
67     RCM_PLLMF_6,
68     RCM_PLLMF_7,
69     RCM_PLLMF_8,
70     RCM_PLLMF_9,
71     RCM_PLLMF_6_5 = 13,
72 #else
73     RCM_PLLMF_2,
74     RCM_PLLMF_3,
75     RCM_PLLMF_4,
76     RCM_PLLMF_5,
77     RCM_PLLMF_6,
78     RCM_PLLMF_7,
79     RCM_PLLMF_8,
80     RCM_PLLMF_9,
81     RCM_PLLMF_10,
82     RCM_PLLMF_11,
83     RCM_PLLMF_12,
84     RCM_PLLMF_13,
85     RCM_PLLMF_14,
86     RCM_PLLMF_15,
87     RCM_PLLMF_16
88 #endif
89 } RCM_PLLMF_T;
90 
91 /**
92  * @brief   PLL2 multiplication factor
93  */
94 typedef enum
95 {
96     RCM_PLL2MF_8  = 6,
97     RCM_PLL2MF_9  = 7,
98     RCM_PLL2MF_10 = 8,
99     RCM_PLL2MF_11 = 9,
100     RCM_PLL2MF_12 = 10,
101     RCM_PLL2MF_13 = 11,
102     RCM_PLL2MF_14 = 12,
103     RCM_PLL2MF_16 = 14,
104     RCM_PLL2MF_20 = 15
105 } RCM_PLL2MF_T;
106 
107 /**
108  * @brief   PLL3 multiplication factor
109  */
110 typedef enum
111 {
112     RCM_PLL3MF_8  = 6,
113     RCM_PLL3MF_9  = 7,
114     RCM_PLL3MF_10 = 8,
115     RCM_PLL3MF_11 = 9,
116     RCM_PLL3MF_12 = 10,
117     RCM_PLL3MF_13 = 11,
118     RCM_PLL3MF_14 = 12,
119     RCM_PLL3MF_16 = 14,
120     RCM_PLL3MF_20 = 15
121 } RCM_PLL3MF_T;
122 
123 /**
124  * @brief   System clock select
125  */
126 typedef enum
127 {
128     RCM_SYSCLK_SEL_HSI,
129     RCM_SYSCLK_SEL_HSE,
130     RCM_SYSCLK_SEL_PLL
131 } RCM_SYSCLK_SEL_T;
132 
133 #if defined(APM32F10X_CL)
134 /**
135  * @brief   PLLPSC1 Source
136  */
137 typedef enum
138 {
139     RCM_PLLPSC1_SRC_HSE,
140     RCM_PLLPSC1_SRC_PLL2
141 } RCM_PLLPSC1_SRC_T;
142 
143 /**
144  * @brief   PLLPSC1 divider Number
145  */
146 typedef enum
147 {
148     RCM_PLLPSC1_DIV_1,
149     RCM_PLLPSC1_DIV_2,
150     RCM_PLLPSC1_DIV_3,
151     RCM_PLLPSC1_DIV_4,
152     RCM_PLLPSC1_DIV_5,
153     RCM_PLLPSC1_DIV_6,
154     RCM_PLLPSC1_DIV_7,
155     RCM_PLLPSC1_DIV_8,
156     RCM_PLLPSC1_DIV_9,
157     RCM_PLLPSC1_DIV_10,
158     RCM_PLLPSC1_DIV_11,
159     RCM_PLLPSC1_DIV_12,
160     RCM_PLLPSC1_DIV_13,
161     RCM_PLLPSC1_DIV_14,
162     RCM_PLLPSC1_DIV_15,
163     RCM_PLLPSC1_DIV_16
164 } RCM_PLLPSC1_DIV_T;
165 
166 /**
167  * @brief   PLLPSC2 divider Number
168  */
169 typedef enum
170 {
171     RCM_PLLPSC2_DIV_1,
172     RCM_PLLPSC2_DIV_2,
173     RCM_PLLPSC2_DIV_3,
174     RCM_PLLPSC2_DIV_4,
175     RCM_PLLPSC2_DIV_5,
176     RCM_PLLPSC2_DIV_6,
177     RCM_PLLPSC2_DIV_7,
178     RCM_PLLPSC2_DIV_8,
179     RCM_PLLPSC2_DIV_9,
180     RCM_PLLPSC2_DIV_10,
181     RCM_PLLPSC2_DIV_11,
182     RCM_PLLPSC2_DIV_12,
183     RCM_PLLPSC2_DIV_13,
184     RCM_PLLPSC2_DIV_14,
185     RCM_PLLPSC2_DIV_15,
186     RCM_PLLPSC2_DIV_16
187 } RCM_PLLPSC2_DIV_T;
188 
189 #endif
190 
191 /**
192  * @brief   AHB divider Number
193  */
194 typedef enum
195 {
196     RCM_AHB_DIV_1 = 7,
197     RCM_AHB_DIV_2,
198     RCM_AHB_DIV_4,
199     RCM_AHB_DIV_8,
200     RCM_AHB_DIV_16,
201     RCM_AHB_DIV_64,
202     RCM_AHB_DIV_128,
203     RCM_AHB_DIV_256,
204     RCM_AHB_DIV_512
205 } RCM_AHB_DIV_T;
206 
207 /**
208  * @brief   APB divider Number
209  */
210 typedef enum
211 {
212     RCM_APB_DIV_1 = 3,
213     RCM_APB_DIV_2,
214     RCM_APB_DIV_4,
215     RCM_APB_DIV_8,
216     RCM_APB_DIV_16
217 } RCM_APB_DIV_T;
218 
219 /**
220  * @brief   USB divider Number
221  */
222 typedef enum
223 {
224     RCM_USB_DIV_1_5,
225     RCM_USB_DIV_1,
226     RCM_USB_DIV_2,
227     RCM_USB_DIV_2_5  /*!< (Only for High-density devices for APM32F103xx) */
228 } RCM_USB_DIV_T;
229 
230 /**
231  * @brief   OTG FS divider Number
232  */
233 typedef enum
234 {
235     RCM_OTGFS_DIV_1_5,
236     RCM_OTGFS_DIV_1
237 } RCM_OTGFS_DIV_T;
238 
239 /**
240  * @brief   FPU divider Number
241  */
242 typedef enum
243 {
244     RCM_FPU_DIV_1,
245     RCM_FPU_DIV_2
246 } RCM_FPU_DIV_T;
247 
248 /**
249  * @brief   ADC divider Number
250  */
251 typedef enum
252 {
253     RCM_PCLK2_DIV_2,
254     RCM_PCLK2_DIV_4,
255     RCM_PCLK2_DIV_6,
256     RCM_PCLK2_DIV_8
257 } RCM_PCLK2_DIV_T;
258 
259 /**
260  * @brief   LSE State
261  */
262 typedef enum
263 {
264     RCM_LSE_CLOSE,
265     RCM_LSE_OPEN,
266     RCM_LSE_BYPASS
267 } RCM_LSE_T;
268 
269 /**
270  * @brief   I2S2 clock select
271  */
272 typedef enum
273 {
274     RCM_I2S2CLK_SYSCLK,
275     RCM_I2S2CLK_DOUBLE_PLL3
276 } RCM_I2S2CLK_T;
277 
278 /**
279  * @brief   I2S3 clock select
280  */
281 typedef enum
282 {
283     RCM_I2S3CLK_SYSCLK,
284     RCM_I2S3CLK_DOUBLE_PLL3
285 } RCM_I2S3CLK_T;
286 
287 /**
288  * @brief   RTC clock select
289  */
290 typedef enum
291 {
292     RCM_RTCCLK_LSE = 1,
293     RCM_RTCCLK_LSI,
294     RCM_RTCCLK_HSE_DIV_128
295 } RCM_RTCCLK_T;
296 
297 /**
298  * @brief   Clock output control
299  */
300 typedef enum
301 {
302     RCM_MCOCLK_NO_CLOCK = 3,
303     RCM_MCOCLK_SYSCLK,
304     RCM_MCOCLK_HSI,
305     RCM_MCOCLK_HSE,
306     RCM_MCOCLK_PLLCLK_DIV_2,
307 #if defined(APM32F10X_CL)
308     RCM_MCOCLK_PLL2CLK = 8,
309     RCM_MCOCLK_PLL3CLK_DIV_2,
310     RCM_MCOCLK_OSCCLK,
311     RCM_MCOCLK_PLL3CLK
312 #endif
313 } RCM_MCOCLK_T;
314 
315 /**
316  * @brief   PLL entry clock select
317  */
318 typedef enum
319 {
320     RCM_PLLSEL_HSI_DIV_2 = 0,
321 #if defined(APM32F10X_CL)
322     RCM_PLLSEL_PREDIV1   = 1,
323 #else
324     RCM_PLLSEL_HSE       = 1,
325     RCM_PLLSEL_HSE_DIV2  = 3,
326 #endif /* APM32F10X_CL */
327 } RCM_PLLSEL_T;
328 
329 /**
330  * @brief   RCM Interrupt Source
331  */
332 typedef enum
333 {
334     RCM_INT_LSIRDY  = BIT0,  /*!< LSI ready interrupt */
335     RCM_INT_LSERDY  = BIT1,  /*!< LSE ready interrupt */
336     RCM_INT_HSIRDY  = BIT2,  /*!< HSI ready interrupt */
337     RCM_INT_HSERDY  = BIT3,  /*!< HSE ready interrupt */
338     RCM_INT_PLLRDY  = BIT4,  /*!< PLL ready interrupt */
339     RCM_INT_PLL2RDY = BIT5,  /*!< PLL2 ready interrupt */
340     RCM_INT_PLL3RDY = BIT6,  /*!< PLL3 ready interrupt */
341     RCM_INT_CSS     = BIT7   /*!< Clock security system interrupt */
342 } RCM_INT_T;
343 
344 /**
345  * @brief   AHB peripheral
346  */
347 typedef enum
348 {
349     RCM_AHB_PERIPH_DMA1       = BIT0,
350     RCM_AHB_PERIPH_DMA2       = BIT1,
351     RCM_AHB_PERIPH_SRAM       = BIT2,
352     RCM_AHB_PERIPH_FPU        = BIT3,
353     RCM_AHB_PERIPH_FMC        = BIT4,
354     RCM_AHB_PERIPH_QSPI       = BIT5,
355     RCM_AHB_PERIPH_CRC        = BIT6,
356     RCM_AHB_PERIPH_EMMC       = BIT8,
357     RCM_AHB_PERIPH_SDIO       = BIT10,
358     RCM_AHB_PERIPH_OTG_FS     = BIT12,
359     RCM_AHB_PERIPH_ETH_MAC    = BIT14,
360     RCM_AHB_PERIPH_ETH_MAC_TX = BIT15,
361     RCM_AHB_PERIPH_ETH_MAC_RX = BIT16
362 } RCM_AHB_PERIPH_T;
363 
364 /**
365  * @brief   AHB2 peripheral
366  */
367 typedef enum
368 {
369     RCM_APB2_PERIPH_AFIO    = BIT0,
370     RCM_APB2_PERIPH_GPIOA   = BIT2,
371     RCM_APB2_PERIPH_GPIOB   = BIT3,
372     RCM_APB2_PERIPH_GPIOC   = BIT4,
373     RCM_APB2_PERIPH_GPIOD   = BIT5,
374     RCM_APB2_PERIPH_GPIOE   = BIT6,
375     RCM_APB2_PERIPH_GPIOF   = BIT7,
376     RCM_APB2_PERIPH_GPIOG   = BIT8,
377     RCM_APB2_PERIPH_ADC1    = BIT9,
378     RCM_APB2_PERIPH_ADC2    = BIT10,
379     RCM_APB2_PERIPH_TMR1    = BIT11,
380     RCM_APB2_PERIPH_SPI1    = BIT12,
381     RCM_APB2_PERIPH_TMR8    = BIT13,
382     RCM_APB2_PERIPH_USART1  = BIT14,
383     RCM_APB2_PERIPH_ADC3    = BIT15
384 } RCM_APB2_PERIPH_T;
385 
386 /**
387  * @brief   AHB1 peripheral
388  */
389 typedef enum
390 {
391     RCM_APB1_PERIPH_TMR2   = BIT0,
392     RCM_APB1_PERIPH_TMR3   = BIT1,
393     RCM_APB1_PERIPH_TMR4   = BIT2,
394     RCM_APB1_PERIPH_TMR5   = BIT3,
395     RCM_APB1_PERIPH_TMR6   = BIT4,
396     RCM_APB1_PERIPH_TMR7   = BIT5,
397     RCM_APB1_PERIPH_WWDT   = BIT11,
398     RCM_APB1_PERIPH_SPI2   = BIT14,
399     RCM_APB1_PERIPH_SPI3   = BIT15,
400     RCM_APB1_PERIPH_USART2 = BIT17,
401     RCM_APB1_PERIPH_USART3 = BIT18,
402     RCM_APB1_PERIPH_UART4  = BIT19,
403     RCM_APB1_PERIPH_UART5  = BIT20,
404     RCM_APB1_PERIPH_I2C1   = BIT21,
405     RCM_APB1_PERIPH_I2C2   = BIT22,
406     RCM_APB1_PERIPH_USB    = BIT23,
407     RCM_APB1_PERIPH_CAN1   = BIT25,
408     RCM_APB1_PERIPH_CAN2   = BIT26,
409     RCM_APB1_PERIPH_BAKR   = BIT27,
410     RCM_APB1_PERIPH_PMU    = BIT28,
411     RCM_APB1_PERIPH_DAC    = BIT29
412 } RCM_APB1_PERIPH_T;
413 
414 /**
415  * @brief   RCM FLAG define
416  */
417 typedef enum
418 {
419     RCM_FLAG_HSIRDY  = 0x001,   /*!< HSI Ready Flag */
420     RCM_FLAG_HSERDY  = 0x011,   /*!< HSE Ready Flag */
421     RCM_FLAG_PLLRDY  = 0x019,   /*!< PLL Ready Flag */
422     RCM_FLAG_PLL2RDY = 0x01B,   /*!< PLL2 Ready Flag */
423     RCM_FLAG_PLL3RDY = 0x01D,   /*!< PLL3 Ready Flag */
424     RCM_FLAG_LSERDY  = 0x101,   /*!< LSE Ready Flag */
425     RCM_FLAG_LSIRDY  = 0x201,   /*!< LSI Ready Flag */
426     RCM_FLAG_PINRST  = 0x21A,   /*!< PIN reset flag */
427     RCM_FLAG_PORRST  = 0x21B,   /*!< POR/PDR reset flag */
428     RCM_FLAG_SWRST   = 0x21C,   /*!< Software reset flag */
429     RCM_FLAG_IWDTRST = 0x21D,   /*!< Independent watchdog reset flag */
430     RCM_FLAG_WWDTRST = 0x21E,   /*!< Window watchdog reset flag */
431     RCM_FLAG_LPRRST  = 0x21F    /*!< Low-power reset flag */
432 } RCM_FLAG_T;
433 
434 /**@} end of group RCM_Enumerations */
435 
436 
437 /** @defgroup RCM_Functions Functions
438   @{
439 */
440 
441 /* Function description */
442 
443 /* RCM Reset */
444 void RCM_Reset(void);
445 
446 /* HSE clock */
447 void RCM_ConfigHSE(RCM_HSE_T state);
448 uint8_t RCM_WaitHSEReady(void);
449 
450 /* HSI clock */
451 void RCM_ConfigHSITrim(uint8_t HSITrim);
452 void RCM_EnableHSI(void);
453 void RCM_DisableHSI(void);
454 
455 /* LSE and LSI clock */
456 void RCM_ConfigLSE(RCM_LSE_T state);
457 void RCM_EnableLSI(void);
458 void RCM_DisableLSI(void);
459 
460 /* PLL clock */
461 void RCM_ConfigPLL(RCM_PLLSEL_T pllSelect, RCM_PLLMF_T pllMf);
462 void RCM_EnablePLL(void);
463 void RCM_DisablePLL(void);
464 #if defined(APM32F10X_CL)
465 void RCM_EnablePLL2(void);
466 void RCM_DisablePLL2(void);
467 void RCM_EnablePLL3(void);
468 void RCM_DisablePLL3(void);
469 void RCM_ConfigPLLPSC1(RCM_PLLPSC1_SRC_T pllPsc1Src,  RCM_PLLPSC1_DIV_T pllPsc1);
470 void RCM_ConfigPLLPSC2(RCM_PLLPSC2_DIV_T pllpsc2);
471 void RCM_ConfigPLL2(RCM_PLL2MF_T pll2Mf);
472 void RCM_ConfigPLL3(RCM_PLL3MF_T pll3Mf);
473 #endif
474 
475 /* Clock Security System */
476 void RCM_EnableCSS(void);
477 void RCM_DisableCSS(void);
478 
479 void RCM_ConfigMCO(RCM_MCOCLK_T mcoClock);
480 void RCM_ConfigSYSCLK(RCM_SYSCLK_SEL_T sysClkSelect);
481 RCM_SYSCLK_SEL_T RCM_ReadSYSCLKSource(void);
482 
483 /* Config clock prescaler of AHB, APB1, APB2, USB and ADC */
484 void RCM_ConfigAHB(RCM_AHB_DIV_T AHBDiv);
485 void RCM_ConfigAPB1(RCM_APB_DIV_T APB1Div);
486 void RCM_ConfigAPB2(RCM_APB_DIV_T APB2Div);
487 #if defined(APM32F10X_CL)
488 void RCM_ConfigI2S2CLK(RCM_I2S2CLK_T i2s2ClkSelect);
489 void RCM_ConfigI2S3CLK(RCM_I2S2CLK_T i2s3ClkSelect);
490 void RCM_ConfigOTGFSCLK(RCM_OTGFS_DIV_T OTGDiv);
491 #else
492 void RCM_ConfigUSBCLK(RCM_USB_DIV_T USBDiv);
493 void RCM_ConfigFPUCLK(RCM_FPU_DIV_T FPUDiv);
494 #endif
495 void RCM_ConfigADCCLK(RCM_PCLK2_DIV_T ADCDiv);
496 
497 /* RTC clock */
498 void RCM_ConfigRTCCLK(RCM_RTCCLK_T rtcClkSelect);
499 void RCM_EnableRTCCLK(void);
500 void RCM_DisableRTCCLK(void);
501 
502 /* Reads the clock frequency */
503 uint32_t RCM_ReadSYSCLKFreq(void);
504 uint32_t RCM_ReadHCLKFreq(void);
505 void RCM_ReadPCLKFreq(uint32_t* PCLK1, uint32_t* PCLK2);
506 uint32_t RCM_ReadADCCLKFreq(void);
507 
508 /* Enable or disable Periph Clock */
509 void RCM_EnableAHBPeriphClock(uint32_t AHBPeriph);
510 void RCM_DisableAHBPeriphClock(uint32_t AHBPeriph);
511 void RCM_EnableAPB2PeriphClock(uint32_t APB2Periph);
512 void RCM_DisableAPB2PeriphClock(uint32_t APB2Periph);
513 void RCM_EnableAPB1PeriphClock(uint32_t APB1Periph);
514 void RCM_DisableAPB1PeriphClock(uint32_t APB1Periph);
515 
516 /* Enable or disable Periph Reset */
517 #if defined(APM32F10X_CL)
518 void RCM_EnableAHBPeriphReset(uint32_t AHBPeriph);
519 void RCM_DisableAHBPeriphReset(uint32_t AHBPeriph);
520 #endif
521 void RCM_EnableAPB2PeriphReset(uint32_t APB2Periph);
522 void RCM_DisableAPB2PeriphReset(uint32_t APB2Periph);
523 void RCM_EnableAPB1PeriphReset(uint32_t APB1Periph);
524 void RCM_DisableAPB1PeriphReset(uint32_t APB1Periph);
525 
526 /* Backup domain reset */
527 void RCM_EnableBackupReset(void);
528 void RCM_DisableBackupReset(void);
529 
530 /* Interrupts and flags */
531 void RCM_EnableInterrupt(uint32_t interrupt);
532 void RCM_DisableInterrupt(uint32_t interrupt);
533 uint8_t RCM_ReadStatusFlag(RCM_FLAG_T flag);
534 void RCM_ClearStatusFlag(void);
535 uint8_t RCM_ReadIntFlag(RCM_INT_T flag);
536 void RCM_ClearIntFlag(uint32_t flag);
537 
538 /**@} end of group RCM_Functions */
539 /**@} end of group RCM_Driver */
540 /**@} end of group APM32F10x_StdPeriphDriver */
541 
542 #ifdef __cplusplus
543 }
544 #endif
545 
546 #endif /* __APM32F10X_RCM_H */
547