1 /*! 2 * @file apm32f10x_sci2c.h 3 * 4 * @brief This file contains all the prototypes,enumeration and macros for the SCI2C(I2C3, I2C4) peripheral 5 * 6 * @version V1.0.4 7 * 8 * @date 2022-12-01 9 * 10 * @attention 11 * 12 * Copyright (C) 2020-2022 Geehy Semiconductor 13 * 14 * You may not use this file except in compliance with the 15 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). 16 * 17 * The program is only for reference, which is distributed in the hope 18 * that it will be useful and instructional for customers to develop 19 * their software. Unless required by applicable law or agreed to in 20 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT 21 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions 23 * and limitations under the License. 24 */ 25 26 /* Define to prevent recursive inclusion */ 27 #ifndef __APM32F10X_SCI2C_H 28 #define __APM32F10X_SCI2C_H 29 30 /* Includes */ 31 #include "apm32f10x.h" 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 /** @addtogroup APM32F10x_StdPeriphDriver 38 @{ 39 */ 40 41 /** @addtogroup SCI2C_Driver SCI2C Driver 42 @{ 43 */ 44 45 /** @defgroup SCI2C_Enumerations Enumerations 46 @{ 47 */ 48 49 /** 50 * @brief SCI2C speed enumeration 51 */ 52 typedef enum 53 { 54 SCI2C_SPEED_STANDARD = 1, 55 SCI2C_SPEED_FAST, 56 SCI2C_SPEED_HIGH 57 } SCI2C_SPEED_T; 58 59 /** 60 * @brief Address mode 61 */ 62 typedef enum 63 { 64 SCI2C_ADDR_MODE_7BIT, 65 SCI2C_ADDR_MODE_10BIT 66 } SCI2C_ADDR_MODE_T; 67 68 /** 69 * @brief SCI2C mode enumeration 70 */ 71 typedef enum 72 { 73 SCI2C_MODE_MASTER, 74 SCI2C_MODE_SLAVE 75 } SCI2C_MODE_T; 76 77 /** 78 * @brief Restart enable or disable 79 */ 80 typedef enum 81 { 82 SCI2C_RESTART_DISABLE, 83 SCI2C_RESTART_ENABLE 84 } SCI2C_RESTART_T; 85 86 /** 87 * @brief Enable or disable generate stop condition 88 */ 89 typedef enum 90 { 91 SCI2C_STOP_DISABLE, 92 SCI2C_STOP_ENABLE 93 } SCI2C_STOP_T; 94 /** 95 * @brief Data direction 96 */ 97 typedef enum 98 { 99 SCI2C_DATA_DIR_WRITE, 100 SCI2C_DATA_DIR_READ, 101 } SCI2C_DATA_DIR_T; 102 103 /** 104 * @brief SCI2C interrupt 105 */ 106 typedef enum 107 { 108 SCI2C_INT_RFU = BIT0, /*!< Rx FIFO underflow interrupt */ 109 SCI2C_INT_RFO = BIT1, /*!< Rx FIFO onverflow interrupt */ 110 SCI2C_INT_RFF = BIT2, /*!< Rx FIFO full interrupt */ 111 SCI2C_INT_TFO = BIT3, /*!< Tx FIFO onverflow interrupt */ 112 SCI2C_INT_TFE = BIT4, /*!< Tx FIFO empty interrupt */ 113 SCI2C_INT_RR = BIT5, /*!< Read request interrupt */ 114 SCI2C_INT_TA = BIT6, /*!< Tx abort interrupt */ 115 SCI2C_INT_RD = BIT7, /*!< Read done interrupt */ 116 SCI2C_INT_ACT = BIT8, /*!< Activity interrupt */ 117 SCI2C_INT_STPD = BIT9, /*!< Stop detect interrupt */ 118 SCI2C_INT_STAD = BIT10, /*!< Start detect interrupt */ 119 SCI2C_INT_GC = BIT11, /*!< Gernal call interrupt */ 120 SCI2C_INT_RSTAD = BIT12, /*!< Restart detect interrupt */ 121 SCI2C_INT_MOH = BIT13, /*!< Master on hold interrupt */ 122 SCI2C_INT_ALL = BIT15 /*!< All interrupt */ 123 } SCI2C_INT_T; 124 125 /** 126 * @brief Flag enumeration 127 */ 128 typedef enum 129 { 130 SCI2C_FLAG_ACT = BIT0, /*!< Activity flag */ 131 SCI2C_FLAG_TFNF = BIT1, /*!< Tx FIFO not full flag */ 132 SCI2C_FLAG_TFE = BIT2, /*!< Tx FIFO empty flag */ 133 SCI2C_FLAG_RFNE = BIT3, /*!< Rx FIFO not empty flag */ 134 SCI2C_FLAG_RFF = BIT4, /*!< Rx FIFO full flag */ 135 SCI2C_FLAG_MA = BIT5, /*!< Master activity flag */ 136 SCI2C_FLAG_SA = BIT6, /*!< Slave activity flag */ 137 SCI2C_FLAG_I2CEN = BIT8 | BIT0, /*!< I2C enable flag */ 138 SCI2C_FLAG_SDWB = BIT8 | BIT1, /*!< Slave disable while busy flag */ 139 SCI2C_FLAG_SRDL = BIT8 | BIT2 /*!< Slave receive data lost flag */ 140 } SCI2C_FLAG_T; 141 142 /** 143 * @brief Tx abort source 144 */ 145 typedef enum 146 { 147 SCI2C_TAS_AD7NA = BIT0, /*!< 7 bit address mode NACK */ 148 SCI2C_TAS_AD10FBNA = BIT1, /*!< 10 bit address mode first byte NACK */ 149 SCI2C_TAS_AD10SBNA = BIT2, /*!< 10 bit address mode second byte NACK */ 150 SCI2C_TAS_TDNA = BIT3, /*!< Tx data NACK */ 151 SCI2C_TAS_GCNA = BIT4, /*!< Gernal call NACK */ 152 SCI2C_TAS_GCR = BIT5, /*!< Gernal call read */ 153 SCI2C_TAS_HSAD = BIT6, /*!< High speed ack detected */ 154 SCI2C_TAS_SNR = BIT7, /*!< Start byte no restart */ 155 SCI2C_TAS_RNR10B = BIT8, /*!< Read 10bit address mode when restart disable */ 156 SCI2C_TAS_MSTDIS = BIT9, /*!< Master disable */ 157 SCI2C_TAS_ARBLOST = BIT10, /*!< Arbitration lost */ 158 SCI2C_TAS_LFTF = BIT11, /*!< Slave flush tx FIFO */ 159 SCI2C_TAS_SAL = BIT12, /*!< Slave arbitration lost */ 160 SCI2C_TAS_SRI = BIT13, /*!< Slave read done */ 161 SCI2C_TAS_USRARB = BIT14, /*!< User abort */ 162 SCI2C_TAS_FLUCNT = BIT15 /*!< Tx flush counter */ 163 } SCI2C_TAS_T; 164 165 /** 166 * @brief DMA Enable 167 */ 168 typedef enum 169 { 170 SCI2C_DMA_RX = BIT0, 171 SCI2C_DMA_TX = BIT1, 172 } SCI2C_DMA_T; 173 174 /**@} end of group SCI2C_Enumerations */ 175 176 /** @defgroup SCI2C_Macros Macros 177 @{ 178 */ 179 180 /* Macros description */ 181 #define SCI2C_CTRL1_RESET_VALUE ((uint32_t)0x3E) 182 #define SCI2C_TARADDR_RESET_VALUE ((uint32_t)0x1055) 183 #define SCI2C_SLAADDR_RESET_VALUE ((uint32_t)0x55) 184 #define SCI2C_HSMC_RESET_VALUE ((uint32_t)0x07) 185 #define SCI2C_DATA_RESET_VALUE ((uint32_t)0x00) 186 #define SCI2C_SSCHC_RESET_VALUE ((uint32_t)0x190) 187 #define SCI2C_SSCLC_RESET_VALUE ((uint32_t)0x1D6) 188 #define SCI2C_FSCHC_RESET_VALUE ((uint32_t)0x3C) 189 #define SCI2C_FSCLC_RESET_VALUE ((uint32_t)0x82) 190 #define SCI2C_HSCHC_RESET_VALUE ((uint32_t)0x06) 191 #define SCI2C_HSCLC_RESET_VALUE ((uint32_t)0x10) 192 #define SCI2C_INTEN_RESET_VALUE ((uint32_t)0x00) 193 #define SCI2C_RFT_RESET_VALUE ((uint32_t)0x00) 194 #define SCI2C_TFT_RESET_VALUE ((uint32_t)0x00) 195 #define SCI2C_CTRL2_RESET_VALUE ((uint32_t)0x00) 196 #define SCI2C_TFL_RESET_VALUE ((uint32_t)0x00) 197 #define SCI2C_RFL_RESET_VALUE ((uint32_t)0x00) 198 #define SCI2C_SDAHOLD_RESET_VALUE ((uint32_t)0x01) 199 #define SCI2C_SDNO_RESET_VALUE ((uint32_t)0x00) 200 #define SCI2C_DMACTRL_RESET_VALUE ((uint32_t)0x00) 201 #define SCI2C_DTDL_RESET_VALUE ((uint32_t)0x00) 202 #define SCI2C_DRDL_RESET_VALUE ((uint32_t)0x00) 203 #define SCI2C_SDADLY_RESET_VALUE ((uint32_t)0x64) 204 #define SCI2C_GCA_RESET_VALUE ((uint32_t)0x01) 205 #define SCI2C_LSSSL_RESET_VALUE ((uint32_t)0x05) 206 #define SCI2C_HSSSL_RESET_VALUE ((uint32_t)0x01) 207 208 #define SCI2C_FIFO_DEPTH (0X08) 209 210 /**@} end of group SCI2C_Macros */ 211 212 /** @defgroup SCI2C_Structures Structures 213 @{ 214 */ 215 216 /** 217 * @brief Structure description 218 */ 219 typedef struct 220 { 221 uint16_t slaveAddr; /*!< Slave address. */ 222 SCI2C_MODE_T mode; /*!< Specifies mode, master mode or slave mode */ 223 SCI2C_SPEED_T speed; /*!< Specifies speed. Standard speed, fast speed or high speed. */ 224 uint16_t clkLowPeriod; /*!< SCL high period */ 225 uint16_t clkHighPeriod; /*!< SCL low period */ 226 uint8_t rxFifoThreshold; /*!< Rx FIFO threshold */ 227 uint8_t txFifoThreshold; /*!< Tx FIFO threshold */ 228 SCI2C_RESTART_T restart; /*!< Enable or disable restart */ 229 SCI2C_ADDR_MODE_T addrMode; /*!< Address mode. 7-bit or 10-bit mode. */ 230 } SCI2C_Config_T; 231 232 /**@} end of group SCI2C_Structure */ 233 234 /** @defgroup SCI2C_Functions Functions 235 @{ 236 */ 237 238 /* Reset */ 239 void SCI2C_Reset(SCI2C_T* i2c); 240 241 /* Configuration */ 242 void SCI2C_Config(SCI2C_T* i2c, SCI2C_Config_T* sci2cConfig); 243 void SCI2C_ConfigStructInit(SCI2C_Config_T* sci2cConfig); 244 245 /* Stop detect */ 246 void SCI2C_EnableStopDetectAddressed(SCI2C_T* i2c); 247 void SCI2C_DisableStopDetectAddressed(SCI2C_T* i2c); 248 void SCI2C_EnableStopDetectMasterActivity(SCI2C_T* i2c); 249 void SCI2C_DisableStopDetectMasterActivity(SCI2C_T* i2c); 250 251 /* Restart */ 252 void SCI2C_EnableRestart(SCI2C_T* i2c); 253 void SCI2C_DisableRestart(SCI2C_T* i2c); 254 255 /* Speed */ 256 void SCI2C_ConfigSpeed(SCI2C_T* i2c, SCI2C_SPEED_T speed); 257 258 /* Address */ 259 void SCI2C_ConfigMasterAddr(SCI2C_T* i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr); 260 void SCI2C_ConfigSlaveAddr(SCI2C_T* i2c, SCI2C_ADDR_MODE_T mode, uint16_t addr); 261 262 /* Master mode and slave mode */ 263 void SCI2C_EnableMasterMode(SCI2C_T* i2c); 264 void SCI2C_DisableMasterMode(SCI2C_T* i2c); 265 void SCI2C_EnableSlaveMode(SCI2C_T* i2c); 266 void SCI2C_DisableSlaveMode(SCI2C_T* i2c); 267 void SCI2C_ConfigMasterCode(SCI2C_T* i2c, uint8_t code); 268 269 /* Data */ 270 void SCI2C_ConfigDataDir(SCI2C_T* i2c, SCI2C_DATA_DIR_T dir); 271 void SCI2C_TxData(SCI2C_T* i2c, uint8_t data); 272 uint8_t SCI2C_RxData(SCI2C_T* i2c); 273 void SCI2C_ConfigDataRegister(SCI2C_T* i2c, SCI2C_STOP_T stop, SCI2C_DATA_DIR_T dataDir, uint8_t data); 274 275 /* Rx and Tx FIFO */ 276 uint8_t SCI2C_ReadRxFifoDataCnt(SCI2C_T* i2c); 277 uint8_t SCI2C_ReadTxFifoDataCnt(SCI2C_T* i2c); 278 void SCI2C_ConfigRxFifoThreshold(SCI2C_T* i2c, uint8_t threshold); 279 void SCI2C_ConfigTxFifoThreshold(SCI2C_T* i2c, uint8_t threshold); 280 281 /* I2C Enable, disable, abort, block */ 282 void SCI2C_Enable(SCI2C_T* i2c); 283 void SCI2C_Disable(SCI2C_T* i2c); 284 void SCI2C_Abort(SCI2C_T* i2c); 285 void SCI2C_BlockTxCmd(SCI2C_T* i2c, uint8_t enable); 286 287 /* SCL and SDA */ 288 void SCI2C_ConfigClkPeriod(SCI2C_T* i2c, SCI2C_SPEED_T speed, uint16_t highPeriod, uint16_t lowPeriod); 289 void SCI2C_ConfigSDAHoldTime(SCI2C_T* i2c, uint16_t txHold, uint8_t rxHold); 290 void SCI2C_ConfigSDADelayTime(SCI2C_T* i2c, uint8_t delay); 291 292 /* ACK and NACK */ 293 void SCI2C_GernalCallAck(SCI2C_T* i2c, uint8_t enable); 294 void SCI2C_SlaveDataNackOnly(SCI2C_T* i2c, uint8_t enable); 295 296 /* Abort */ 297 uint32_t SCI2C_ReadTxAbortSource(SCI2C_T* i2c); 298 299 /* DMA */ 300 void SCI2C_EnableDMA(SCI2C_T* i2c, SCI2C_DMA_T dma); 301 void SCI2C_DisableDMA(SCI2C_T* i2c, SCI2C_DMA_T dma); 302 void SCI2C_ConfigDMATxDataLevel(SCI2C_T* i2c, uint8_t cnt); 303 void SCI2C_ConfigDMARxDataLevel(SCI2C_T* i2c, uint8_t cnt); 304 305 /* Spike suppression limit */ 306 void SCI2C_ConfigSpikeSuppressionLimit(SCI2C_T* i2c, SCI2C_SPEED_T speed, uint8_t limit); 307 308 /* Ingerrupt and flag */ 309 uint8_t SCI2C_ReadStatusFlag(SCI2C_T* i2c, SCI2C_FLAG_T flag); 310 void SCI2C_ClearIntFlag(SCI2C_T* i2c, SCI2C_INT_T flag); 311 uint8_t SCI2C_ReadIntFlag(SCI2C_T* i2c, SCI2C_INT_T flag); 312 uint8_t SCI2C_ReadRawIntFlag(SCI2C_T* i2c, SCI2C_INT_T flag); 313 void SCI2C_EnableInterrupt(SCI2C_T* i2c, uint16_t interrupt); 314 void SCI2C_DisableInterrupt(SCI2C_T* i2c, uint16_t interrupt); 315 316 /**@} end of group SCI2C_Functions */ 317 /**@} end of group SCI2C_Driver */ 318 /**@} end of group APM32F10x_StdPeriphDriver */ 319 320 #ifdef __cplusplus 321 } 322 #endif 323 324 #endif /* __APM32F10X_SCI2C_H */ 325