1 /*!
2  * @file        apm32f10x_smc.h
3  *
4  * @brief       This file contains all the functions prototypes for the SMC firmware library
5  *
6  * @version     V1.0.4
7  *
8  * @date        2022-12-01
9  *
10  * @attention
11  *
12  *  Copyright (C) 2020-2022 Geehy Semiconductor
13  *
14  *  You may not use this file except in compliance with the
15  *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
16  *
17  *  The program is only for reference, which is distributed in the hope
18  *  that it will be useful and instructional for customers to develop
19  *  their software. Unless required by applicable law or agreed to in
20  *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
21  *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
22  *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
23  *  and limitations under the License.
24  */
25 
26 /* Define to prevent recursive inclusion */
27 #ifndef __APM32F10X_SMC_H
28 #define __APM32F10X_SMC_H
29 
30 /* Includes */
31 #include "apm32f10x.h"
32 
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36 
37 /** @addtogroup APM32F10x_StdPeriphDriver
38   @{
39 */
40 
41 /** @addtogroup SMC_Driver SMC Driver
42   @{
43 */
44 
45 /** @defgroup SMC_Enumerations Enumerations
46   @{
47 */
48 
49 /**
50  * @brief SMC NORSRAM_Bank
51  */
52 typedef enum
53 {
54     SMC_BANK1_NORSRAM_1 = 0x00000000,
55     SMC_BANK1_NORSRAM_2 = 0x00000002,
56     SMC_BANK1_NORSRAM_3 = 0x00000004,
57     SMC_BANK1_NORSRAM_4 = 0x00000006
58 } SMC_BANK1_NORSRAM_T;
59 
60 /**
61  * @brief SMC NAND and PC Card Bank
62  */
63 typedef enum
64 {
65     SMC_BANK2_NAND   = 0x00000010,
66     SMC_BANK3_NAND   = 0x00000100,
67     SMC_BANK4_PCCARD = 0x00001000
68 } SMC_BANK_NAND_T;
69 
70 /**
71  * @brief SMC_Data_Address_Bus_Multiplexing
72  */
73 typedef enum
74 {
75     SMC_DATA_ADDRESS_MUX_DISABLE = 0x00000000,
76     SMC_DATA_ADDRESS_MUX_ENABLE  = 0x00000002
77 } SMC_DATA_ADDRESS_MUX_T;
78 
79 /**
80  * @brief SMC_Memory_Type
81  */
82 typedef enum
83 {
84     SMC_MEMORY_TYPE_SRAM  = 0x00000000,
85     SMC_MEMORY_TYPE_PSRAM = 0x00000004,
86     SMC_MEMORY_TYPE_NOR   = 0x00000008
87 } SMC_MEMORY_TYPE_T;
88 
89 /**
90  * @brief SMC_Data_Width
91  */
92 typedef enum
93 {
94     SMC_MEMORY_DATA_WIDTH_8BIT  = 0x00000000,
95     SMC_MEMORY_DATA_WIDTH_16BIT = 0x00000010
96 } SMC_MEMORY_DATA_WIDTH_T;
97 
98 /**
99  * @brief SMC_Burst_Access_Mode
100  */
101 typedef enum
102 {
103     SMC_BURST_ACCESS_MODE_DISABLE = 0x00000000,
104     SMC_BURST_ACCESS_MODE_ENABLE  = 0x00000100
105 } SMC_BURST_ACCESS_MODE_T;
106 
107 /**
108  * @brief SMC_AsynchronousWait
109  */
110 typedef enum
111 {
112     SMC_ASYNCHRONOUS_WAIT_DISABLE = 0x00000000,
113     SMC_ASYNCHRONOUS_WAIT_ENABLE  = 0x00008000
114 } SMC_ASYNCHRONOUS_WAIT_T;
115 
116 /**
117  * @brief SMC_Wait_Signal_Polarity
118  */
119 typedef enum
120 {
121     SMC_WAIT_SIGNAL_POLARITY_LOW  = 0x00000000,
122     SMC_WAIT_SIGNAL_POLARITY_HIGH = 0x00000200
123 } SMC_WAIT_SIGNAL_POLARITY_T;
124 
125 /**
126  * @brief SMC_Wrap_Mode
127  */
128 typedef enum
129 {
130     SMC_WRAP_MODE_DISABLE = 0x00000000,
131     SMC_WRAP_MODE_ENABLE  = 0x00000400
132 } SMC_WRAP_MODE_T;
133 
134 /**
135  * @brief SMC_Wait_Timing
136  */
137 typedef enum
138 {
139     SMC_WAIT_SIGNAL_ACTIVE_BEFORE_WAIT = 0x00000000,
140     SMC_WAIT_SIGNAL_ACTIVE_DURING_WAIT = 0x00000800
141 } SMC_WAIT_SIGNAL_ACTIVE_T;
142 
143 /**
144  * @brief SMC_Write_Operation
145  */
146 typedef enum
147 {
148     SMC_WRITE_OPERATION_DISABLE = 0x00000000,
149     SMC_WRITE_OPERATION_ENABLE  = 0x00001000
150 } SMC_WRITE_OPERATION_T;
151 
152 /**
153  * @brief SMC_Wait_Signal
154  */
155 typedef enum
156 {
157     SMC_WAITE_SIGNAL_DISABLE = 0x00000000,
158     SMC_WAITE_SIGNAL_ENABLE  = 0x00002000
159 } SMC_WAITE_SIGNAL_T;
160 
161 /**
162  * @brief SMC_Extended_Mode
163  */
164 typedef enum
165 {
166     SMC_EXTENDEN_MODE_DISABLE = 0x00000000,
167     SMC_EXTENDEN_MODE_ENABLE  = 0x00004000
168 } SMC_EXTENDEN_MODE_T;
169 
170 /**
171  * @brief SMC_Write_Burst
172  */
173 typedef enum
174 {
175     SMC_WRITE_BURST_DISABLE = 0x00000000,
176     SMC_WRITE_BURST_ENABLE  = 0x00080000
177 } SMC_WRITE_BURST_T;
178 
179 /**
180  * @brief   SMC_WAIT_FEATURE
181  */
182 typedef enum
183 {
184     SMC_WAIT_FEATURE_DISABLE = 0x00000000,
185     SMC_WAIT_FEATURE_ENABLE  = 0x00000002
186 } SMC_WAIT_FEATURE_T;
187 
188 /**
189  * @brief SMC_ECC
190  */
191 typedef enum
192 {
193     SMC_ECC_DISABLE = 0x00000000,
194     SMC_ECC_ENABLE  = 0x00000040
195 } SMC_ECC_T;
196 
197 /**
198  * @brief SMC_ECC_Page_Size
199  */
200 typedef enum
201 {
202     SMC_ECC_PAGE_SIZE_BYTE_256  = 0x00000000,
203     SMC_ECC_PAGE_SIZE_BYTE_512  = 0x00020000,
204     SMC_ECC_PAGE_SIZE_BYTE_1024 = 0x00040000,
205     SMC_ECC_PAGE_SIZE_BYTE_2048 = 0x00060000,
206     SMC_ECC_PAGE_SIZE_BYTE_4096 = 0x00080000,
207     SMC_ECC_PAGE_SIZE_BYTE_8192 = 0x000A0000
208 } SMC_ECC_PAGE_SIZE_BYTE_T;
209 
210 /**
211  * @brief SMC_Access_Mode
212  */
213 typedef enum
214 {
215     SMC_ACCESS_MODE_A = 0x00000000,
216     SMC_ACCESS_MODE_B = 0x10000000,
217     SMC_ACCESS_MODE_C = 0x20000000,
218     SMC_ACCESS_MODE_D = 0x30000000
219 } SMC_ACCESS_MODE_T;
220 
221 /**
222  * @brief  SMC_Interrupt_sources
223  */
224 typedef enum
225 {
226     SMC_INT_EDGE_RISING  = 0x00000008,
227     SMC_INT_LEVEL_HIGH   = 0x00000010,
228     SMC_INT_EDGE_FALLING = 0x00000020
229 } SMC_INT_T;
230 
231 /**
232  * @brief  SMC_Flags
233  */
234 typedef enum
235 {
236     SMC_FLAG_EDGE_RISING  = 0x00000001,
237     SMC_FLAG_LEVEL_HIGH   = 0x00000002,
238     SMC_FLAG_EDGE_FALLING = 0x00000004,
239     SMC_FLAG_FIFO_EMPTY   = 0x00000040
240 } SMC_FLAG_T;
241 
242 /**@} end of group SMC_Enumerations */
243 
244 /** @defgroup SMC_Structures Structures
245   @{
246 */
247 
248 /**
249  * @brief Timing parameters for NOR/SRAM Banks
250  */
251 typedef struct
252 {
253     uint32_t           addressSetupTime;
254     uint32_t           addressHodeTime;
255     uint32_t           dataSetupTime;
256     uint32_t           busTurnaroundTime;
257     uint32_t           clockDivision;
258     uint32_t           dataLatency;
259     SMC_ACCESS_MODE_T accessMode;
260 } SMC_NORSRAMTimingConfig_T;
261 
262 /**
263  * @brief SMC NOR/SRAM Configure structure
264  */
265 typedef struct
266 {
267     SMC_BANK1_NORSRAM_T        bank;
268     SMC_DATA_ADDRESS_MUX_T     dataAddressMux;
269     SMC_MEMORY_TYPE_T          memoryType;
270     SMC_MEMORY_DATA_WIDTH_T    memoryDataWidth;
271     SMC_BURST_ACCESS_MODE_T    burstAcceesMode;
272     SMC_ASYNCHRONOUS_WAIT_T    asynchronousWait;
273     SMC_WAIT_SIGNAL_POLARITY_T waitSignalPolarity;
274     SMC_WRAP_MODE_T            wrapMode;
275     SMC_WAIT_SIGNAL_ACTIVE_T   waitSignalActive;
276     SMC_WRITE_OPERATION_T      writeOperation;
277     SMC_WAITE_SIGNAL_T         waiteSignal;
278     SMC_EXTENDEN_MODE_T        extendedMode;
279     SMC_WRITE_BURST_T          writeBurst;
280     SMC_NORSRAMTimingConfig_T*   readWriteTimingStruct;
281     SMC_NORSRAMTimingConfig_T*   writeTimingStruct;
282 } SMC_NORSRAMConfig_T;
283 
284 /**
285  * @brief Timing parameters for NAND and PCCARD Banks
286  */
287 typedef struct
288 {
289     uint32_t setupTime;
290     uint32_t waitSetupTime;
291     uint32_t holdSetupTime;
292     uint32_t HiZSetupTime;
293 } SMC_NAND_PCCARDTimingConfig_T;
294 
295 /**
296  * @brief SMC NAND Configure structure
297  */
298 typedef struct
299 {
300     SMC_BANK_NAND_T          bank;
301     SMC_WAIT_FEATURE_T       waitFeature;
302     SMC_MEMORY_DATA_WIDTH_T  memoryDataWidth;
303     SMC_ECC_T                ECC;
304     SMC_ECC_PAGE_SIZE_BYTE_T ECCPageSize;
305     uint32_t                  TCLRSetupTime;
306     uint32_t                  TARSetupTime;
307     SMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct;
308     SMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct;
309 } SMC_NANDConfig_T;
310 
311 /**
312  * @brief SMC PCCARD Configure structure
313  */
314 typedef struct
315 {
316     SMC_WAIT_FEATURE_T waitFeature;
317     uint32_t            TCLRSetupTime;
318     uint32_t            TARSetupTime;
319     SMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct;
320     SMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct;
321     SMC_NAND_PCCARDTimingConfig_T* IOSpaceTimingStruct;
322 } SMC_PCCARDConfig_T;
323 
324 /**@} end of group SMC_Structures */
325 
326 /** @defgroup SMC_Functions Functions
327   @{
328 */
329 
330 /* SMC reset */
331 void SMC_ResetNORSRAM(SMC_BANK1_NORSRAM_T bank);
332 void SMC_ResetNAND(SMC_BANK_NAND_T bank);
333 void SMC_ResetPCCard(void);
334 
335 /* SMC Configuration */
336 void SMC_ConfigNORSRAM(SMC_NORSRAMConfig_T* smcNORSRAMConfig);
337 void SMC_ConfigNAND(SMC_NANDConfig_T* smcNANDConfig);
338 void SMC_ConfigPCCard(SMC_PCCARDConfig_T* smcPCCardConfig);
339 void SMC_ConfigNORSRAMStructInit(SMC_NORSRAMConfig_T* smcNORSRAMConfig);
340 void SMC_ConfigNANDStructInit(SMC_NANDConfig_T* smcNANDConfig);
341 void SMC_ConfigPCCardStructInit(SMC_PCCARDConfig_T* smcPCCardConfig);
342 
343 /* SMC bank control */
344 void SMC_EnableNORSRAM(SMC_BANK1_NORSRAM_T bank);
345 void SMC_DisableNORSRAM(SMC_BANK1_NORSRAM_T bank);
346 void SMC_EnableNAND(SMC_BANK_NAND_T bank);
347 void SMC_DisableNAND(SMC_BANK_NAND_T bank);
348 void SMC_EnablePCCARD(void);
349 void SMC_DisablePCCARD(void);
350 void SMC_EnableNANDECC(SMC_BANK_NAND_T bank);
351 void SMC_DisableNANDECC(SMC_BANK_NAND_T bank);
352 uint32_t SMC_ReadECC(SMC_BANK_NAND_T bank);
353 
354 /* Interrupt and flag */
355 void SMC_EnableInterrupt(SMC_BANK_NAND_T bank, uint32_t interrupt);
356 void SMC_DisableInterrupt(SMC_BANK_NAND_T bank, uint32_t interrupt);
357 uint8_t SMC_ReadStatusFlag(SMC_BANK_NAND_T bank, SMC_FLAG_T flag);
358 void SMC_ClearStatusFlag(SMC_BANK_NAND_T bank, uint32_t flag);
359 uint8_t SMC_ReadIntFlag(SMC_BANK_NAND_T bank, SMC_INT_T flag);
360 void SMC_ClearIntFlag(SMC_BANK_NAND_T bank, uint32_t flag);
361 
362 /**@} end of group SMC_Functions */
363 /**@} end of group SMC_Driver */
364 /**@} end of group APM32F10x_StdPeriphDriver */
365 
366 #ifdef __cplusplus
367 }
368 #endif
369 
370 #endif /* __APM32F10X_SMC_H */
371