1 /*!
2 * @file apm32f10x_emmc.c
3 *
4 * @brief This file provides all the EMMC firmware functions
5 *
6 * @version V1.0.2
7 *
8 * @date 2022-01-05
9 *
10 * @attention
11 *
12 * Copyright (C) 2020-2022 Geehy Semiconductor
13 *
14 * You may not use this file except in compliance with the
15 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
16 *
17 * The program is only for reference, which is distributed in the hope
18 * that it will be usefull and instructional for customers to develop
19 * their software. Unless required by applicable law or agreed to in
20 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
21 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
23 * and limitations under the License.
24 */
25
26 #include "apm32f10x_emmc.h"
27 #include "apm32f10x_rcm.h"
28
29 /** @addtogroup Peripherals_Library Standard Peripheral Library
30 @{
31 */
32
33 /** @addtogroup EMMC_Driver EMMC Driver
34 @{
35 */
36
37 /** @addtogroup EMMC_Fuctions Fuctions
38 @{
39 */
40
41 /*!
42 * @brief Rest the EMMMC NOR/SRAM Banks registers
43 *
44 * @param bank: Selects the EMMMC Bank.
45 * The parameter can be one of following values:
46 * @arg EMMC_BANK1_NORSRAM_1: EMMC Bank1 NOR/SRAM1
47 * @arg EMMC_BANK1_NORSRAM_2: EMMC Bank1 NOR/SRAM2
48 * @arg EMMC_BANK1_NORSRAM_3: EMMC Bank1 NOR/SRAM3
49 * @arg EMMC_BANK1_NORSRAM_4: EMMC Bank1 NOR/SRAM4
50 *
51 * @retval None
52 */
EMMC_ResetNORSRAM(EMMC_BANK1_NORSRAM_T bank)53 void EMMC_ResetNORSRAM(EMMC_BANK1_NORSRAM_T bank)
54 {
55 /** EMMC_BANK1_NORSRAM_1 */
56 if (bank == EMMC_BANK1_NORSRAM_1)
57 {
58 EMMC_Bank1->SNCTRL_T[bank] = 0x000030DB;
59 }
60 /** EMMC_BANK1_NORSRAM_2, EMMC_BANK1_NORSRAM_3 or EMMC_BANK1_NORSRAM_4 */
61 else
62 {
63 EMMC_Bank1->SNCTRL_T[bank] = 0x000030D2;
64 }
65 EMMC_Bank1->SNCTRL_T[bank + 1] = 0x0FFFFFFF;
66 EMMC_Bank1E->WRTTIM[bank] = 0x0FFFFFFF;
67 }
68
69 /*!
70 * @brief Rest the EMMMC NAND Banks registers
71 *
72 * @param bank: Selects the EMMMC Bank.
73 * The parameter can be one of following values:
74 * @arg EMMC_BANK2_NAND: FSMC Bank2 NAND
75 * @arg EMMC_BANK3_NAND: FSMC Bank3 NAND
76 *
77 * @retval None
78 */
EMMC_ResetNAND(EMMC_BANK_NAND_T bank)79 void EMMC_ResetNAND(EMMC_BANK_NAND_T bank)
80 {
81 if (bank == EMMC_BANK2_NAND)
82 {
83 /** Set the EMMC_Bank2 registers to their reset values */
84 EMMC_Bank2->CTRL2 = 0x00000018;
85 EMMC_Bank2->STSINT2 = 0x00000040;
86 EMMC_Bank2->CMSTIM2 = 0xFCFCFCFC;
87 EMMC_Bank2->AMSTIM2 = 0xFCFCFCFC;
88 }
89 /** EMMC_BANK3_NAND */
90 else
91 {
92 /** Set the EMMC_Bank3 registers to their reset values */
93 EMMC_Bank3->CTRL3 = 0x00000018;
94 EMMC_Bank3->STSINT3 = 0x00000040;
95 EMMC_Bank3->CMSTIM3 = 0xFCFCFCFC;
96 EMMC_Bank3->AMSTIM3 = 0xFCFCFCFC;
97 }
98 }
99
100 /*!
101 * @brief Reset the EMMMC PCCARD Banks registers
102 *
103 * @param None
104 *
105 * @retval None
106 */
EMMC_ResetPCCard(void)107 void EMMC_ResetPCCard(void)
108 {
109 /** Set the EMMC_Bank4 registers to their reset values */
110 EMMC_Bank4->CTRL4 = 0x00000018;
111 EMMC_Bank4->STSINT4 = 0x00000040;
112 EMMC_Bank4->CMSTIM4 = 0xFCFCFCFC;
113 EMMC_Bank4->AMSTIM4 = 0xFCFCFCFC;
114 EMMC_Bank4->IOSTIM4 = 0xFCFCFCFC;
115 }
116
117 /*!
118 * @brief Config the EMMC NOR/SRAM Banks according to the specified parameters in the emmcNORSRAMConfig.
119 *
120 * @param emmcNORSRAMConfig: Point to a EMMC_NORSRAMConfig_T structure
121 *
122 * @retval None
123 */
EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T * emmcNORSRAMConfig)124 void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T *emmcNORSRAMConfig)
125 {
126 /** Bank1 NOR/SRAM control register configuration */
127 EMMC_Bank1->SNCTRL_T[emmcNORSRAMConfig->bank] =
128 (uint32_t)emmcNORSRAMConfig->dataAddressMux |
129 emmcNORSRAMConfig->memoryType |
130 emmcNORSRAMConfig->memoryDataWidth |
131 emmcNORSRAMConfig->burstAcceesMode |
132 emmcNORSRAMConfig->asynchronousWait |
133 emmcNORSRAMConfig->waitSignalPolarity |
134 emmcNORSRAMConfig->wrapMode |
135 emmcNORSRAMConfig->waitSignalActive |
136 emmcNORSRAMConfig->writeOperation |
137 emmcNORSRAMConfig->waiteSignal |
138 emmcNORSRAMConfig->extendedMode |
139 emmcNORSRAMConfig->writeBurst;
140
141 if (emmcNORSRAMConfig->memoryType == EMMC_MEMORY_TYPE_NOR)
142 {
143 EMMC_Bank1->SNCTRL_T[emmcNORSRAMConfig->bank] |= 0x00000040;
144 }
145
146 /** Bank1 NOR/SRAM timing register configuration */
147 EMMC_Bank1->SNCTRL_T[emmcNORSRAMConfig->bank + 1] =
148 (uint32_t)emmcNORSRAMConfig->readWriteTimingStruct->addressSetupTime |
149 (emmcNORSRAMConfig->readWriteTimingStruct->addressHodeTime << 4) |
150 (emmcNORSRAMConfig->readWriteTimingStruct->dataSetupTime << 8) |
151 (emmcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime << 16) |
152 (emmcNORSRAMConfig->readWriteTimingStruct->clockDivision << 20) |
153 (emmcNORSRAMConfig->readWriteTimingStruct->dataLatency << 24) |
154 emmcNORSRAMConfig->readWriteTimingStruct->accessMode;
155
156 /** Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
157 if (emmcNORSRAMConfig->extendedMode == EMMC_EXTENDEN_MODE_ENABLE)
158 {
159 EMMC_Bank1E->WRTTIM[emmcNORSRAMConfig->bank] =
160 (uint32_t)emmcNORSRAMConfig->writeTimingStruct->addressSetupTime |
161 (emmcNORSRAMConfig->writeTimingStruct->addressHodeTime << 4) |
162 (emmcNORSRAMConfig->writeTimingStruct->dataSetupTime << 8) |
163 (emmcNORSRAMConfig->writeTimingStruct->clockDivision << 20) |
164 (emmcNORSRAMConfig->writeTimingStruct->dataLatency << 24) |
165 emmcNORSRAMConfig->writeTimingStruct->accessMode;
166 }
167 else
168 {
169 EMMC_Bank1E->WRTTIM[emmcNORSRAMConfig->bank] = 0x0FFFFFFF;
170 }
171 }
172
173 /*!
174 * @brief Config the EMMC NAND Banks according to the specified parameters in the emmcNANDConfig.
175 *
176 * @param emmcNANDConfig : Point to a EMMC_NANDConfig_T structure.
177 *
178 * @retval None
179 */
EMMC_ConfigNAND(EMMC_NANDConfig_T * emmcNANDConfig)180 void EMMC_ConfigNAND(EMMC_NANDConfig_T *emmcNANDConfig)
181 {
182 uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
183
184 /** Set the tmppcr value according to EMMC_NANDInitStruct parameters */
185 tmppcr = (uint32_t)emmcNANDConfig->waitFeature | 0x00000008 |
186 emmcNANDConfig->memoryDataWidth |
187 emmcNANDConfig->ECC |
188 emmcNANDConfig->ECCPageSize |
189 (emmcNANDConfig->TCLRSetupTime << 9) |
190 (emmcNANDConfig->TARSetupTime << 13);
191
192 /** Set tmppmem value according to EMMC_CommonSpaceTimingStructure parameters */
193 tmppmem = (uint32_t)emmcNANDConfig->commonSpaceTimingStruct->setupTime |
194 (emmcNANDConfig->commonSpaceTimingStruct->waitSetupTime << 8) |
195 (emmcNANDConfig->commonSpaceTimingStruct->holdSetupTime << 16) |
196 (emmcNANDConfig->commonSpaceTimingStruct->HiZSetupTime << 24);
197
198 /** Set tmppatt value according to EMMC_AttributeSpaceTimingStructure parameters */
199 tmppatt = (uint32_t)emmcNANDConfig->attributeSpaceTimingStruct->setupTime |
200 (emmcNANDConfig->attributeSpaceTimingStruct->waitSetupTime << 8) |
201 (emmcNANDConfig->attributeSpaceTimingStruct->holdSetupTime << 16) |
202 (emmcNANDConfig->attributeSpaceTimingStruct->HiZSetupTime << 24);
203
204 if (emmcNANDConfig->bank == EMMC_BANK2_NAND)
205 {
206 /** EMMC_BANK2_NAND registers configuration */
207 EMMC_Bank2->CTRL2 = tmppcr;
208 EMMC_Bank2->CMSTIM2 = tmppmem;
209 EMMC_Bank2->AMSTIM2 = tmppatt;
210 }
211 else
212 {
213 /** EMMC_BANK3_NAND registers configuration */
214 EMMC_Bank3->CTRL3 = tmppcr;
215 EMMC_Bank3->CMSTIM3 = tmppmem;
216 EMMC_Bank3->AMSTIM3 = tmppatt;
217 }
218
219 }
220
221 /*!
222 * @brief Config the EMMC PCCARD according to the specified parameters in the emmcPCCardConfig.
223 *
224 * @param emmcPCCardConfig: Point to a EMMC_PCCARDConfig_T structure.
225 *
226 * @retval None
227 */
EMMC_ConfigPCCard(EMMC_PCCARDConfig_T * emmcPCCardConfig)228 void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T *emmcPCCardConfig)
229 {
230 /** Set the PCR4 register value according to EMMC_PCCARDInitStruct parameters */
231 EMMC_Bank4->CTRL4 = (uint32_t)emmcPCCardConfig->waitFeature | EMMC_MEMORY_DATA_WIDTH_16BIT |
232 (emmcPCCardConfig->TCLRSetupTime << 9) |
233 (emmcPCCardConfig->TARSetupTime << 13);
234
235 /** Set PMEM4 register value according to EMMC_CommonSpaceTimingStructure parameters */
236 EMMC_Bank4->CMSTIM4 = (uint32_t)emmcPCCardConfig->commonSpaceTimingStruct->setupTime |
237 (emmcPCCardConfig->commonSpaceTimingStruct->waitSetupTime << 8) |
238 (emmcPCCardConfig->commonSpaceTimingStruct->holdSetupTime << 16) |
239 (emmcPCCardConfig->commonSpaceTimingStruct->HiZSetupTime << 24);
240
241 /** Set PATT4 register value according to EMMC_AttributeSpaceTimingStructure parameters */
242 EMMC_Bank4->AMSTIM4 = (uint32_t)emmcPCCardConfig->attributeSpaceTimingStruct->setupTime |
243 (emmcPCCardConfig->attributeSpaceTimingStruct->waitSetupTime << 8) |
244 (emmcPCCardConfig->attributeSpaceTimingStruct->holdSetupTime << 16) |
245 (emmcPCCardConfig->attributeSpaceTimingStruct->HiZSetupTime << 24);
246
247 /** Set PIO4 register value according to EMMC_IOSpaceTimingStructure parameters */
248 EMMC_Bank4->IOSTIM4 = (uint32_t)emmcPCCardConfig->IOSpaceTimingStruct->setupTime |
249 (emmcPCCardConfig->IOSpaceTimingStruct->waitSetupTime << 8) |
250 (emmcPCCardConfig->IOSpaceTimingStruct->holdSetupTime << 16) |
251 (emmcPCCardConfig->IOSpaceTimingStruct->HiZSetupTime << 24);
252 }
253
254 /*!
255 * @brief Fills each emmcNORSRAMConfig member with its default value.
256 *
257 * @param emmcNORSRAMConfig : Point to a EMMC_NORSRAMConfig_T structure.
258 *
259 * @retval None
260 */
EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T * emmcNORSRAMConfig)261 void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T *emmcNORSRAMConfig)
262 {
263 /** Reset NOR/SRAM Init structure parameters values */
264 emmcNORSRAMConfig->bank = EMMC_BANK1_NORSRAM_1;
265 emmcNORSRAMConfig->dataAddressMux = EMMC_DATA_ADDRESS_MUX_ENABLE;
266 emmcNORSRAMConfig->memoryType = EMMC_MEMORY_TYPE_SRAM;
267 emmcNORSRAMConfig->memoryDataWidth = EMMC_MEMORY_DATA_WIDTH_8BIT;
268 emmcNORSRAMConfig->burstAcceesMode = EMMC_BURST_ACCESS_MODE_DISABLE;
269 emmcNORSRAMConfig->asynchronousWait = EMMC_ASYNCHRONOUS_WAIT_DISABLE;
270 emmcNORSRAMConfig->waitSignalPolarity = EMMC_WAIT_SIGNAL_POLARITY_LOW;
271 emmcNORSRAMConfig->wrapMode = EMMC_WRAP_MODE_DISABLE;
272 emmcNORSRAMConfig->waitSignalActive = EMMC_WAIT_SIGNAL_ACTIVE_BEFORE_WAIT;
273 emmcNORSRAMConfig->writeOperation = EMMC_WRITE_OPERATION_ENABLE;
274 emmcNORSRAMConfig->waiteSignal = EMMC_WAITE_SIGNAL_ENABLE;
275 emmcNORSRAMConfig->extendedMode = EMMC_EXTENDEN_MODE_DISABLE;
276 emmcNORSRAMConfig->writeBurst = EMMC_WRITE_BURST_DISABLE;
277 emmcNORSRAMConfig->readWriteTimingStruct->addressSetupTime = 0xF;
278 emmcNORSRAMConfig->readWriteTimingStruct->addressHodeTime = 0xF;
279 emmcNORSRAMConfig->readWriteTimingStruct->dataSetupTime = 0xFF;
280 emmcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime = 0xF;
281 emmcNORSRAMConfig->readWriteTimingStruct->clockDivision = 0xF;
282 emmcNORSRAMConfig->readWriteTimingStruct->dataLatency = 0xF;
283 emmcNORSRAMConfig->readWriteTimingStruct->accessMode = EMMC_ACCESS_MODE_A;
284 emmcNORSRAMConfig->writeTimingStruct->addressSetupTime = 0xF;
285 emmcNORSRAMConfig->writeTimingStruct->addressHodeTime = 0xF;
286 emmcNORSRAMConfig->writeTimingStruct->dataSetupTime = 0xFF;
287 emmcNORSRAMConfig->writeTimingStruct->busTurnaroundTime = 0xF;
288 emmcNORSRAMConfig->writeTimingStruct->clockDivision = 0xF;
289 emmcNORSRAMConfig->writeTimingStruct->dataLatency = 0xF;
290 emmcNORSRAMConfig->writeTimingStruct->accessMode = EMMC_ACCESS_MODE_A;
291
292 }
293
294 /*!
295 * @brief Fills each emmcNANDConfig member with its default value.
296 *
297 * @param emmcNANDConfig : Point to a EMMC_NANDConfig_T structure.
298 *
299 * @retval None
300 */
EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T * emmcNANDConfig)301 void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T *emmcNANDConfig)
302 {
303 /** Reset NAND Init structure parameters values */
304 emmcNANDConfig->bank = EMMC_BANK2_NAND;
305 emmcNANDConfig->waitFeature = EMMC_WAIT_FEATURE_DISABLE;
306 emmcNANDConfig->memoryDataWidth = EMMC_MEMORY_DATA_WIDTH_8BIT;
307 emmcNANDConfig->ECC = EMMC_ECC_DISABLE;
308 emmcNANDConfig->ECCPageSize = EMMC_ECC_PAGE_SIZE_BYTE_256;
309 emmcNANDConfig->TCLRSetupTime = 0x0;
310 emmcNANDConfig->TARSetupTime = 0x0;
311 emmcNANDConfig->commonSpaceTimingStruct->setupTime = 0xFC;
312 emmcNANDConfig->commonSpaceTimingStruct->waitSetupTime = 0xFC;
313 emmcNANDConfig->commonSpaceTimingStruct->holdSetupTime = 0xFC;
314 emmcNANDConfig->commonSpaceTimingStruct->HiZSetupTime = 0xFC;
315 emmcNANDConfig->attributeSpaceTimingStruct->setupTime = 0xFC;
316 emmcNANDConfig->attributeSpaceTimingStruct->waitSetupTime = 0xFC;
317 emmcNANDConfig->attributeSpaceTimingStruct->holdSetupTime = 0xFC;
318 emmcNANDConfig->attributeSpaceTimingStruct->HiZSetupTime = 0xFC;
319 }
320
321 /*!
322 * @brief Fills each emmcPCCardConfig member with its default value.
323 *
324 * @param emmcPCCardConfig : Point to a EMMC_PCCARDConfig_T structure.
325 *
326 * @retval None
327 */
EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T * emmcPCCardConfig)328 void EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T *emmcPCCardConfig)
329 {
330 /** Reset PCCARD Init structure parameters values */
331 emmcPCCardConfig->waitFeature = EMMC_WAIT_FEATURE_DISABLE;
332 emmcPCCardConfig->TCLRSetupTime = 0x0;
333 emmcPCCardConfig->TARSetupTime = 0x0;
334 emmcPCCardConfig->commonSpaceTimingStruct->setupTime = 0xFC;
335 emmcPCCardConfig->commonSpaceTimingStruct->waitSetupTime = 0xFC;
336 emmcPCCardConfig->commonSpaceTimingStruct->holdSetupTime = 0xFC;
337 emmcPCCardConfig->commonSpaceTimingStruct->HiZSetupTime = 0xFC;
338 emmcPCCardConfig->attributeSpaceTimingStruct->setupTime = 0xFC;
339 emmcPCCardConfig->attributeSpaceTimingStruct->waitSetupTime = 0xFC;
340 emmcPCCardConfig->attributeSpaceTimingStruct->holdSetupTime = 0xFC;
341 emmcPCCardConfig->attributeSpaceTimingStruct->HiZSetupTime = 0xFC;
342 emmcPCCardConfig->IOSpaceTimingStruct->setupTime = 0xFC;
343 emmcPCCardConfig->IOSpaceTimingStruct->waitSetupTime = 0xFC;
344 emmcPCCardConfig->IOSpaceTimingStruct->holdSetupTime = 0xFC;
345 emmcPCCardConfig->IOSpaceTimingStruct->HiZSetupTime = 0xFC;
346 }
347
348 /*!
349 * @brief Enables the specified NOR/SRAM Memory Bank.
350 *
351 * @param bank: Selects the EMMMC Bank.
352 * The parameter can be one of following values:
353 * @arg EMMC_BANK1_NORSRAM_1: EMMC Bank1 NOR/SRAM1
354 * @arg EMMC_BANK1_NORSRAM_2: EMMC Bank1 NOR/SRAM2
355 * @arg EMMC_BANK1_NORSRAM_3: EMMC Bank1 NOR/SRAM3
356 * @arg EMMC_BANK1_NORSRAM_4: EMMC Bank1 NOR/SRAM4
357 *
358 * @retval None
359 */
EMMC_EnableNORSRAM(EMMC_BANK1_NORSRAM_T bank)360 void EMMC_EnableNORSRAM(EMMC_BANK1_NORSRAM_T bank)
361 {
362 EMMC_Bank1->SNCTRL_T[bank] |= 0x00000001;
363 }
364
365 /*!
366 * @brief Disbles the specified NOR/SRAM Memory Bank.
367 *
368 * @param bank: Selects the EMMMC Bank.
369 * The parameter can be one of following values:
370 * @arg EMMC_BANK1_NORSRAM_1: EMMC Bank1 NOR/SRAM1
371 * @arg EMMC_BANK1_NORSRAM_2: EMMC Bank1 NOR/SRAM2
372 * @arg EMMC_BANK1_NORSRAM_3: EMMC Bank1 NOR/SRAM3
373 * @arg EMMC_BANK1_NORSRAM_4: EMMC Bank1 NOR/SRAM4
374 *
375 * @retval None
376 */
EMMC_DisableNORSRAM(EMMC_BANK1_NORSRAM_T bank)377 void EMMC_DisableNORSRAM(EMMC_BANK1_NORSRAM_T bank)
378 {
379 EMMC_Bank1->SNCTRL_T[bank] &= 0x000FFFFE;
380 }
381
382 /*!
383 * @brief Enables the specified NAND Memory Bank.
384 *
385 * @param bank: Selects the EMMMC Bank.
386 * The parameter can be one of following values:
387 * @arg EMMC_BANK2_NAND: FSMC Bank2 NAND
388 * @arg EMMC_BANK3_NAND: FSMC Bank3 NAND
389 *
390 * @retval None
391 */
EMMC_EnableNAND(EMMC_BANK_NAND_T bank)392 void EMMC_EnableNAND(EMMC_BANK_NAND_T bank)
393 {
394 if (bank == EMMC_BANK2_NAND)
395 {
396 EMMC_Bank2->CTRL2_B.MBKEN = BIT_SET;
397 }
398 else
399 {
400 EMMC_Bank3->CTRL3_B.MBKEN = BIT_SET;
401 }
402 }
403
404 /*!
405 * @brief Disbles the specified NAND Memory Bank.
406 *
407 * @param bank: Selects the EMMMC Bank.
408 * The parameter can be one of following values:
409 * @arg EMMC_BANK2_NAND: FSMC Bank2 NAND
410 * @arg EMMC_BANK3_NAND: FSMC Bank3 NAND
411 *
412 * @retval None
413 */
EMMC_DisableNAND(EMMC_BANK_NAND_T bank)414 void EMMC_DisableNAND(EMMC_BANK_NAND_T bank)
415 {
416 if (bank == EMMC_BANK2_NAND)
417 {
418 EMMC_Bank2->CTRL2_B.MBKEN = BIT_RESET;
419 }
420 else
421 {
422 EMMC_Bank3->CTRL3_B.MBKEN = BIT_RESET;
423 }
424 }
425
426 /*!
427 * @brief Enables the specified PC Card Memory Bank.
428 *
429 * @param None
430 *
431 * @retval None
432 */
EMMC_EnablePCCARD(void)433 void EMMC_EnablePCCARD(void)
434 {
435 EMMC_Bank4->CTRL4_B.MBKEN = BIT_SET;
436 }
437
438 /*!
439 * @brief Disables the specified PC Card Memory Bank.
440 *
441 * @param None
442 *
443 * @retval None
444 */
EMMC_DisablePCCARD(void)445 void EMMC_DisablePCCARD(void)
446 {
447 EMMC_Bank4->CTRL4_B.MBKEN = BIT_RESET;
448 }
449
450 /*!
451 * @brief Enbles the EMMC NAND ECC feature.
452 *
453 * @param bank: Selects the EMMMC Bank.
454 * The parameter can be one of following values:
455 * @arg EMMC_BANK2_NAND: FSMC Bank2 NAND
456 * @arg EMMC_BANK3_NAND: FSMC Bank3 NAND
457 *
458 * @retval None
459 */
EMMC_EnableNANDECC(EMMC_BANK_NAND_T bank)460 void EMMC_EnableNANDECC(EMMC_BANK_NAND_T bank)
461 {
462 if (bank == EMMC_BANK2_NAND)
463 {
464 EMMC_Bank2->CTRL2 |= 0x00000040;
465 }
466 else
467 {
468 EMMC_Bank3->CTRL3 |= 0x00000040;
469 }
470 }
471
472 /*!
473 * @brief Disbles or disables the EMMC NAND ECC feature.
474 *
475 * @param bank: Selects the EMMMC Bank.
476 * The parameter can be one of following values:
477 * @arg EMMC_BANK2_NAND: FSMC Bank2 NAND
478 * @arg EMMC_BANK3_NAND: FSMC Bank3 NAND
479 *
480 * @retval None
481 *
482 */
EMMC_DisableNANDECC(EMMC_BANK_NAND_T bank)483 void EMMC_DisableNANDECC(EMMC_BANK_NAND_T bank)
484 {
485 if (bank == EMMC_BANK2_NAND)
486 {
487 EMMC_Bank2->CTRL2 &= 0x000FFFBF;
488 }
489 else
490 {
491 EMMC_Bank3->CTRL3 &= 0x000FFFBF;
492 }
493 }
494
495 /*!
496 * @brief Read the error correction code register value.
497 *
498 * @param bank: Selects the EMMMC Bank.
499 * The parameter can be one of following values:
500 * @arg EMMC_BANK2_NAND: FSMC Bank2 NAND
501 * @arg EMMC_BANK3_NAND: FSMC Bank3 NAND
502 *
503 * @retval The value of Error Correction Code (ECC).
504 */
EMMC_ReadECC(EMMC_BANK_NAND_T bank)505 uint32_t EMMC_ReadECC(EMMC_BANK_NAND_T bank)
506 {
507 uint32_t eccval = 0x00000000;
508
509 if (bank == EMMC_BANK2_NAND)
510 {
511 eccval = EMMC_Bank2->ECCRS2;
512 }
513 else
514 {
515 eccval = EMMC_Bank3->ECCRS3;
516 }
517 return eccval;
518 }
519
520 /*!
521 * @brief Enables the specified EMMC interrupts.
522 *
523 * @param bank: Selects the EMMMC Bank.
524 * The parameter can be one of following values:
525 * @arg EMMC_BANK2_NAND : FSMC Bank2 NAND
526 * @arg EMMC_BANK3_NAND : FSMC Bank3 NAND
527 * @arg EMMC_BANK4_PCCARD: FSMC Bank4 PCCARD
528 *
529 * @param interrupt: Select the EMMC interrupt sources.
530 * This parameter can be any combination of the following values:
531 * @arg EMMC_INT_EDGE_RISING : Rising edge detection interrupt.
532 * @arg EMMC_INT_LEVEL_HIGH : High level detection interrupt.
533 * @arg EMMC_INT_EDGE_FALLING: Falling edge detection interrupt.
534 *
535 * @retval None
536 */
EMMC_EnableInterrupt(EMMC_BANK_NAND_T bank,uint32_t interrupt)537 void EMMC_EnableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt)
538 {
539 if (bank == EMMC_BANK2_NAND)
540 {
541 EMMC_Bank2->STSINT2 |= interrupt;
542 }
543 else if (bank == EMMC_BANK3_NAND)
544 {
545 EMMC_Bank3->STSINT3 |= interrupt;
546 }
547 else
548 {
549 EMMC_Bank4->STSINT4 |= interrupt;
550 }
551 }
552
553 /*!
554 * @brief Enables the specified EMMC interrupts.
555 *
556 * @param bank: Selects the EMMMC Bank.
557 * The parameter can be one of following values:
558 * @arg EMMC_BANK2_NAND : FSMC Bank2 NAND
559 * @arg EMMC_BANK3_NAND : FSMC Bank3 NAND
560 * @arg EMMC_BANK4_PCCARD: FSMC Bank4 PCCARD
561 *
562 * @param interrupt: Select the EMMC interrupt sources.
563 * This parameter can be any combination of the following values:
564 * @arg EMMC_INT_EDGE_RISING : Rising edge detection interrupt.
565 * @arg EMMC_INT_LEVEL_HIGH : High level edge detection interrupt.
566 * @arg EMMC_INT_EDGE_FALLING: Falling edge detection interrupt.
567 *
568 * @retval None
569 */
EMMC_DisableInterrupt(EMMC_BANK_NAND_T bank,uint32_t interrupt)570 void EMMC_DisableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt)
571 {
572 if (bank == EMMC_BANK2_NAND)
573 {
574 EMMC_Bank2->STSINT2 &= ~interrupt;
575 }
576 else if (bank == EMMC_BANK3_NAND)
577 {
578 EMMC_Bank3->STSINT3 &= ~interrupt;
579 }
580 else
581 {
582 EMMC_Bank4->STSINT4 &= ~interrupt;
583 }
584 }
585
586 /*!
587 * @brief Read the status of specified EMMC flag.
588 *
589 * @param bank: Selects the EMMMC Bank.
590 * The parameter can be one of following values:
591 * @arg EMMC_BANK2_NAND : FSMC Bank2 NAND
592 * @arg EMMC_BANK3_NAND : FSMC Bank3 NAND
593 * @arg EMMC_BANK4_PCCARD: FSMC Bank4 PCCARD
594 *
595 * @param flag: Select the EMMC interrupt sources.
596 * This parameter can be one of the following values:
597 * @arg EMMC_FLAG_EDGE_RISING : Rising egde detection Flag.
598 * @arg EMMC_FLAG_LEVEL_HIGH : High level detection Flag.
599 * @arg EMMC_FLAG_EDGE_FALLING: Falling egde detection Flag.
600 * @arg EMMC_FLAG_FIFO_EMPTY : FIFO empty Flag.
601 *
602 * @retval SET or RESET
603 *
604 */
EMMC_ReadStatusFlag(EMMC_BANK_NAND_T bank,EMMC_FLAG_T flag)605 uint8_t EMMC_ReadStatusFlag(EMMC_BANK_NAND_T bank, EMMC_FLAG_T flag)
606 {
607 uint32_t tmpsr = 0x00000000;
608
609 if (bank == EMMC_BANK2_NAND)
610 {
611 tmpsr = EMMC_Bank2->STSINT2;
612 }
613 else if (bank == EMMC_BANK3_NAND)
614 {
615 tmpsr = EMMC_Bank3->STSINT3;
616 }
617 else
618 {
619 tmpsr = EMMC_Bank4->STSINT4;
620 }
621 /** Get the flag status */
622 if ((tmpsr & flag) != RESET)
623 {
624 return SET;
625 }
626 else
627 {
628 return RESET;
629 }
630 }
631
632 /*!
633 * @brief Clears the EMMC's pending flags.
634 *
635 * @param bank: Selects the EMMMC Bank.
636 * The parameter can be one of following values:
637 * @arg EMMC_BANK2_NAND : FSMC Bank2 NAND
638 * @arg EMMC_BANK3_NAND : FSMC Bank3 NAND
639 * @arg EMMC_BANK4_PCCARD: FSMC Bank4 PCCARD
640 *
641 * @param flag: Select the EMMC interrupt sources.
642 * This parameter can be any combination of the following values:
643 * @arg EMMC_FLAG_EDGE_RISING : Rising egde detection Flag.
644 * @arg EMMC_FLAG_LEVEL_HIGH : High level detection Flag.
645 * @arg EMMC_FLAG_EDGE_FALLING: Falling egde detection Flag.
646 *
647 * @retval None
648 */
EMMC_ClearStatusFlag(EMMC_BANK_NAND_T bank,uint32_t flag)649 void EMMC_ClearStatusFlag(EMMC_BANK_NAND_T bank, uint32_t flag)
650 {
651 if (bank == EMMC_BANK2_NAND)
652 {
653 EMMC_Bank2->STSINT2 &= ~flag;
654 }
655 else if (bank == EMMC_BANK3_NAND)
656 {
657 EMMC_Bank3->STSINT3 &= ~flag;
658 }
659 else
660 {
661 EMMC_Bank4->STSINT4 &= ~flag;
662 }
663 }
664
665 /*!
666 * @brief Read the specified EMMC interrupt has occurred or not.
667 *
668 * @param bank: Selects the EMMMC Bank.
669 * The parameter can be one of following values:
670 * @arg EMMC_BANK2_NAND : FSMC Bank2 NAND
671 * @arg EMMC_BANK3_NAND : FSMC Bank3 NAND
672 * @arg EMMC_BANK4_PCCARD: FSMC Bank4 PCCARD
673 *
674 * @param interrupt: Select the EMMC interrupt source.
675 * This parameter can be one of the following values:
676 * @arg EMMC_INT_EDGE_RISING : Rising edge detection interrupt.
677 * @arg EMMC_INT_LEVEL_HIGH : High level edge detection interrupt.
678 * @arg EMMC_INT_EDGE_FALLING: Falling edge detection interrupt.
679 *
680 * @retval The status of specified EMMC interrupt source.
681 */
EMMC_ReadIntFlag(EMMC_BANK_NAND_T bank,EMMC_INT_T flag)682 uint8_t EMMC_ReadIntFlag(EMMC_BANK_NAND_T bank, EMMC_INT_T flag)
683 {
684 uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
685
686 if (bank == EMMC_BANK2_NAND)
687 {
688 tmpsr = EMMC_Bank2->STSINT2;
689 }
690 else if (bank == EMMC_BANK3_NAND)
691 {
692 tmpsr = EMMC_Bank3->STSINT3;
693 }
694 else
695 {
696 tmpsr = EMMC_Bank4->STSINT4;
697 }
698
699 itstatus = tmpsr & flag;
700 itenable = tmpsr & (flag >> 3);
701
702 if ((itstatus != RESET) && (itenable != RESET))
703 {
704 return SET;
705 }
706 else
707 {
708 return RESET;
709 }
710 }
711
712 /*!
713 * @brief Clears the EMMC's interrupt Flag.
714 *
715 * @param bank: Selects the EMMMC Bank.
716 * The parameter can be one of following values:
717 * @arg EMMC_BANK2_NAND : FSMC Bank2 NAND
718 * @arg EMMC_BANK3_NAND : FSMC Bank3 NAND
719 * @arg EMMC_BANK4_PCCARD: FSMC Bank4 PCCARD
720 *
721 * @param interrupt: Select the EMMC interrupt sources.
722 * This parameter can be any combination of the following values:
723 * @arg EMMC_INT_EDGE_RISING : Rising edge detection interrupt.
724 * @arg EMMC_INT_LEVEL_HIGH : High level edge detection interrupt.
725 * @arg EMMC_INT_EDGE_FALLING: Falling edge detection interrupt.
726 *
727 * @retval None
728 */
EMMC_ClearIntFlag(EMMC_BANK_NAND_T bank,uint32_t flag)729 void EMMC_ClearIntFlag(EMMC_BANK_NAND_T bank, uint32_t flag)
730 {
731 if (bank == EMMC_BANK2_NAND)
732 {
733 EMMC_Bank2->STSINT2 &= ~(flag >> 3);
734 }
735 else if (bank == EMMC_BANK3_NAND)
736 {
737 EMMC_Bank3->STSINT3 &= ~(flag >> 3);
738 }
739 else
740 {
741 EMMC_Bank4->STSINT4 &= ~(flag >> 3);
742 }
743 }
744
745 /**@} end of group EMMC_Fuctions*/
746 /**@} end of group EMMC_Driver*/
747 /**@} end of group Peripherals_Library*/
748