1 /*! 2 * @file apm32f10x_sdio.c 3 * 4 * @brief This file provides all the SDIO firmware functions 5 * 6 * @version V1.0.4 7 * 8 * @date 2022-12-01 9 * 10 * @attention 11 * 12 * Copyright (C) 2020-2022 Geehy Semiconductor 13 * 14 * You may not use this file except in compliance with the 15 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). 16 * 17 * The program is only for reference, which is distributed in the hope 18 * that it will be useful and instructional for customers to develop 19 * their software. Unless required by applicable law or agreed to in 20 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT 21 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions 23 * and limitations under the License. 24 */ 25 26 #include "apm32f10x_sdio.h" 27 #include "apm32f10x_rcm.h" 28 29 /** @addtogroup APM32F10x_StdPeriphDriver 30 @{ 31 */ 32 33 /** @addtogroup SDIO_Driver SDIO Driver 34 * @brief SDIO driver modules 35 @{ 36 */ 37 38 /** @defgroup SDIO_Functions Functions 39 @{ 40 */ 41 42 /*! 43 * @brief Reset sdio peripheral registers to their default reset values 44 * 45 * @param None 46 * 47 * @retval None 48 */ SDIO_Reset(void)49void SDIO_Reset(void) 50 { 51 SDIO->PWRCTRL = 0x00000000; 52 SDIO->CLKCTRL = 0x00000000; 53 SDIO->ARG = 0x00000000; 54 SDIO->CMD = 0x00000000; 55 SDIO->DATATIME = 0x00000000; 56 SDIO->DATALEN = 0x00000000; 57 SDIO->DCTRL = 0x00000000; 58 SDIO->ICF = 0x00C007FF; 59 SDIO->MASK = 0x00000000; 60 } 61 62 /*! 63 * @brief Configures the SDIO peripheral according to the specified parameters in the sdioConfig 64 * 65 * @param sdioConfig: pointer to a SDIO_Config_T structure 66 * 67 * @retval None 68 */ SDIO_Config(SDIO_Config_T * sdioConfig)69void SDIO_Config(SDIO_Config_T* sdioConfig) 70 { 71 uint32_t tmp = 0; 72 73 tmp = SDIO->CLKCTRL; 74 tmp &= 0xFFFF8100; 75 76 tmp |= (sdioConfig->clockDiv | sdioConfig->clockPowerSave | sdioConfig->clockBypass | sdioConfig->busWide | 77 sdioConfig->clockEdge | sdioConfig->hardwareFlowControl); 78 79 SDIO->CLKCTRL = tmp; 80 } 81 82 /*! 83 * @brief Fills each SDIO_Config_T member with its default value 84 * 85 * @param sdioConfig: pointer to a SDIO_Config_T structure 86 * 87 * @retval None 88 */ SDIO_ConfigStructInit(SDIO_Config_T * sdioConfig)89void SDIO_ConfigStructInit(SDIO_Config_T* sdioConfig) 90 { 91 sdioConfig->clockDiv = 0x00; 92 sdioConfig->clockEdge = SDIO_CLOCK_EDGE_RISING; 93 sdioConfig->clockBypass = SDIO_CLOCK_BYPASS_DISABLE; 94 sdioConfig->clockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; 95 sdioConfig->busWide = SDIO_BUS_WIDE_1B; 96 sdioConfig->hardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; 97 } 98 99 /*! 100 * @brief Enable the SDIO clock 101 * 102 * @param None 103 * 104 * @retval None 105 */ SDIO_EnableClock(void)106void SDIO_EnableClock(void) 107 { 108 *(__IO uint32_t*) CLKCTRL_CLKEN_BB = (uint32_t)SET; 109 } 110 111 /*! 112 * @brief Disable the SDIO clock 113 * 114 * @param None 115 * 116 * @retval None 117 */ SDIO_DisableClock(void)118void SDIO_DisableClock(void) 119 { 120 *(__IO uint32_t*) CLKCTRL_CLKEN_BB = (uint32_t)RESET; 121 } 122 123 /*! 124 * @brief Set the power status of the controller 125 * 126 * @param powerState: new state of the Power state 127 * The parameter can be one of following values: 128 * @arg SDIO_POWER_STATE_OFF 129 * @arg SDIO_POWER_STATE_ON 130 * @retval None 131 */ SDIO_ConfigPowerState(SDIO_POWER_STATE_T powerState)132void SDIO_ConfigPowerState(SDIO_POWER_STATE_T powerState) 133 { 134 SDIO->PWRCTRL &= 0xFFFFFFFC; 135 SDIO->PWRCTRL |= powerState; 136 } 137 138 /*! 139 * @brief Read the SDIO power state 140 * 141 * @param None 142 * 143 * @retval The new state SDIO power 144 * 145 * @note 0x00:Power OFF, 0x02:Power UP, 0x03:Power ON 146 */ SDIO_ReadPowerState(void)147uint32_t SDIO_ReadPowerState(void) 148 { 149 return (SDIO->PWRCTRL & (~0xFFFFFFFC)); 150 } 151 152 /*! 153 * @brief Enable the SDIO DMA request 154 * 155 * @param None 156 * 157 * @retval None 158 */ SDIO_EnableDMA(void)159void SDIO_EnableDMA(void) 160 { 161 *(__IO uint32_t*) DCTRL_DMAEN_BB = (uint32_t)SET; 162 } 163 164 /*! 165 * @brief Disable the SDIO DMA request 166 * 167 * @param None 168 * 169 * @retval None 170 */ SDIO_DisableDMA(void)171void SDIO_DisableDMA(void) 172 { 173 *(__IO uint32_t*) DCTRL_DMAEN_BB = (uint32_t)RESET; 174 } 175 176 /*! 177 * @brief Configures the SDIO Command and send the command 178 * 179 * @param cmdConfig: pointer to a SDIO_CmdConfig_T structure 180 * 181 * @retval None 182 * 183 */ SDIO_TxCommand(SDIO_CmdConfig_T * cmdConfig)184void SDIO_TxCommand(SDIO_CmdConfig_T* cmdConfig) 185 { 186 uint32_t tmpreg = 0; 187 188 SDIO->ARG = cmdConfig->argument; 189 tmpreg = SDIO->CMD; 190 tmpreg &= 0xFFFFF800; 191 tmpreg |= (uint32_t)cmdConfig->cmdIndex | cmdConfig->response 192 | cmdConfig->wait | cmdConfig->CPSM; 193 SDIO->CMD = tmpreg; 194 } 195 196 /*! 197 * @brief Fills each SDIO_CMD_ConfigStruct_T member with its default value 198 * 199 * @param cmdConfig: pointer to a SDIO_CmdConfig_T structure 200 * 201 * @retval None 202 * 203 */ SDIO_TxCommandStructInit(SDIO_CmdConfig_T * cmdConfig)204void SDIO_TxCommandStructInit(SDIO_CmdConfig_T* cmdConfig) 205 { 206 cmdConfig->argument = 0x00; 207 cmdConfig->cmdIndex = 0x00; 208 cmdConfig->response = SDIO_RESPONSE_NO; 209 cmdConfig->wait = SDIO_WAIT_NO; 210 cmdConfig->CPSM = SDIO_CPSM_DISABLE; 211 } 212 213 /*! 214 * @brief Read the SDIO command response 215 * 216 * @param None 217 * 218 * @retval The command index of the last command response received 219 * 220 */ SDIO_ReadCommandResponse(void)221uint8_t SDIO_ReadCommandResponse(void) 222 { 223 return (uint8_t)(SDIO->CMDRES); 224 } 225 226 /*! 227 * @brief Read the SDIO response 228 * 229 * @param res: Specifies the SDIO response register 230 * The parameter can be one of following values: 231 * @arg SDIO_RES1: Response Register 1 232 * @arg SDIO_RES2: Response Register 2 233 * @arg SDIO_RES3: Response Register 3 234 * @arg SDIO_RES4: Response Register 4 235 * 236 * @retval The Corresponding response register value 237 */ SDIO_ReadResponse(SDIO_RES_T res)238uint32_t SDIO_ReadResponse(SDIO_RES_T res) 239 { 240 __IO uint32_t tmp = 0; 241 242 tmp = ((uint32_t)(SDIO_BASE + 0x14)) + res; 243 244 return (*(__IO uint32_t*) tmp); 245 } 246 247 /*! 248 * @brief Configures the SDIO Dataaccording to the specified parameters in the dataConfig 249 * 250 * @param dataConfig: pointer to a SDIO_DataConfig_T structure 251 * 252 * @retval None 253 */ SDIO_ConfigData(SDIO_DataConfig_T * dataConfig)254void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig) 255 { 256 uint32_t tmpreg = 0; 257 258 SDIO->DATATIME = dataConfig->dataTimeOut; 259 260 SDIO->DATALEN = dataConfig->dataLength; 261 262 tmpreg = SDIO->DCTRL; 263 264 tmpreg &= 0xFFFFFF08; 265 266 tmpreg |= (uint32_t)dataConfig->dataBlockSize | dataConfig->transferDir 267 | dataConfig->transferMode | dataConfig->DPSM; 268 269 SDIO->DCTRL = tmpreg; 270 } 271 272 /*! 273 * @brief Fills each SDIO_DataConfig_T member with its default value 274 * 275 * @param dataConfig: pointer to a SDIO_DataConfig_T structure 276 * 277 * @retval None 278 */ SDIO_ConfigDataStructInit(SDIO_DataConfig_T * dataConfig)279void SDIO_ConfigDataStructInit(SDIO_DataConfig_T* dataConfig) 280 { 281 dataConfig->dataTimeOut = 0xFFFFFFFF; 282 dataConfig->dataLength = 0x00; 283 dataConfig->dataBlockSize = SDIO_DATA_BLOCKSIZE_1B; 284 dataConfig->transferDir = SDIO_TRANSFER_DIR_TO_CARD; 285 dataConfig->transferMode = SDIO_TRANSFER_MODE_BLOCK; 286 dataConfig->DPSM = SDIO_DPSM_DISABLE; 287 } 288 289 /*! 290 * @brief Read the SDIO Data counter 291 * 292 * @param None 293 * 294 * @retval The SDIO Data counter value 295 */ SDIO_ReadDataCounter(void)296uint32_t SDIO_ReadDataCounter(void) 297 { 298 return SDIO->DCNT; 299 } 300 301 /*! 302 * @brief Write the SDIO Data 303 * 304 * @param Data: Write 32-bit data 305 * 306 * @retval None 307 */ SDIO_WriteData(uint32_t data)308void SDIO_WriteData(uint32_t data) 309 { 310 SDIO->FIFODATA = data; 311 } 312 313 /*! 314 * @brief Read the SDIO Data 315 * 316 * @param None 317 * 318 * @retval The SDIO FIFO Data value 319 */ SDIO_ReadData(void)320uint32_t SDIO_ReadData(void) 321 { 322 return SDIO->FIFODATA; 323 } 324 325 /*! 326 * @brief Read the SDIO FIFO count value 327 * 328 * @param None 329 * 330 * @retval The SDIO FIFO count value 331 */ SDIO_ReadFIFOCount(void)332uint32_t SDIO_ReadFIFOCount(void) 333 { 334 return SDIO->FIFOCNT; 335 } 336 337 /*! 338 * @brief Enable SDIO start read wait 339 * 340 * @param None 341 * 342 * @retval None 343 */ SDIO_EnableStartReadWait(void)344void SDIO_EnableStartReadWait(void) 345 { 346 *(__IO uint32_t*) DCTRL_RWSTR_BB = (uint32_t) SET; 347 } 348 349 /*! 350 * @brief Disable SDIO start read wait 351 * 352 * @param None 353 * 354 * @retval None 355 */ SDIO_DisableStopReadWait(void)356void SDIO_DisableStopReadWait(void) 357 { 358 *(__IO uint32_t*) DCTRL_RWSTR_BB = (uint32_t) RESET; 359 } 360 361 /*! 362 * @brief Enable SDIO stop read wait 363 * 364 * @param None 365 * 366 * @retval None 367 */ SDIO_EnableStopReadWait(void)368void SDIO_EnableStopReadWait(void) 369 { 370 *(__IO uint32_t*) DCTRL_RWSTOP_BB = (uint32_t) SET; 371 } 372 373 /*! 374 * @brief Disable SDIO stop read wait 375 * 376 * @param None 377 * 378 * @retval None 379 */ SDIO_DisableStartReadWait(void)380void SDIO_DisableStartReadWait(void) 381 { 382 *(__IO uint32_t*) DCTRL_RWSTOP_BB = (uint32_t) RESET; 383 } 384 385 /*! 386 * @brief Set the read wait interval 387 * 388 * @param readWaitMode: SDIO read Wait Mode 389 * The parameter can be one of following values: 390 * @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDIOCLK 391 * @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDIO_DATA2 392 * 393 * @retval None 394 * 395 */ SDIO_ConfigSDIOReadWaitMode(SDIO_READ_WAIT_MODE_T readWaitMode)396void SDIO_ConfigSDIOReadWaitMode(SDIO_READ_WAIT_MODE_T readWaitMode) 397 { 398 *(__IO uint32_t*) DCTRL_RDWAIT_BB = readWaitMode; 399 } 400 /*! 401 * @brief Enable SDIO SD I/O Mode Operation 402 * 403 * @param None 404 * 405 * @retval None 406 */ SDIO_EnableSDIO(void)407void SDIO_EnableSDIO(void) 408 { 409 *(__IO uint32_t*) DCTRL_SDIOF_BB = (uint32_t)SET; 410 } 411 412 /*! 413 * @brief Disable SDIO SD I/O Mode Operation 414 * 415 * @param None 416 * 417 * @retval None 418 */ SDIO_DisableSDIO(void)419void SDIO_DisableSDIO(void) 420 { 421 *(__IO uint32_t*) DCTRL_SDIOF_BB = (uint32_t)RESET; 422 } 423 424 /*! 425 * @brief Enable SDIO SD I/O Mode suspend command sending 426 * 427 * @param None 428 * 429 * @retval None 430 */ SDIO_EnableTxSDIOSuspend(void)431void SDIO_EnableTxSDIOSuspend(void) 432 { 433 *(__IO uint32_t*) CMD_SDIOSC_BB = (uint32_t)SET; 434 } 435 436 /*! 437 * @brief Disable SDIO SD I/O Mode suspend command sending 438 * 439 * @param None 440 * 441 * @retval None 442 */ SDIO_DisableTxSDIOSuspend(void)443void SDIO_DisableTxSDIOSuspend(void) 444 { 445 *(__IO uint32_t*) CMD_SDIOSC_BB = (uint32_t)RESET; 446 } 447 448 /*! 449 * @brief Enable the command completion signal 450 * 451 * @param None 452 * 453 * @retval None 454 */ SDIO_EnableCommandCompletion(void)455void SDIO_EnableCommandCompletion(void) 456 { 457 *(__IO uint32_t*) CMD_CMDCPEN_BB = (uint32_t)SET; 458 } 459 460 /*! 461 * @brief Disable the command completion signal 462 * 463 * @param None 464 * 465 * @retval None 466 */ SDIO_DisableCommandCompletion(void)467void SDIO_DisableCommandCompletion(void) 468 { 469 *(__IO uint32_t*) CMD_CMDCPEN_BB = (uint32_t)RESET; 470 } 471 472 /*! 473 * @brief Enable the CE-ATA interrupt 474 * 475 * @param None 476 * 477 * @retval None 478 */ SDIO_EnableCEATAInterrupt(void)479void SDIO_EnableCEATAInterrupt(void) 480 { 481 *(__IO uint32_t*) CMD_INTEN_BB = (uint32_t)((~((uint32_t)SET)) & ((uint32_t)0x1)); 482 } 483 484 /*! 485 * @brief Disable the CE-ATA interrupt 486 * 487 * @param None 488 * 489 * @retval None 490 */ SDIO_DisableCEATAInterrupt(void)491void SDIO_DisableCEATAInterrupt(void) 492 { 493 *(__IO uint32_t*) CMD_INTEN_BB = (uint32_t)((~((uint32_t)RESET)) & ((uint32_t)0x1)); 494 } 495 496 /*! 497 * @brief Enable Sends CE-ATA command 498 * 499 * @param None 500 * 501 * @retval None 502 */ SDIO_EnableTxCEATA(void)503void SDIO_EnableTxCEATA(void) 504 { 505 *(__IO uint32_t*) CMD_ATACMD_BB = (uint32_t)SET; 506 } 507 508 /*! 509 * @brief Disable Sends CE-ATA command 510 * 511 * @param None 512 * 513 * @retval None 514 */ SDIO_DisableTxCEATA(void)515void SDIO_DisableTxCEATA(void) 516 { 517 *(__IO uint32_t*) CMD_ATACMD_BB = (uint32_t)RESET; 518 } 519 520 /*! 521 * @brief Enable the specified SDIO interrupt 522 * 523 * @param interrupt: Select the SDIO interrupt source 524 * The parameter can be any combination of following values: 525 * @arg SDIO_INT_COMRESP: Command response received (CRC check failed) interrupt 526 * @arg SDIO_INT_DBDR: Data block sent/received (CRC check failed) interrupt 527 * @arg SDIO_INT_CMDRESTO: Command response timeout interrupt 528 * @arg SDIO_INT_DATATO: Data timeout interrupt 529 * @arg SDIO_INT_TXUDRER: Transmit FIFO underrun error interrupt 530 * @arg SDIO_INT_RXOVRER: Received FIFO overrun error interrupt 531 * @arg SDIO_INT_CMDRES: Command response received (CRC check passed) interrupt 532 * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt 533 * @arg SDIO_INT_DATAEND: Data end (data counter is zero) interrupt 534 * @arg SDIO_INT_SBE: Start bit not detected on all data signals in wide bus mode interrupt 535 * @arg SDIO_INT_DBCP: Data block sent/received (CRC check passed) interrupt 536 * @arg SDIO_INT_CMDACT: Command transfer in progress interrupt 537 * @arg SDIO_INT_TXACT: Data transmit in progress interrupt 538 * @arg SDIO_INT_RXACT: Data receive in progress interrupt 539 * @arg SDIO_INT_TXFHF: Transmit FIFO Half Empty interrupt 540 * @arg SDIO_INT_RXFHF: Receive FIFO Half Full interrupt 541 * @arg SDIO_INT_TXFF: Transmit FIFO full interrupt 542 * @arg SDIO_INT_RXFF: Receive FIFO full interrupt 543 * @arg SDIO_INT_TXFE: Transmit FIFO empty interrupt 544 * @arg SDIO_INT_RXFE: Receive FIFO empty interrupt 545 * @arg SDIO_INT_TXDA: Data available in transmit FIFO interrupt 546 * @arg SDIO_INT_RXDA: Data available in receive FIFO interrupt 547 * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt 548 * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt 549 * @retval None 550 */ SDIO_EnableInterrupt(uint32_t interrupt)551void SDIO_EnableInterrupt(uint32_t interrupt) 552 { 553 SDIO->MASK |= interrupt; 554 } 555 556 /*! 557 * @brief Disable the specified SDIO interrupt 558 * 559 * @param interrupt: Select the SDIO interrupt source 560 * The parameter can be any combination of following values: 561 * @arg SDIO_INT_COMRESP: Command response received (CRC check failed) interrupt 562 * @arg SDIO_INT_DBDR: Data block sent/received (CRC check failed) interrupt 563 * @arg SDIO_INT_CMDRESTO: Command response timeout interrupt 564 * @arg SDIO_INT_DATATO: Data timeout interrupt 565 * @arg SDIO_INT_TXUDRER: Transmit FIFO underrun error interrupt 566 * @arg SDIO_INT_RXOVRER: Received FIFO overrun error interrupt 567 * @arg SDIO_INT_CMDRES: Command response received (CRC check passed) interrupt 568 * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt 569 * @arg SDIO_INT_DATAEND: Data end (data counter is zero) interrupt 570 * @arg SDIO_INT_SBE: Start bit not detected on all data signals in wide bus mode interrupt 571 * @arg SDIO_INT_DBCP: Data block sent/received (CRC check passed) interrupt 572 * @arg SDIO_INT_CMDACT: Command transfer in progress interrupt 573 * @arg SDIO_INT_TXACT: Data transmit in progress interrupt 574 * @arg SDIO_INT_RXACT: Data receive in progress interrupt 575 * @arg SDIO_INT_TXFHF: Transmit FIFO Half Empty interrupt 576 * @arg SDIO_INT_RXFHF: Receive FIFO Half Full interrupt 577 * @arg SDIO_INT_TXFF: Transmit FIFO full interrupt 578 * @arg SDIO_INT_RXFF: Receive FIFO full interrupt 579 * @arg SDIO_INT_TXFE: Transmit FIFO empty interrupt 580 * @arg SDIO_INT_RXFE: Receive FIFO empty interrupt 581 * @arg SDIO_INT_TXDA: Data available in transmit FIFO interrupt 582 * @arg SDIO_INT_RXDA: Data available in receive FIFO interrupt 583 * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt 584 * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt 585 * @retval None 586 */ SDIO_DisableInterrupt(uint32_t interrupt)587void SDIO_DisableInterrupt(uint32_t interrupt) 588 { 589 SDIO->MASK &= ~interrupt; 590 } 591 592 /*! 593 * @brief Read the specified SDIO flag 594 * 595 * @param flag: Select the flag to read 596 * The parameter can be one of following values: 597 * @arg SDIO_FLAG_COMRESP: Command response received (CRC check failed) flag 598 * @arg SDIO_FLAG_DBDR: Data block sent/received (CRC check failed) flag 599 * @arg SDIO_FLAG_CMDRESTO: Command response timeout flag 600 * @arg SDIO_FLAG_DATATO: Data timeout flag 601 * @arg SDIO_FLAG_TXUDRER: Transmit FIFO underrun error flag 602 * @arg SDIO_FLAG_RXOVRER: Received FIFO overrun error flag 603 * @arg SDIO_FLAG_CMDRES: Command response received (CRC check passed) flag 604 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) flag 605 * @arg SDIO_FLAG_DATAEND: Data end (data counter is zero) flag 606 * @arg SDIO_FLAG_SBE: Start bit not detected on all data signals in wide bus mode flag 607 * @arg SDIO_FLAG_DBCP: Data block sent/received (CRC check passed) flag 608 * @arg SDIO_FLAG_CMDACT: Command transfer in progress flag 609 * @arg SDIO_FLAG_TXACT: Data transmit in progress flag 610 * @arg SDIO_FLAG_RXACT: Data receive in progress flag 611 * @arg SDIO_FLAG_TXFHF: Transmit FIFO Half Empty flag 612 * @arg SDIO_FLAG_RXFHF: Receive FIFO Half Full flag 613 * @arg SDIO_FLAG_TXFF: Transmit FIFO full flag 614 * @arg SDIO_FLAG_RXFF: Receive FIFO full flag 615 * @arg SDIO_FLAG_TXFE: Transmit FIFO empty flag 616 * @arg SDIO_FLAG_RXFE: Receive FIFO empty flag 617 * @arg SDIO_FLAG_TXDA: Data available in transmit FIFO flag 618 * @arg SDIO_FLAG_RXDA: Data available in receive FIFO flag 619 * @arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag 620 * @arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received for CMD61 flag 621 * 622 * @retval SET or RESET 623 */ SDIO_ReadStatusFlag(SDIO_FLAG_T flag)624uint8_t SDIO_ReadStatusFlag(SDIO_FLAG_T flag) 625 { 626 return (SDIO->STS & flag) ? SET : RESET; 627 } 628 629 /*! 630 * @brief Clear the specified SDIO flag 631 * 632 * @param flag: Select the flag to clear 633 * The parameter can be any combination of following values: 634 * @arg SDIO_FLAG_COMRESP: Command response received (CRC check failed) flag 635 * @arg SDIO_FLAG_DBDR: Data block sent/received (CRC check failed) flag 636 * @arg SDIO_FLAG_CMDRESTO: Command response timeout flag 637 * @arg SDIO_FLAG_DATATO: Data timeout flag 638 * @arg SDIO_FLAG_TXUDRER: Transmit FIFO underrun error flag 639 * @arg SDIO_FLAG_RXOVRER: Received FIFO overrun error flag 640 * @arg SDIO_FLAG_CMDRES: Command response received (CRC check passed) flag 641 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) flag 642 * @arg SDIO_FLAG_DATAEND: Data end (data counter is zero) flag 643 * @arg SDIO_FLAG_SBE: Start bit not detected on all data signals in wide bus mode flag 644 * @arg SDIO_FLAG_DBCP: Data block sent/received (CRC check passed) flag 645 * @arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag 646 * @arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received for CMD61 flag 647 * 648 * @retval None 649 */ SDIO_ClearStatusFlag(uint32_t flag)650void SDIO_ClearStatusFlag(uint32_t flag) 651 { 652 SDIO->ICF = flag; 653 } 654 655 /*! 656 * @brief Read the specified SDIO Interrupt flag 657 * 658 * @param flag: Select the SDIO interrupt source 659 * The parameter can be one of following values: 660 * @arg SDIO_INT_COMRESP: Command response received (CRC check failed) interrupt 661 * @arg SDIO_INT_DBDR: Data block sent/received (CRC check failed) interrupt 662 * @arg SDIO_INT_CMDRESTO: Command response timeout interrupt 663 * @arg SDIO_INT_DATATO: Data timeout interrupt 664 * @arg SDIO_INT_TXUDRER: Transmit FIFO underrun error interrupt 665 * @arg SDIO_INT_RXOVRER: Received FIFO overrun error interrupt 666 * @arg SDIO_INT_CMDRES: Command response received (CRC check passed) interrupt 667 * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt 668 * @arg SDIO_INT_DATAEND: Data end (data counter is zero) interrupt 669 * @arg SDIO_INT_SBE: Start bit not detected on all data signals in wide bus mode interrupt 670 * @arg SDIO_INT_DBCP: Data block sent/received (CRC check passed) interrupt 671 * @arg SDIO_INT_CMDACT: Command transfer in progress interrupt 672 * @arg SDIO_INT_TXACT: Data transmit in progress interrupt 673 * @arg SDIO_INT_RXACT: Data receive in progress interrupt 674 * @arg SDIO_INT_TXFHF: Transmit FIFO Half Empty interrupt 675 * @arg SDIO_INT_RXFHF: Receive FIFO Half Full interrupt 676 * @arg SDIO_INT_TXFF: Transmit FIFO full interrupt 677 * @arg SDIO_INT_RXFF: Receive FIFO full interrupt 678 * @arg SDIO_INT_TXFE: Transmit FIFO empty interrupt 679 * @arg SDIO_INT_RXFE: Receive FIFO empty interrupt 680 * @arg SDIO_INT_TXDA: Data available in transmit FIFO interrupt 681 * @arg SDIO_INT_RXDA: Data available in receive FIFO interrupt 682 * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt 683 * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt 684 * 685 * @retval SET or RESET 686 */ SDIO_ReadIntFlag(SDIO_INT_T flag)687uint8_t SDIO_ReadIntFlag(SDIO_INT_T flag) 688 { 689 uint32_t intEnable; 690 uint32_t intStatus; 691 692 intEnable = (uint32_t)(SDIO->MASK & flag); 693 intStatus = (uint32_t)(SDIO->STS & flag); 694 695 if (intEnable && intStatus) 696 { 697 return SET; 698 } 699 700 return RESET; 701 } 702 703 /*! 704 * @brief Clear the specified SDIO Interrupt pending bits 705 * 706 * @param flag: Select the SDIO interrupt source 707 * The parameter can be any combination of following values: 708 * @arg SDIO_INT_COMRESP: Command response received (CRC check failed) interrupt 709 * @arg SDIO_INT_DBDR: Data block sent/received (CRC check failed) interrupt 710 * @arg SDIO_INT_CMDRESTO: Command response timeout interrupt 711 * @arg SDIO_INT_DATATO: Data timeout interrupt 712 * @arg SDIO_INT_TXUDRER: Transmit FIFO underrun error interrupt 713 * @arg SDIO_INT_RXOVRER: Received FIFO overrun error interrupt 714 * @arg SDIO_INT_CMDRES: Command response received (CRC check passed) interrupt 715 * @arg SDIO_INT_CMDSENT: Command sent (no response required) interrupt 716 * @arg SDIO_INT_DATAEND: Data end (data counter is zero) interrupt 717 * @arg SDIO_INT_SBE: Start bit not detected on all data signals in wide bus mode interrupt 718 * @arg SDIO_INT_DBCP: Data block sent/received (CRC check passed) interrupt 719 * @arg SDIO_INT_SDIOINT: SD I/O interrupt received interrupt 720 * @arg SDIO_INT_ATAEND: CE-ATA command completion signal received for CMD61 interrupt 721 * 722 * @retval None 723 */ SDIO_ClearIntFlag(uint32_t flag)724void SDIO_ClearIntFlag(uint32_t flag) 725 { 726 SDIO->ICF = flag; 727 } 728 729 /**@} end of group SDIO_Functions */ 730 /**@} end of group SDIO_Driver */ 731 /**@} end of group APM32F10x_StdPeriphDriver */ 732