1 /*!
2 * @file apm32f10x_smc.c
3 *
4 * @brief This file provides all the SMC firmware functions
5 *
6 * @version V1.0.4
7 *
8 * @date 2022-12-01
9 *
10 * @attention
11 *
12 * Copyright (C) 2020-2022 Geehy Semiconductor
13 *
14 * You may not use this file except in compliance with the
15 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
16 *
17 * The program is only for reference, which is distributed in the hope
18 * that it will be useful and instructional for customers to develop
19 * their software. Unless required by applicable law or agreed to in
20 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
21 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
23 * and limitations under the License.
24 */
25
26 #include "apm32f10x_smc.h"
27 #include "apm32f10x_rcm.h"
28
29 /** @addtogroup APM32F10x_StdPeriphDriver
30 @{
31 */
32
33 /** @addtogroup SMC_Driver SMC Driver
34 * @brief SMC driver modules
35 @{
36 */
37
38 /** @defgroup SMC_Functions Functions
39 @{
40 */
41
42 /*!
43 * @brief Reset the EMMMC NOR/SRAM Banks registers
44 *
45 * @param bank: Select the EMMMC Bank.
46 * The parameter can be one of following values:
47 * @arg SMC_BANK1_NORSRAM_1: SMC Bank1 NOR/SRAM1
48 * @arg SMC_BANK1_NORSRAM_2: SMC Bank1 NOR/SRAM2
49 * @arg SMC_BANK1_NORSRAM_3: SMC Bank1 NOR/SRAM3
50 * @arg SMC_BANK1_NORSRAM_4: SMC Bank1 NOR/SRAM4
51 *
52 * @retval None
53 */
SMC_ResetNORSRAM(SMC_BANK1_NORSRAM_T bank)54 void SMC_ResetNORSRAM(SMC_BANK1_NORSRAM_T bank)
55 {
56 /* SMC_BANK1_NORSRAM_1 */
57 if (bank == SMC_BANK1_NORSRAM_1)
58 {
59 SMC_Bank1->SNCTRL_T[bank] = 0x000030DB;
60 }
61 /* SMC_BANK1_NORSRAM_2, SMC_BANK1_NORSRAM_3 or SMC_BANK1_NORSRAM_4 */
62 else
63 {
64 SMC_Bank1->SNCTRL_T[bank] = 0x000030D2;
65 }
66 SMC_Bank1->SNCTRL_T[bank + 1] = 0x0FFFFFFF;
67 SMC_Bank1E->WRTTIM[bank] = 0x0FFFFFFF;
68 }
69
70 /*!
71 * @brief Reset the EMMMC NAND Banks registers
72 *
73 * @param bank: Select the EMMMC Bank.
74 * The parameter can be one of following values:
75 * @arg SMC_BANK2_NAND: FSMC Bank2 NAND
76 * @arg SMC_BANK3_NAND: FSMC Bank3 NAND
77 *
78 * @retval None
79 */
SMC_ResetNAND(SMC_BANK_NAND_T bank)80 void SMC_ResetNAND(SMC_BANK_NAND_T bank)
81 {
82 if (bank == SMC_BANK2_NAND)
83 {
84 /* Set the SMC_Bank2 registers to their reset values */
85 SMC_Bank2->CTRL2 = 0x00000018;
86 SMC_Bank2->STSINT2 = 0x00000040;
87 SMC_Bank2->CMSTIM2 = 0xFCFCFCFC;
88 SMC_Bank2->AMSTIM2 = 0xFCFCFCFC;
89 }
90 /* SMC BANK3 NAND */
91 else
92 {
93 /* Set the SMC_Bank3 registers to their reset values */
94 SMC_Bank3->CTRL3 = 0x00000018;
95 SMC_Bank3->STSINT3 = 0x00000040;
96 SMC_Bank3->CMSTIM3 = 0xFCFCFCFC;
97 SMC_Bank3->AMSTIM3 = 0xFCFCFCFC;
98 }
99 }
100
101 /*!
102 * @brief Reset the EMMMC PCCARD Banks registers
103 *
104 * @param None
105 *
106 * @retval None
107 */
SMC_ResetPCCard(void)108 void SMC_ResetPCCard(void)
109 {
110 /* Set the SMC_Bank4 registers to their reset values */
111 SMC_Bank4->CTRL4 = 0x00000018;
112 SMC_Bank4->STSINT4 = 0x00000040;
113 SMC_Bank4->CMSTIM4 = 0xFCFCFCFC;
114 SMC_Bank4->AMSTIM4 = 0xFCFCFCFC;
115 SMC_Bank4->IOSTIM4 = 0xFCFCFCFC;
116 }
117
118 /*!
119 * @brief Configures the SMC NOR/SRAM Banks according to the specified parameters in the smcNORSRAMConfig.
120 *
121 * @param smcNORSRAMConfig: Point to a SMC_NORSRAMConfig_T structure
122 *
123 * @retval None
124 */
SMC_ConfigNORSRAM(SMC_NORSRAMConfig_T * smcNORSRAMConfig)125 void SMC_ConfigNORSRAM(SMC_NORSRAMConfig_T* smcNORSRAMConfig)
126 {
127 /* Bank1 NOR/SRAM control register configuration */
128 SMC_Bank1->SNCTRL_T[smcNORSRAMConfig->bank] =
129 (uint32_t)smcNORSRAMConfig->dataAddressMux |
130 smcNORSRAMConfig->memoryType |
131 smcNORSRAMConfig->memoryDataWidth |
132 smcNORSRAMConfig->burstAcceesMode |
133 smcNORSRAMConfig->asynchronousWait |
134 smcNORSRAMConfig->waitSignalPolarity |
135 smcNORSRAMConfig->wrapMode |
136 smcNORSRAMConfig->waitSignalActive |
137 smcNORSRAMConfig->writeOperation |
138 smcNORSRAMConfig->waiteSignal |
139 smcNORSRAMConfig->extendedMode |
140 smcNORSRAMConfig->writeBurst;
141
142 if (smcNORSRAMConfig->memoryType == SMC_MEMORY_TYPE_NOR)
143 {
144 SMC_Bank1->SNCTRL_T[smcNORSRAMConfig->bank] |= 0x00000040;
145 }
146
147 /* Bank1 NOR/SRAM timing register configuration */
148 SMC_Bank1->SNCTRL_T[smcNORSRAMConfig->bank + 1] =
149 (uint32_t)smcNORSRAMConfig->readWriteTimingStruct->addressSetupTime |
150 (smcNORSRAMConfig->readWriteTimingStruct->addressHodeTime << 4) |
151 (smcNORSRAMConfig->readWriteTimingStruct->dataSetupTime << 8) |
152 (smcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime << 16) |
153 (smcNORSRAMConfig->readWriteTimingStruct->clockDivision << 20) |
154 (smcNORSRAMConfig->readWriteTimingStruct->dataLatency << 24) |
155 smcNORSRAMConfig->readWriteTimingStruct->accessMode;
156
157 /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
158 if (smcNORSRAMConfig->extendedMode == SMC_EXTENDEN_MODE_ENABLE)
159 {
160 SMC_Bank1E->WRTTIM[smcNORSRAMConfig->bank] =
161 (uint32_t)smcNORSRAMConfig->writeTimingStruct->addressSetupTime |
162 (smcNORSRAMConfig->writeTimingStruct->addressHodeTime << 4) |
163 (smcNORSRAMConfig->writeTimingStruct->dataSetupTime << 8) |
164 (smcNORSRAMConfig->writeTimingStruct->clockDivision << 20) |
165 (smcNORSRAMConfig->writeTimingStruct->dataLatency << 24) |
166 smcNORSRAMConfig->writeTimingStruct->accessMode;
167 }
168 else
169 {
170 SMC_Bank1E->WRTTIM[smcNORSRAMConfig->bank] = 0x0FFFFFFF;
171 }
172 }
173
174 /*!
175 * @brief Configures the SMC NAND Banks according to the specified parameters in the smcNANDConfig.
176 *
177 * @param smcNANDConfig : Point to a SMC_NANDConfig_T structure.
178 *
179 * @retval None
180 */
SMC_ConfigNAND(SMC_NANDConfig_T * smcNANDConfig)181 void SMC_ConfigNAND(SMC_NANDConfig_T* smcNANDConfig)
182 {
183 uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
184
185 /* Set the tmppcr value according to SMC_NANDInitStruct parameters */
186 tmppcr = (uint32_t)smcNANDConfig->waitFeature | 0x00000008 |
187 smcNANDConfig->memoryDataWidth |
188 smcNANDConfig->ECC |
189 smcNANDConfig->ECCPageSize |
190 (smcNANDConfig->TCLRSetupTime << 9) |
191 (smcNANDConfig->TARSetupTime << 13);
192
193 /* Set tmppmem value according to SMC_CommonSpaceTimingStructure parameters */
194 tmppmem = (uint32_t)smcNANDConfig->commonSpaceTimingStruct->setupTime |
195 (smcNANDConfig->commonSpaceTimingStruct->waitSetupTime << 8) |
196 (smcNANDConfig->commonSpaceTimingStruct->holdSetupTime << 16) |
197 (smcNANDConfig->commonSpaceTimingStruct->HiZSetupTime << 24);
198
199 /* Set tmppatt value according to SMC_AttributeSpaceTimingStructure parameters */
200 tmppatt = (uint32_t)smcNANDConfig->attributeSpaceTimingStruct->setupTime |
201 (smcNANDConfig->attributeSpaceTimingStruct->waitSetupTime << 8) |
202 (smcNANDConfig->attributeSpaceTimingStruct->holdSetupTime << 16) |
203 (smcNANDConfig->attributeSpaceTimingStruct->HiZSetupTime << 24);
204
205 if (smcNANDConfig->bank == SMC_BANK2_NAND)
206 {
207 /* SMC_BANK2_NAND registers configuration */
208 SMC_Bank2->CTRL2 = tmppcr;
209 SMC_Bank2->CMSTIM2 = tmppmem;
210 SMC_Bank2->AMSTIM2 = tmppatt;
211 }
212 else
213 {
214 /* SMC_BANK3_NAND registers configuration */
215 SMC_Bank3->CTRL3 = tmppcr;
216 SMC_Bank3->CMSTIM3 = tmppmem;
217 SMC_Bank3->AMSTIM3 = tmppatt;
218 }
219
220 }
221
222 /*!
223 * @brief Configures the SMC PCCARD according to the specified parameters in the smcPCCardConfig.
224 *
225 * @param smcPCCardConfig: Point to a SMC_PCCARDConfig_T structure.
226 *
227 * @retval None
228 */
SMC_ConfigPCCard(SMC_PCCARDConfig_T * smcPCCardConfig)229 void SMC_ConfigPCCard(SMC_PCCARDConfig_T* smcPCCardConfig)
230 {
231 /* Set the PCR4 register value according to SMC_PCCARDInitStruct parameters */
232 SMC_Bank4->CTRL4 = (uint32_t)smcPCCardConfig->waitFeature | SMC_MEMORY_DATA_WIDTH_16BIT |
233 (smcPCCardConfig->TCLRSetupTime << 9) |
234 (smcPCCardConfig->TARSetupTime << 13);
235
236 /* Set PMEM4 register value according to SMC_CommonSpaceTimingStructure parameters */
237 SMC_Bank4->CMSTIM4 = (uint32_t)smcPCCardConfig->commonSpaceTimingStruct->setupTime |
238 (smcPCCardConfig->commonSpaceTimingStruct->waitSetupTime << 8) |
239 (smcPCCardConfig->commonSpaceTimingStruct->holdSetupTime << 16) |
240 (smcPCCardConfig->commonSpaceTimingStruct->HiZSetupTime << 24);
241
242 /* Set PATT4 register value according to SMC_AttributeSpaceTimingStructure parameters */
243 SMC_Bank4->AMSTIM4 = (uint32_t)smcPCCardConfig->attributeSpaceTimingStruct->setupTime |
244 (smcPCCardConfig->attributeSpaceTimingStruct->waitSetupTime << 8) |
245 (smcPCCardConfig->attributeSpaceTimingStruct->holdSetupTime << 16) |
246 (smcPCCardConfig->attributeSpaceTimingStruct->HiZSetupTime << 24);
247
248 /* Set PIO4 register value according to SMC_IOSpaceTimingStructure parameters */
249 SMC_Bank4->IOSTIM4 = (uint32_t)smcPCCardConfig->IOSpaceTimingStruct->setupTime |
250 (smcPCCardConfig->IOSpaceTimingStruct->waitSetupTime << 8) |
251 (smcPCCardConfig->IOSpaceTimingStruct->holdSetupTime << 16) |
252 (smcPCCardConfig->IOSpaceTimingStruct->HiZSetupTime << 24);
253 }
254
255 /*!
256 * @brief Fills each smcNORSRAMConfig member with its default value.
257 *
258 * @param smcNORSRAMConfig : Point to a SMC_NORSRAMConfig_T structure.
259 *
260 * @retval None
261 */
SMC_ConfigNORSRAMStructInit(SMC_NORSRAMConfig_T * smcNORSRAMConfig)262 void SMC_ConfigNORSRAMStructInit(SMC_NORSRAMConfig_T* smcNORSRAMConfig)
263 {
264 /* Reset NOR/SRAM Init structure parameters values */
265 smcNORSRAMConfig->bank = SMC_BANK1_NORSRAM_1;
266 smcNORSRAMConfig->dataAddressMux = SMC_DATA_ADDRESS_MUX_ENABLE;
267 smcNORSRAMConfig->memoryType = SMC_MEMORY_TYPE_SRAM;
268 smcNORSRAMConfig->memoryDataWidth = SMC_MEMORY_DATA_WIDTH_8BIT;
269 smcNORSRAMConfig->burstAcceesMode = SMC_BURST_ACCESS_MODE_DISABLE;
270 smcNORSRAMConfig->asynchronousWait = SMC_ASYNCHRONOUS_WAIT_DISABLE;
271 smcNORSRAMConfig->waitSignalPolarity = SMC_WAIT_SIGNAL_POLARITY_LOW;
272 smcNORSRAMConfig->wrapMode = SMC_WRAP_MODE_DISABLE;
273 smcNORSRAMConfig->waitSignalActive = SMC_WAIT_SIGNAL_ACTIVE_BEFORE_WAIT;
274 smcNORSRAMConfig->writeOperation = SMC_WRITE_OPERATION_ENABLE;
275 smcNORSRAMConfig->waiteSignal = SMC_WAITE_SIGNAL_ENABLE;
276 smcNORSRAMConfig->extendedMode = SMC_EXTENDEN_MODE_DISABLE;
277 smcNORSRAMConfig->writeBurst = SMC_WRITE_BURST_DISABLE;
278 smcNORSRAMConfig->readWriteTimingStruct->addressSetupTime = 0xF;
279 smcNORSRAMConfig->readWriteTimingStruct->addressHodeTime = 0xF;
280 smcNORSRAMConfig->readWriteTimingStruct->dataSetupTime = 0xFF;
281 smcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime = 0xF;
282 smcNORSRAMConfig->readWriteTimingStruct->clockDivision = 0xF;
283 smcNORSRAMConfig->readWriteTimingStruct->dataLatency = 0xF;
284 smcNORSRAMConfig->readWriteTimingStruct->accessMode = SMC_ACCESS_MODE_A;
285 smcNORSRAMConfig->writeTimingStruct->addressSetupTime = 0xF;
286 smcNORSRAMConfig->writeTimingStruct->addressHodeTime = 0xF;
287 smcNORSRAMConfig->writeTimingStruct->dataSetupTime = 0xFF;
288 smcNORSRAMConfig->writeTimingStruct->busTurnaroundTime = 0xF;
289 smcNORSRAMConfig->writeTimingStruct->clockDivision = 0xF;
290 smcNORSRAMConfig->writeTimingStruct->dataLatency = 0xF;
291 smcNORSRAMConfig->writeTimingStruct->accessMode = SMC_ACCESS_MODE_A;
292 }
293
294 /*!
295 * @brief Fills each smcNANDConfig member with its default value.
296 *
297 * @param smcNANDConfig : Point to a SMC_NANDConfig_T structure.
298 *
299 * @retval None
300 */
SMC_ConfigNANDStructInit(SMC_NANDConfig_T * smcNANDConfig)301 void SMC_ConfigNANDStructInit(SMC_NANDConfig_T* smcNANDConfig)
302 {
303 /* Reset NAND Init structure parameters values */
304 smcNANDConfig->bank = SMC_BANK2_NAND;
305 smcNANDConfig->waitFeature = SMC_WAIT_FEATURE_DISABLE;
306 smcNANDConfig->memoryDataWidth = SMC_MEMORY_DATA_WIDTH_8BIT;
307 smcNANDConfig->ECC = SMC_ECC_DISABLE;
308 smcNANDConfig->ECCPageSize = SMC_ECC_PAGE_SIZE_BYTE_256;
309 smcNANDConfig->TCLRSetupTime = 0x0;
310 smcNANDConfig->TARSetupTime = 0x0;
311 smcNANDConfig->commonSpaceTimingStruct->setupTime = 0xFC;
312 smcNANDConfig->commonSpaceTimingStruct->waitSetupTime = 0xFC;
313 smcNANDConfig->commonSpaceTimingStruct->holdSetupTime = 0xFC;
314 smcNANDConfig->commonSpaceTimingStruct->HiZSetupTime = 0xFC;
315 smcNANDConfig->attributeSpaceTimingStruct->setupTime = 0xFC;
316 smcNANDConfig->attributeSpaceTimingStruct->waitSetupTime = 0xFC;
317 smcNANDConfig->attributeSpaceTimingStruct->holdSetupTime = 0xFC;
318 smcNANDConfig->attributeSpaceTimingStruct->HiZSetupTime = 0xFC;
319 }
320
321 /*!
322 * @brief Fills each smcPCCardConfig member with its default value.
323 *
324 * @param smcPCCardConfig : Point to a SMC_PCCARDConfig_T structure.
325 *
326 * @retval None
327 */
SMC_ConfigPCCardStructInit(SMC_PCCARDConfig_T * smcPCCardConfig)328 void SMC_ConfigPCCardStructInit(SMC_PCCARDConfig_T* smcPCCardConfig)
329 {
330 /* Reset PCCARD Init structure parameters values */
331 smcPCCardConfig->waitFeature = SMC_WAIT_FEATURE_DISABLE;
332 smcPCCardConfig->TCLRSetupTime = 0x0;
333 smcPCCardConfig->TARSetupTime = 0x0;
334 smcPCCardConfig->commonSpaceTimingStruct->setupTime = 0xFC;
335 smcPCCardConfig->commonSpaceTimingStruct->waitSetupTime = 0xFC;
336 smcPCCardConfig->commonSpaceTimingStruct->holdSetupTime = 0xFC;
337 smcPCCardConfig->commonSpaceTimingStruct->HiZSetupTime = 0xFC;
338 smcPCCardConfig->attributeSpaceTimingStruct->setupTime = 0xFC;
339 smcPCCardConfig->attributeSpaceTimingStruct->waitSetupTime = 0xFC;
340 smcPCCardConfig->attributeSpaceTimingStruct->holdSetupTime = 0xFC;
341 smcPCCardConfig->attributeSpaceTimingStruct->HiZSetupTime = 0xFC;
342 smcPCCardConfig->IOSpaceTimingStruct->setupTime = 0xFC;
343 smcPCCardConfig->IOSpaceTimingStruct->waitSetupTime = 0xFC;
344 smcPCCardConfig->IOSpaceTimingStruct->holdSetupTime = 0xFC;
345 smcPCCardConfig->IOSpaceTimingStruct->HiZSetupTime = 0xFC;
346 }
347
348 /*!
349 * @brief Enable the specified NOR/SRAM Memory Bank.
350 *
351 * @param bank: Select the EMMMC Bank.
352 * The parameter can be one of following values:
353 * @arg SMC_BANK1_NORSRAM_1: SMC Bank1 NOR/SRAM1
354 * @arg SMC_BANK1_NORSRAM_2: SMC Bank1 NOR/SRAM2
355 * @arg SMC_BANK1_NORSRAM_3: SMC Bank1 NOR/SRAM3
356 * @arg SMC_BANK1_NORSRAM_4: SMC Bank1 NOR/SRAM4
357 *
358 * @retval None
359 */
SMC_EnableNORSRAM(SMC_BANK1_NORSRAM_T bank)360 void SMC_EnableNORSRAM(SMC_BANK1_NORSRAM_T bank)
361 {
362 SMC_Bank1->SNCTRL_T[bank] |= 0x00000001;
363 }
364
365 /*!
366 * @brief Disable the specified NOR/SRAM Memory Bank.
367 *
368 * @param bank: Select the EMMMC Bank.
369 * The parameter can be one of following values:
370 * @arg SMC_BANK1_NORSRAM_1: SMC Bank1 NOR/SRAM1
371 * @arg SMC_BANK1_NORSRAM_2: SMC Bank1 NOR/SRAM2
372 * @arg SMC_BANK1_NORSRAM_3: SMC Bank1 NOR/SRAM3
373 * @arg SMC_BANK1_NORSRAM_4: SMC Bank1 NOR/SRAM4
374 *
375 * @retval None
376 */
SMC_DisableNORSRAM(SMC_BANK1_NORSRAM_T bank)377 void SMC_DisableNORSRAM(SMC_BANK1_NORSRAM_T bank)
378 {
379 SMC_Bank1->SNCTRL_T[bank] &= 0x000FFFFE;
380 }
381
382 /*!
383 * @brief Enable the specified NAND Memory Bank.
384 *
385 * @param bank: Select the EMMMC Bank.
386 * The parameter can be one of following values:
387 * @arg SMC_BANK2_NAND: FSMC Bank2 NAND
388 * @arg SMC_BANK3_NAND: FSMC Bank3 NAND
389 *
390 * @retval None
391 */
SMC_EnableNAND(SMC_BANK_NAND_T bank)392 void SMC_EnableNAND(SMC_BANK_NAND_T bank)
393 {
394 if (bank == SMC_BANK2_NAND)
395 {
396 SMC_Bank2->CTRL2_B.MBKEN = BIT_SET;
397 }
398 else
399 {
400 SMC_Bank3->CTRL3_B.MBKEN = BIT_SET;
401 }
402 }
403
404 /*!
405 * @brief Disable the specified NAND Memory Bank.
406 *
407 * @param bank: Select the EMMMC Bank.
408 * The parameter can be one of following values:
409 * @arg SMC_BANK2_NAND: FSMC Bank2 NAND
410 * @arg SMC_BANK3_NAND: FSMC Bank3 NAND
411 *
412 * @retval None
413 */
SMC_DisableNAND(SMC_BANK_NAND_T bank)414 void SMC_DisableNAND(SMC_BANK_NAND_T bank)
415 {
416 if (bank == SMC_BANK2_NAND)
417 {
418 SMC_Bank2->CTRL2_B.MBKEN = BIT_RESET;
419 }
420 else
421 {
422 SMC_Bank3->CTRL3_B.MBKEN = BIT_RESET;
423 }
424 }
425
426 /*!
427 * @brief Enable the specified PC Card Memory Bank.
428 *
429 * @param None
430 *
431 * @retval None
432 */
SMC_EnablePCCARD(void)433 void SMC_EnablePCCARD(void)
434 {
435 SMC_Bank4->CTRL4_B.MBKEN = BIT_SET;
436 }
437
438 /*!
439 * @brief Disable the specified PC Card Memory Bank.
440 *
441 * @param None
442 *
443 * @retval None
444 */
SMC_DisablePCCARD(void)445 void SMC_DisablePCCARD(void)
446 {
447 SMC_Bank4->CTRL4_B.MBKEN = BIT_RESET;
448 }
449
450 /*!
451 * @brief Enable the SMC NAND ECC feature.
452 *
453 * @param bank: Select the EMMMC Bank.
454 * The parameter can be one of following values:
455 * @arg SMC_BANK2_NAND: FSMC Bank2 NAND
456 * @arg SMC_BANK3_NAND: FSMC Bank3 NAND
457 *
458 * @retval None
459 */
SMC_EnableNANDECC(SMC_BANK_NAND_T bank)460 void SMC_EnableNANDECC(SMC_BANK_NAND_T bank)
461 {
462 if (bank == SMC_BANK2_NAND)
463 {
464 SMC_Bank2->CTRL2 |= 0x00000040;
465 }
466 else
467 {
468 SMC_Bank3->CTRL3 |= 0x00000040;
469 }
470 }
471
472 /*!
473 * @brief Disable the SMC Bank2 or Bank3 NAND ECC feature.
474 *
475 * @param bank: Select the EMMMC Bank.
476 * The parameter can be one of following values:
477 * @arg SMC_BANK2_NAND: FSMC Bank2 NAND
478 * @arg SMC_BANK3_NAND: FSMC Bank3 NAND
479 *
480 * @retval None
481 *
482 */
SMC_DisableNANDECC(SMC_BANK_NAND_T bank)483 void SMC_DisableNANDECC(SMC_BANK_NAND_T bank)
484 {
485 if (bank == SMC_BANK2_NAND)
486 {
487 SMC_Bank2->CTRL2 &= 0x000FFFBF;
488 }
489 else
490 {
491 SMC_Bank3->CTRL3 &= 0x000FFFBF;
492 }
493 }
494
495 /*!
496 * @brief Read the error correction code register value.
497 *
498 * @param bank: Select the EMMMC Bank.
499 * The parameter can be one of following values:
500 * @arg SMC_BANK2_NAND: FSMC Bank2 NAND
501 * @arg SMC_BANK3_NAND: FSMC Bank3 NAND
502 *
503 * @retval The value of Error Correction Code (ECC).
504 */
SMC_ReadECC(SMC_BANK_NAND_T bank)505 uint32_t SMC_ReadECC(SMC_BANK_NAND_T bank)
506 {
507 uint32_t eccval = 0x00000000;
508
509 if (bank == SMC_BANK2_NAND)
510 {
511 eccval = SMC_Bank2->ECCRS2;
512 }
513 else
514 {
515 eccval = SMC_Bank3->ECCRS3;
516 }
517 return eccval;
518 }
519
520 /*!
521 * @brief Enable the specified SMC interrupts.
522 *
523 * @param bank: Select the EMMMC Bank.
524 * The parameter can be one of following values:
525 * @arg SMC_BANK2_NAND : FSMC Bank2 NAND
526 * @arg SMC_BANK3_NAND : FSMC Bank3 NAND
527 * @arg SMC_BANK4_PCCARD: FSMC Bank4 PCCARD
528 *
529 * @param interrupt: Select the SMC interrupt sources.
530 * This parameter can be any combination of the following values:
531 * @arg SMC_INT_EDGE_RISING : Rising edge detection interrupt.
532 * @arg SMC_INT_LEVEL_HIGH : High level detection interrupt.
533 * @arg SMC_INT_EDGE_FALLING: Falling edge detection interrupt.
534 *
535 * @retval None
536 */
SMC_EnableInterrupt(SMC_BANK_NAND_T bank,uint32_t interrupt)537 void SMC_EnableInterrupt(SMC_BANK_NAND_T bank, uint32_t interrupt)
538 {
539 if (bank == SMC_BANK2_NAND)
540 {
541 SMC_Bank2->STSINT2 |= interrupt;
542 }
543 else if (bank == SMC_BANK3_NAND)
544 {
545 SMC_Bank3->STSINT3 |= interrupt;
546 }
547 else
548 {
549 SMC_Bank4->STSINT4 |= interrupt;
550 }
551 }
552
553 /*!
554 * @brief Enable the specified SMC interrupts.
555 *
556 * @param bank: Select the EMMMC Bank.
557 * The parameter can be one of following values:
558 * @arg SMC_BANK2_NAND : FSMC Bank2 NAND
559 * @arg SMC_BANK3_NAND : FSMC Bank3 NAND
560 * @arg SMC_BANK4_PCCARD: FSMC Bank4 PCCARD
561 *
562 * @param interrupt: Select the SMC interrupt sources.
563 * This parameter can be any combination of the following values:
564 * @arg SMC_INT_EDGE_RISING : Rising edge detection interrupt.
565 * @arg SMC_INT_LEVEL_HIGH : High level edge detection interrupt.
566 * @arg SMC_INT_EDGE_FALLING: Falling edge detection interrupt.
567 *
568 * @retval None
569 */
SMC_DisableInterrupt(SMC_BANK_NAND_T bank,uint32_t interrupt)570 void SMC_DisableInterrupt(SMC_BANK_NAND_T bank, uint32_t interrupt)
571 {
572 if (bank == SMC_BANK2_NAND)
573 {
574 SMC_Bank2->STSINT2 &= ~interrupt;
575 }
576 else if (bank == SMC_BANK3_NAND)
577 {
578 SMC_Bank3->STSINT3 &= ~interrupt;
579 }
580 else
581 {
582 SMC_Bank4->STSINT4 &= ~interrupt;
583 }
584 }
585
586 /*!
587 * @brief Read the status of specified SMC flag.
588 *
589 * @param bank: Select the EMMMC Bank.
590 * The parameter can be one of following values:
591 * @arg SMC_BANK2_NAND : FSMC Bank2 NAND
592 * @arg SMC_BANK3_NAND : FSMC Bank3 NAND
593 * @arg SMC_BANK4_PCCARD: FSMC Bank4 PCCARD
594 *
595 * @param flag: Select the SMC interrupt sources.
596 * This parameter can be one of the following values:
597 * @arg SMC_FLAG_EDGE_RISING : Rising egde detection Flag.
598 * @arg SMC_FLAG_LEVEL_HIGH : High level detection Flag.
599 * @arg SMC_FLAG_EDGE_FALLING: Falling egde detection Flag.
600 * @arg SMC_FLAG_FIFO_EMPTY : FIFO empty Flag.
601 *
602 * @retval SET or RESET
603 *
604 */
SMC_ReadStatusFlag(SMC_BANK_NAND_T bank,SMC_FLAG_T flag)605 uint8_t SMC_ReadStatusFlag(SMC_BANK_NAND_T bank, SMC_FLAG_T flag)
606 {
607 uint32_t tmpsr = 0x00000000;
608
609 if (bank == SMC_BANK2_NAND)
610 {
611 tmpsr = SMC_Bank2->STSINT2;
612 }
613 else if (bank == SMC_BANK3_NAND)
614 {
615 tmpsr = SMC_Bank3->STSINT3;
616 }
617 else
618 {
619 tmpsr = SMC_Bank4->STSINT4;
620 }
621 /* Get the flag status */
622 if ((tmpsr & flag) != RESET)
623 {
624 return SET;
625 }
626 else
627 {
628 return RESET;
629 }
630 }
631
632 /*!
633 * @brief Clear the SMC's pending flags.
634 *
635 * @param bank: Select the EMMMC Bank.
636 * The parameter can be one of following values:
637 * @arg SMC_BANK2_NAND : FSMC Bank2 NAND
638 * @arg SMC_BANK3_NAND : FSMC Bank3 NAND
639 * @arg SMC_BANK4_PCCARD: FSMC Bank4 PCCARD
640 *
641 * @param flag: Select the SMC interrupt sources.
642 * This parameter can be any combination of the following values:
643 * @arg SMC_FLAG_EDGE_RISING : Rising egde detection Flag.
644 * @arg SMC_FLAG_LEVEL_HIGH : High level detection Flag.
645 * @arg SMC_FLAG_EDGE_FALLING: Falling egde detection Flag.
646 *
647 * @retval None
648 */
SMC_ClearStatusFlag(SMC_BANK_NAND_T bank,uint32_t flag)649 void SMC_ClearStatusFlag(SMC_BANK_NAND_T bank, uint32_t flag)
650 {
651 if (bank == SMC_BANK2_NAND)
652 {
653 SMC_Bank2->STSINT2 &= ~flag;
654 }
655 else if (bank == SMC_BANK3_NAND)
656 {
657 SMC_Bank3->STSINT3 &= ~flag;
658 }
659 else
660 {
661 SMC_Bank4->STSINT4 &= ~flag;
662 }
663 }
664
665 /*!
666 * @brief Read the specified SMC interrupt has occurred or not.
667 *
668 * @param bank: Select the EMMMC Bank.
669 * The parameter can be one of following values:
670 * @arg SMC_BANK2_NAND : FSMC Bank2 NAND
671 * @arg SMC_BANK3_NAND : FSMC Bank3 NAND
672 * @arg SMC_BANK4_PCCARD: FSMC Bank4 PCCARD
673 *
674 * @param interrupt: Select the SMC interrupt source.
675 * This parameter can be one of the following values:
676 * @arg SMC_INT_EDGE_RISING : Rising edge detection interrupt.
677 * @arg SMC_INT_LEVEL_HIGH : High level edge detection interrupt.
678 * @arg SMC_INT_EDGE_FALLING: Falling edge detection interrupt.
679 *
680 * @retval The status of specified SMC interrupt source.
681 */
SMC_ReadIntFlag(SMC_BANK_NAND_T bank,SMC_INT_T flag)682 uint8_t SMC_ReadIntFlag(SMC_BANK_NAND_T bank, SMC_INT_T flag)
683 {
684 uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
685
686 if (bank == SMC_BANK2_NAND)
687 {
688 tmpsr = SMC_Bank2->STSINT2;
689 }
690 else if (bank == SMC_BANK3_NAND)
691 {
692 tmpsr = SMC_Bank3->STSINT3;
693 }
694 else
695 {
696 tmpsr = SMC_Bank4->STSINT4;
697 }
698
699 itstatus = tmpsr & flag;
700 itenable = tmpsr & (flag >> 3);
701
702 if ((itstatus != RESET) && (itenable != RESET))
703 {
704 return SET;
705 }
706 else
707 {
708 return RESET;
709 }
710 }
711
712 /*!
713 * @brief Clear the SMC's interrupt Flag.
714 *
715 * @param bank: Select the EMMMC Bank.
716 * The parameter can be one of following values:
717 * @arg SMC_BANK2_NAND : FSMC Bank2 NAND
718 * @arg SMC_BANK3_NAND : FSMC Bank3 NAND
719 * @arg SMC_BANK4_PCCARD: FSMC Bank4 PCCARD
720 *
721 * @param interrupt: Select the SMC interrupt sources.
722 * This parameter can be any combination of the following values:
723 * @arg SMC_INT_EDGE_RISING : Rising edge detection interrupt.
724 * @arg SMC_INT_LEVEL_HIGH : High level edge detection interrupt.
725 * @arg SMC_INT_EDGE_FALLING: Falling edge detection interrupt.
726 *
727 * @retval None
728 */
SMC_ClearIntFlag(SMC_BANK_NAND_T bank,uint32_t flag)729 void SMC_ClearIntFlag(SMC_BANK_NAND_T bank, uint32_t flag)
730 {
731 if (bank == SMC_BANK2_NAND)
732 {
733 SMC_Bank2->STSINT2 &= ~(flag >> 3);
734 }
735 else if (bank == SMC_BANK3_NAND)
736 {
737 SMC_Bank3->STSINT3 &= ~(flag >> 3);
738 }
739 else
740 {
741 SMC_Bank4->STSINT4 &= ~(flag >> 3);
742 }
743 }
744
745 /**@} end of group SMC_Functions */
746 /**@} end of group SMC_Driver */
747 /**@} end of group APM32F10x_StdPeriphDriver */
748