1 /*! 2 * @file apm32f4xx_dmc.h 3 * 4 * @brief This file contains all the prototypes,enumeration and macros for the DMC peripheral 5 * 6 * @version V1.0.2 7 * 8 * @date 2022-06-23 9 * 10 * @attention 11 * 12 * Copyright (C) 2021-2022 Geehy Semiconductor 13 * 14 * You may not use this file except in compliance with the 15 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). 16 * 17 * The program is only for reference, which is distributed in the hope 18 * that it will be usefull and instructional for customers to develop 19 * their software. Unless required by applicable law or agreed to in 20 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT 21 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions 23 * and limitations under the License. 24 */ 25 26 /* Define to prevent recursive inclusion */ 27 #ifndef __APM32F4XX_DMC_H 28 #define __APM32F4XX_DMC_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /* Includes */ 35 #include "apm32f4xx.h" 36 37 /** @addtogroup APM32F4xx_StdPeriphDriver 38 @{ 39 */ 40 41 /** @addtogroup DMC_Driver 42 @{ 43 */ 44 45 /** @defgroup DMC_Enumerations 46 @{ 47 */ 48 49 /** 50 * @brief Bank Address Width 51 */ 52 typedef enum 53 { 54 DMC_BANK_WIDTH_1, /*!< Set bank address width to 1-bit */ 55 DMC_BANK_WIDTH_2 /*!< Set bank address width to 2-bit */ 56 } DMC_BANK_WIDTH_T; 57 58 /** 59 * @brief Row Address Width 60 */ 61 typedef enum 62 { 63 DMC_ROW_WIDTH_11 = 0x0A, /*!< Set row address width to 11-bit */ 64 DMC_ROW_WIDTH_12, /*!< Set row address width to 12-bit */ 65 DMC_ROW_WIDTH_13, /*!< Set row address width to 13-bit */ 66 DMC_ROW_WIDTH_14, /*!< Set row address width to 14-bit */ 67 DMC_ROW_WIDTH_15, /*!< Set row address width to 15-bit */ 68 DMC_ROW_WIDTH_16 /*!< Set row address width to 16-bit */ 69 } DMC_ROW_WIDTH_T; 70 71 /** 72 * @brief Column Address Width 73 */ 74 typedef enum 75 { 76 DMC_COL_WIDTH_8 = 0x07, /*!< Set column address width to 8-bit */ 77 DMC_COL_WIDTH_9, /*!< Set column address width to 9-bit */ 78 DMC_COL_WIDTH_10, /*!< Set column address width to 10-bit */ 79 DMC_COL_WIDTH_11, /*!< Set column address width to 11-bit */ 80 DMC_COL_WIDTH_12, /*!< Set column address width to 12-bit */ 81 DMC_COL_WIDTH_13, /*!< Set column address width to 13-bit */ 82 DMC_COL_WIDTH_14, /*!< Set column address width to 14-bit */ 83 DMC_COL_WIDTH_15 /*!< Set column address width to 15-bit */ 84 } DMC_COL_WIDTH_T; 85 86 /** 87 * @brief CAS Latency Select 88 */ 89 typedef enum 90 { 91 DMC_CAS_LATENCY_1, /*!< Set CAS lantency to 1 clock */ 92 DMC_CAS_LATENCY_2, /*!< Set CAS lantency to 2 clock */ 93 DMC_CAS_LATENCY_3, /*!< Set CAS lantency to 3 clock */ 94 DMC_CAS_LATENCY_4 /*!< Set CAS lantency to 4 clock */ 95 } DMC_CAS_LATENCY_T; 96 97 /** 98 * @brief RAS Minimun Time Select 99 */ 100 typedef enum 101 { 102 DMC_RAS_MINIMUM_1, /*!< Set RAS minimun time to 1 clock */ 103 DMC_RAS_MINIMUM_2, /*!< Set RAS minimun time to 2 clock */ 104 DMC_RAS_MINIMUM_3, /*!< Set RAS minimun time to 3 clock */ 105 DMC_RAS_MINIMUM_4, /*!< Set RAS minimun time to 4 clock */ 106 DMC_RAS_MINIMUM_5, /*!< Set RAS minimun time to 5 clock */ 107 DMC_RAS_MINIMUM_6, /*!< Set RAS minimun time to 6 clock */ 108 DMC_RAS_MINIMUM_7, /*!< Set RAS minimun time to 7 clock */ 109 DMC_RAS_MINIMUM_8, /*!< Set RAS minimun time to 8 clock */ 110 DMC_RAS_MINIMUM_9, /*!< Set RAS minimun time to 9 clock */ 111 DMC_RAS_MINIMUM_10, /*!< Set RAS minimun time to 10 clock */ 112 DMC_RAS_MINIMUM_11, /*!< Set RAS minimun time to 11 clock */ 113 DMC_RAS_MINIMUM_12, /*!< Set RAS minimun time to 12 clock */ 114 DMC_RAS_MINIMUM_13, /*!< Set RAS minimun time to 13 clock */ 115 DMC_RAS_MINIMUM_14, /*!< Set RAS minimun time to 14 clock */ 116 DMC_RAS_MINIMUM_15, /*!< Set RAS minimun time to 15 clock */ 117 DMC_RAS_MINIMUM_16 /*!< Set RAS minimun time to 16 clock */ 118 } DMC_RAS_MINIMUM_T; 119 120 /** 121 * @brief RAS To CAS Delay Time Select 122 */ 123 typedef enum 124 { 125 DMC_DELAY_TIME_1, /*!< Set RAS to CAS delay time to 1 clock */ 126 DMC_DELAY_TIME_2, /*!< Set RAS to CAS delay time to 2 clock */ 127 DMC_DELAY_TIME_3, /*!< Set RAS to CAS delay time to 3 clock */ 128 DMC_DELAY_TIME_4, /*!< Set RAS to CAS delay time to 4 clock */ 129 DMC_DELAY_TIME_5, /*!< Set RAS to CAS delay time to 5 clock */ 130 DMC_DELAY_TIME_6, /*!< Set RAS to CAS delay time to 6 clock */ 131 DMC_DELAY_TIME_7, /*!< Set RAS to CAS delay time to 7 clock */ 132 DMC_DELAY_TIME_8 /*!< Set RAS to CAS delay time to 8 clock */ 133 } DMC_DELAY_TIME_T; 134 135 /** 136 * @brief Precharge Period Select 137 */ 138 typedef enum 139 { 140 DMC_PRECHARGE_1, /*!< Set precharge period to 1 clock */ 141 DMC_PRECHARGE_2, /*!< Set precharge period to 2 clock */ 142 DMC_PRECHARGE_3, /*!< Set precharge period to 3 clock */ 143 DMC_PRECHARGE_4, /*!< Set precharge period to 4 clock */ 144 DMC_PRECHARGE_5, /*!< Set precharge period to 5 clock */ 145 DMC_PRECHARGE_6, /*!< Set precharge period to 6 clock */ 146 DMC_PRECHARGE_7, /*!< Set precharge period to 7 clock */ 147 DMC_PRECHARGE_8 /*!< Set precharge period to 8 clock */ 148 } DMC_PRECHARGE_T; 149 150 /** 151 * @brief Last Data Next Precharge For Write Time Select 152 */ 153 typedef enum 154 { 155 DMC_NEXT_PRECHARGE_1, /*!< Set time between the last data and 156 next precharge for write to 1 clock */ 157 DMC_NEXT_PRECHARGE_2, /*!< Set time between the last data and 158 next precharge for write to 2 clock */ 159 DMC_NEXT_PRECHARGE_3, /*!< Set time between the last data and 160 next precharge for write to 3 clock */ 161 DMC_NEXT_PRECHARGE_4 /*!< Set time between the last data and 162 next precharge for write to 4 clock */ 163 } DMC_NEXT_PRECHARGE_T; 164 165 /** 166 * @brief Auto-Refresh Period Select 167 */ 168 typedef enum 169 { 170 DMC_AUTO_REFRESH_1, /*!< Set auto-refresh period to 1 clock */ 171 DMC_AUTO_REFRESH_2, /*!< Set auto-refresh period to 2 clock */ 172 DMC_AUTO_REFRESH_3, /*!< Set auto-refresh period to 3 clock */ 173 DMC_AUTO_REFRESH_4, /*!< Set auto-refresh period to 4 clock */ 174 DMC_AUTO_REFRESH_5, /*!< Set auto-refresh period to 5 clock */ 175 DMC_AUTO_REFRESH_6, /*!< Set auto-refresh period to 6 clock */ 176 DMC_AUTO_REFRESH_7, /*!< Set auto-refresh period to 7 clock */ 177 DMC_AUTO_REFRESH_8, /*!< Set auto-refresh period to 8 clock */ 178 DMC_AUTO_REFRESH_9, /*!< Set auto-refresh period to 9 clock */ 179 DMC_AUTO_REFRESH_10, /*!< Set auto-refresh period to 10 clock */ 180 DMC_AUTO_REFRESH_11, /*!< Set auto-refresh period to 11 clock */ 181 DMC_AUTO_REFRESH_12, /*!< Set auto-refresh period to 12 clock */ 182 DMC_AUTO_REFRESH_13, /*!< Set auto-refresh period to 13 clock */ 183 DMC_AUTO_REFRESH_14, /*!< Set auto-refresh period to 14 clock */ 184 DMC_AUTO_REFRESH_15, /*!< Set auto-refresh period to 15 clock */ 185 DMC_AUTO_REFRESH_16, /*!< Set auto-refresh period to 16 clock */ 186 } DMC_AUTO_REFRESH_T; 187 188 /** 189 * @brief Active-to-active Command Period Select 190 */ 191 typedef enum 192 { 193 DMC_ATA_CMD_1, /*!< Set active to active command period to 1 clock */ 194 DMC_ATA_CMD_2, /*!< Set active to active command period to 2 clock */ 195 DMC_ATA_CMD_3, /*!< Set active to active command period to 3 clock */ 196 DMC_ATA_CMD_4, /*!< Set active to active command period to 4 clock */ 197 DMC_ATA_CMD_5, /*!< Set active to active command period to 5 clock */ 198 DMC_ATA_CMD_6, /*!< Set active to active command period to 6 clock */ 199 DMC_ATA_CMD_7, /*!< Set active to active command period to 7 clock */ 200 DMC_ATA_CMD_8, /*!< Set active to active command period to 8 clock */ 201 DMC_ATA_CMD_9, /*!< Set active to active command period to 9 clock */ 202 DMC_ATA_CMD_10, /*!< Set active to active command period to 10 clock */ 203 DMC_ATA_CMD_11, /*!< Set active to active command period to 11 clock */ 204 DMC_ATA_CMD_12, /*!< Set active to active command period to 12 clock */ 205 DMC_ATA_CMD_13, /*!< Set active to active command period to 13 clock */ 206 DMC_ATA_CMD_14, /*!< Set active to active command period to 14 clock */ 207 DMC_ATA_CMD_15, /*!< Set active to active command period to 15 clock */ 208 DMC_ATA_CMD_16, /*!< Set active to active command period to 16 clock */ 209 } DMC_ATA_CMD_T; 210 211 /** 212 * @brief Clock PHASE 213 */ 214 typedef enum 215 { 216 DMC_CLK_PHASE_NORMAL, /*!< Clock phase is normal */ 217 DMC_CLK_PHASE_REVERSE /*!< Clock phase is reverse */ 218 } DMC_CLK_PHASE_T; 219 220 /** 221 * @brief Open Banks Of Number 222 */ 223 typedef enum 224 { 225 DMC_BANK_NUMBER_1, /*!< Set 1 bank be opened */ 226 DMC_BANK_NUMBER_2, /*!< Set 2 banks be opened */ 227 DMC_BANK_NUMBER_3, /*!< Set 3 banks be opened */ 228 DMC_BANK_NUMBER_4, /*!< Set 4 banks be opened */ 229 DMC_BANK_NUMBER_5, /*!< Set 5 banks be opened */ 230 DMC_BANK_NUMBER_6, /*!< Set 6 banks be opened */ 231 DMC_BANK_NUMBER_7, /*!< Set 7 banks be opened */ 232 DMC_BANK_NUMBER_8, /*!< Set 8 banks be opened */ 233 DMC_BANK_NUMBER_9, /*!< Set 9 banks be opened */ 234 DMC_BANK_NUMBER_10, /*!< Set 10 banks be opened */ 235 DMC_BANK_NUMBER_11, /*!< Set 11 banks be opened */ 236 DMC_BANK_NUMBER_12, /*!< Set 12 banks be opened */ 237 DMC_BANK_NUMBER_13, /*!< Set 13 banks be opened */ 238 DMC_BANK_NUMBER_14, /*!< Set 14 banks be opened */ 239 DMC_BANK_NUMBER_15, /*!< Set 15 banks be opened */ 240 DMC_BANK_NUMBER_16, /*!< Set 16 banks be opened */ 241 } DMC_BANK_NUMBER_T; 242 243 /** 244 * @brief Full refresh type 245 */ 246 typedef enum 247 { 248 DMC_REFRESH_ROW_ONE, /*!< Refresh one row */ 249 DMC_REFRESH_ROW_ALL, /*!< Refresh all row */ 250 } DMC_REFRESH_T; 251 252 /** 253 * @brief Precharge type 254 */ 255 typedef enum 256 { 257 DMC_PRECHARGE_IM, /*!< Immediate precharge */ 258 DMC_PRECHARGE_DELAY, /*!< Delayed precharge */ 259 } DMC_PRECHARE_T; 260 261 /** 262 * @brief WRAP Burst Type 263 */ 264 typedef enum 265 { 266 DMC_WRAPB_4, /*!< Wrap4 burst transfer */ 267 DMC_WRAPB_8, /*!< Wrap8 burst transfer */ 268 } DMC_WRPB_T; 269 270 /**@} end of group DMC_Enumerations*/ 271 272 /** @addtogroup DMC_Structure Data Structure 273 @{ 274 */ 275 276 /** 277 * @brief Timing config definition 278 */ 279 typedef struct 280 { 281 uint32_t latencyCAS : 2; /*!< DMC_CAS_LATENCY_T */ 282 uint32_t tRAS : 4; /*!< DMC_RAS_MINIMUM_T */ 283 uint32_t tRCD : 3; /*!< DMC_DELAY_TIME_T */ 284 uint32_t tRP : 3; /*!< DMC_PRECHARGE_T */ 285 uint32_t tWR : 2; /*!< DMC_NEXT_PRECHARGE_T */ 286 uint32_t tARP : 4; /*!< DMC_AUTO_REFRESH_T */ 287 uint32_t tCMD : 4; /*!< DMC_ATA_CMD_T */ 288 uint32_t tXSR : 9; /*!< auto-refresh commands, can be 0x000 to 0x1FF */ 289 uint16_t tRFP : 16; /*!< Refresh period, can be 0x0000 to 0xFFFF */ 290 } DMC_TimingConfig_T; 291 292 /** 293 * @brief Config struct definition 294 */ 295 typedef struct 296 { 297 DMC_BANK_WIDTH_T bankWidth; /*!< Number of bank bits */ 298 DMC_ROW_WIDTH_T rowWidth; /*!< Number of row address bits */ 299 DMC_COL_WIDTH_T colWidth; /*!< Number of col address bits */ 300 DMC_CLK_PHASE_T clkPhase; /*!< Clock phase */ 301 DMC_TimingConfig_T timing; /*!< Timing */ 302 } DMC_Config_T; 303 304 /**@} end of group DMC_Structure*/ 305 306 /** @defgroup DMC_Functions 307 @{ 308 */ 309 310 /* Enable / Disable */ 311 void DMC_Enable(void); 312 void DMC_Disable(void); 313 void DMC_EnableInit(void); 314 315 /* Global config */ 316 void DMC_Config(DMC_Config_T* dmcConfig); 317 void DMC_ConfigStructInit(DMC_Config_T* dmcConfig); 318 319 /* Address */ 320 void DMC_ConfigBankWidth(DMC_BANK_WIDTH_T bankWidth); 321 void DMC_ConfigAddrWidth(DMC_ROW_WIDTH_T rowWidth, DMC_COL_WIDTH_T colWidth); 322 323 /* Timing */ 324 void DMC_ConfigTiming(DMC_TimingConfig_T* timingConfig); 325 void DMC_ConfigTimingStructInit(DMC_TimingConfig_T* timingConfig); 326 void DMC_ConfigStableTimePowerup(uint16_t stableTime); 327 void DMC_ConfigAutoRefreshNumDuringInit(DMC_AUTO_REFRESH_T num); 328 void DMC_ConfigRefreshPeriod(uint16_t period); 329 330 /* Refresh mode */ 331 void DMC_EixtSlefRefreshMode(void); 332 void DMC_EnterSlefRefreshMode(void); 333 334 /* Accelerate Module */ 335 void DMC_EnableAccelerateModule(void); 336 void DMC_DisableAccelerateModule(void); 337 338 /* Config */ 339 void DMC_ConfigOpenBank(DMC_BANK_NUMBER_T num); 340 void DMC_EnableUpdateMode(void); 341 void DMC_EnterPowerdownMode(void); 342 void DMC_ConfigFullRefreshBeforeSR(DMC_REFRESH_T refresh); 343 void DMC_ConfigFullRefreshAfterSR(DMC_REFRESH_T refresh); 344 void DMC_ConfigPrechargeType(DMC_PRECHARE_T precharge); 345 void DMC_ConfigClockPhase(DMC_CLK_PHASE_T clkPhase); 346 void DMC_ConfigWRAPB(DMC_WRPB_T burst); 347 348 /* read flag */ 349 uint8_t DMC_ReadSelfRefreshStatus(void); 350 351 #ifdef __cplusplus 352 } 353 #endif 354 355 #endif /* __APM32F4XX_DMC_H */ 356 357 /**@} end of group DMC_Enumerations */ 358 /**@} end of group DMC_Driver */ 359 /**@} end of group APM32F4xx_StdPeriphDriver */ 360