1 /*! 2 * @file apm32f4xx_tmr.h 3 * 4 * @brief This file contains all the functions prototypes for the TMR firmware library. 5 * 6 * @version V1.0.2 7 * 8 * @date 2022-06-23 9 * 10 * @attention 11 * 12 * Copyright (C) 2021-2022 Geehy Semiconductor 13 * 14 * You may not use this file except in compliance with the 15 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). 16 * 17 * The program is only for reference, which is distributed in the hope 18 * that it will be usefull and instructional for customers to develop 19 * their software. Unless required by applicable law or agreed to in 20 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT 21 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions 23 * and limitations under the License. 24 */ 25 26 /* Define to prevent recursive inclusion */ 27 #ifndef __APM32F4XX_TMR_H 28 #define __APM32F4XX_TMR_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /* Includes */ 35 #include "apm32f4xx.h" 36 37 /** @addtogroup APM32F4xx_StdPeriphDriver 38 @{ 39 */ 40 41 /** @addtogroup TMR_Driver 42 @{ 43 */ 44 45 /** @defgroup TMR_Enumerations 46 @{ 47 */ 48 49 /** 50 * @brief TMR Output Compare and PWM modes 51 */ 52 typedef enum 53 { 54 TMR_OC_MODE_TMRING = 0x00, /*!< Frozen TMR output compare mode */ 55 TMR_OC_MODE_ACTIVE = 0x01, /*!< Set output to high when matching */ 56 TMR_OC_MODE_INACTIVE = 0x02, /*!< Set output to low when matching */ 57 TMR_OC_MODE_TOGGLE = 0x03, /*!< Toggle output when matching */ 58 TMR_OC_MODE_LOWLEVEL = 0x04, /*!< Force output to be low */ 59 TMR_OC_MODE_HIGHLEVEL = 0x05, /*!< Force output to be high */ 60 TMR_OC_MODE_PWM1 = 0x06, /*!< PWM1 mode */ 61 TMR_OC_MODE_PWM2 = 0x07 /*!< PWM2 mode */ 62 } TMR_OC_MODE_T; 63 64 /** 65 * @brief TMR Single Pulse Mode 66 */ 67 typedef enum 68 { 69 TMR_SPM_REPETITIVE, /*!< Enable repetitive pulse mode */ 70 TMR_SPM_SINGLE /*!< Enable single pulse mode */ 71 } TMR_SPM_T; 72 73 /** 74 * @brief TMR Input Capture Init structure definition 75 */ 76 typedef enum 77 { 78 TMR_CHANNEL_1 = 0x0000, /*!< Timer Channel 1 */ 79 TMR_CHANNEL_2 = 0x0004, /*!< Timer Channel 2 */ 80 TMR_CHANNEL_3 = 0x0008, /*!< Timer Channel 3 */ 81 TMR_CHANNEL_4 = 0x000C /*!< Timer Channel 4 */ 82 } TMR_CHANNEL_T; 83 84 /** 85 * @brief TMR Clock division 86 */ 87 88 typedef enum 89 { 90 TMR_CLOCK_DIV_1, /*!< TDTS = Tck_tim */ 91 TMR_CLOCK_DIV_2, /*!< TDTS = 2 * Tck_tim */ 92 TMR_CLOCK_DIV_4 /*!< TDTS = 4 * Tck_tim */ 93 } TMR_CLOCK_DIV_T; 94 95 /** 96 * @brief TMR Counter Mode 97 */ 98 typedef enum 99 { 100 TMR_COUNTER_MODE_UP = 0x00, /*!< Timer Up Counting Mode */ 101 TMR_COUNTER_MODE_DOWN = 0x01, /*!< Timer Down Counting Mode */ 102 TMR_COUNTER_MODE_CENTER_ALIGNED1 = 0x10, /*!< Timer Center Aligned Mode1 */ 103 TMR_COUNTER_MODE_CENTER_ALIGNED2 = 0x20, /*!< Timer Center Aligned Mode2 */ 104 TMR_COUNTER_MODE_CENTER_ALIGNED3 = 0x30 /*!< Timer Center Aligned Mode3 */ 105 } TMR_COUNTER_MODE_T; 106 107 /** 108 * @brief TMR Output Compare Polarity 109 */ 110 typedef enum 111 { 112 TMR_OC_POLARITY_HIGH, /*!< Output Compare active high */ 113 TMR_OC_POLARITY_LOW /*!< Output Compare active low */ 114 } TMR_OC_POLARITY_T; 115 116 /** 117 * @brief TMR Output Compare N Polarity 118 */ 119 typedef enum 120 { 121 TMR_OC_NPOLARITY_HIGH, /*!< Output Compare active high */ 122 TMR_OC_NPOLARITY_LOW /*!< Output Compare active low */ 123 } TMR_OC_NPOLARITY_T; 124 125 /** 126 * @brief TMR Output Compare state 127 */ 128 typedef enum 129 { 130 TMR_OC_STATE_DISABLE, /*!< Disable output compare */ 131 TMR_OC_STATE_ENABLE /*!< Enable output compare */ 132 } TMR_OC_STATE_T; 133 134 /** 135 * @brief TMR Output Compare N state 136 */ 137 typedef enum 138 { 139 TMR_OC_NSTATE_DISABLE, /*!< Disable complementary output */ 140 TMR_OC_NSTATE_ENABLE /*!< Enable complementary output */ 141 } TMR_OC_NSTATE_T; 142 143 /** 144 * @brief TMR BRK state 145 */ 146 typedef enum 147 { 148 TMR_BRK_STATE_DISABLE, /*!< Disable brake function */ 149 TMR_BRK_STATE_ENABLE /*!< Enable brake function */ 150 } TMR_BRK_STATE_T; 151 152 /** 153 * @brief TMR Specifies the Break Input pin polarity. 154 */ 155 typedef enum 156 { 157 TMR_BRK_POLARITY_LOW, /*!< BRK low level valid */ 158 TMR_BRK_POLARITY_HIGH /*!< BRK high level valid */ 159 } TMR_BRK_POLARITY_T; 160 161 /** 162 * @brief TMR Specifies the Break Input pin polarity. 163 */ 164 typedef enum 165 { 166 TMR_AUTOMATIC_OUTPUT_DISABLE, /*!< Disable automatic output */ 167 TMR_AUTOMATIC_OUTPUT_ENABLE /*!< Enable automatic output */ 168 } TMR_AUTOMATIC_OUTPUT_T; 169 170 /** 171 * @brief TMR Protect mode configuration values 172 */ 173 typedef enum 174 { 175 TMR_LOCK_LEVEL_OFF, /*!< No lock write protection */ 176 TMR_LOCK_LEVEL_1, /*!< Lock write protection level 1 */ 177 TMR_LOCK_LEVEL_2, /*!< Lock write protection level 2 */ 178 TMR_LOCK_LEVEL_3 /*!< Lock write protection level 3 */ 179 } TMR_LOCK_LEVEL_T; 180 181 /** 182 * @brief TMR Specifies the Off-State selection used in Run mode 183 */ 184 typedef enum 185 { 186 TMR_RMOS_STATE_DISABLE, /*!< Disable run mode off-state */ 187 TMR_RMOS_STATE_ENABLE /*!< Enable run mode off-state */ 188 } TMR_RMOS_STATE_T; 189 190 /** 191 * @brief TMR Closed state configuration in idle mode 192 */ 193 typedef enum 194 { 195 TMR_IMOS_STATE_DISABLE, /*!< Disable idle mode off-state */ 196 TMR_IMOS_STATE_ENABLE /*!< Enable idle mode off-state */ 197 } TMR_IMOS_STATE_T; 198 199 /** 200 * @brief TMR Output Compare Idle State 201 */ 202 typedef enum 203 { 204 TMR_OC_IDLE_STATE_RESET, /*!< Reset output compare idle state */ 205 TMR_OC_IDLE_STATE_SET /*!< Set output compare idle state */ 206 } TMR_OC_IDLE_STATE_T; 207 208 /** 209 * @brief TMR Output Compare N Idle State 210 */ 211 typedef enum 212 { 213 TMR_OC_NIDLE_STATE_RESET, /*!< Reset output complementary idle state */ 214 TMR_OC_NIDLE_STATE_SET /*!< Set output complementary idle state */ 215 } TMR_OC_NIDLE_STATE_T; 216 217 /** 218 * @brief TMR Input Capture Polarity 219 */ 220 typedef enum 221 { 222 TMR_IC_POLARITY_RISING = 0x00, /*!< Rising edge */ 223 TMR_IC_POLARITY_FALLING = 0x02, /*!< Falling edge */ 224 TMR_IC_POLARITY_BOTHEDGE = 0x0A /*!< Both rising and falling edge */ 225 } TMR_IC_POLARITY_T; 226 227 /** 228 * @brief TMR Input Capture Selection 229 */ 230 typedef enum 231 { 232 TMR_IC_SELECTION_DIRECT_TI = 0x01, /*!< Input capture mapping in TI1 */ 233 TMR_IC_SELECTION_INDIRECT_TI = 0x02, /*!< Input capture mapping in TI2 */ 234 TMR_IC_SELECTION_TRC = 0x03 /*!< Input capture mapping in TRC */ 235 } TMR_IC_SELECTION_T; 236 237 /** 238 * @brief TMR Input Capture Prescaler 239 */ 240 typedef enum 241 { 242 TMR_IC_PSC_1, /*!< No prescaler */ 243 TMR_IC_PSC_2, /*!< Capture is done once every 2 events */ 244 TMR_IC_PSC_4, /*!< capture is done once every 4 events */ 245 TMR_IC_PSC_8 /*!< capture is done once every 8 events */ 246 } TMR_IC_PSC_T; 247 248 /** 249 * @brief TMR_interrupt_sources 250 */ 251 typedef enum 252 { 253 TMR_INT_UPDATE = 0x0001, /*!< Timer update Interrupt source */ 254 TMR_INT_CC1 = 0x0002, /*!< Timer Capture Compare 1 Interrupt source */ 255 TMR_INT_CC2 = 0x0004, /*!< Timer Capture Compare 2 Interrupt source */ 256 TMR_INT_CC3 = 0x0008, /*!< Timer Capture Compare 3 Interrupt source */ 257 TMR_INT_CC4 = 0x0010, /*!< Timer Capture Compare 4 Interrupt source */ 258 TMR_INT_COM = 0x0020, /*!< Timer Commutation Interrupt source (Only for TMR1 and TMR8) */ 259 TMR_INT_TRG = 0x0040, /*!< Timer Trigger Interrupt source */ 260 TMR_INT_BRK = 0x0080 /*!< Timer Break Interrupt source (Only for TMR1 and TMR8) */ 261 } TMR_INT_T; 262 263 /** 264 * @brief TMR DMA Base Address 265 */ 266 typedef enum 267 { 268 TMR_DMA_BASE_CTRL1 = 0x0000, /*!< TMR CTRL1 DMA base address setup */ 269 TMR_DMA_BASE_CTRL2 = 0x0001, /*!< TMR CTRL2 DMA base address setup */ 270 TMR_DMA_BASE_SMCTRL = 0x0002, /*!< TMR SMCTRL DMA base address setup */ 271 TMR_DMA_BASE_DIEN = 0x0003, /*!< TMR DIEN DMA base address setup */ 272 TMR_DMA_BASE_STS = 0x0004, /*!< TMR STS DMA base address setup */ 273 TMR_DMA_BASE_CEG = 0x0005, /*!< TMR CEG DMA base address setup */ 274 TMR_DMA_BASE_CCM1 = 0x0006, /*!< TMR CCM1 DMA base address setup */ 275 TMR_DMA_BASE_CCM2 = 0x0007, /*!< TMR CCM2 DMA base address setup */ 276 TMR_DMA_BASE_CCEN = 0x0008, /*!< TMR CCEN DMA base address setup */ 277 TMR_DMA_BASE_CNT = 0x0009, /*!< TMR CNT DMA base address setup */ 278 TMR_DMA_BASE_PSC = 0x000A, /*!< TMR PSC DMA base address setup */ 279 TMR_DMA_BASE_AUTORLD = 0x000B, /*!< TMR AUTORLD DMA base address setup */ 280 TMR_DMA_BASE_REPCNT = 0x000C, /*!< TMR REPCNT DMA base address setup */ 281 TMR_DMA_BASE_CC1 = 0x000D, /*!< TMR CC1 DMA base address setup */ 282 TMR_DMA_BASE_CC2 = 0x000E, /*!< TMR CC2 DMA base address setup */ 283 TMR_DMA_BASE_CC3 = 0x000F, /*!< TMR CC3 DMA base address setup */ 284 TMR_DMA_BASE_CC4 = 0x0010, /*!< TMR CC4 DMA base address setup */ 285 TMR_DMA_BASE_BDT = 0x0011, /*!< TMR BDT DMA base address setup */ 286 TMR_DMA_BASE_DCTRL = 0x0012 /*!< TMR DCTRL DMA base address setup */ 287 } TMR_DMA_BASE_T; 288 289 /** 290 * @brief TMR DMA Soueces 291 */ 292 typedef enum 293 { 294 TMR_DMA_SOURCE_UPDATE = 0x0100, /*!< TMR update DMA souces */ 295 TMR_DMA_SOURCE_CH1 = 0x0200, /*!< TMR Capture Compare 1 DMA souces */ 296 TMR_DMA_SOURCE_CH2 = 0x0400, /*!< TMR Capture Compare 2 DMA souces */ 297 TMR_DMA_SOURCE_CH3 = 0x0800, /*!< TMR Capture Compare 3 DMA souces */ 298 TMR_DMA_SOURCE_CH4 = 0x1000, /*!< TMR Capture Compare 4 DMA souces */ 299 TMR_DMA_SOURCE_COM = 0x2000, /*!< TMR Commutation DMA souces */ 300 TMR_DMA_SOURCE_TRG = 0x4000 /*!< TMR Trigger DMA souces */ 301 } TMR_DMA_SOURCE_T; 302 303 /** 304 * @brief TMR The external Trigger Prescaler. 305 */ 306 typedef enum 307 { 308 TMR_EXTTRG_PSC_OFF = 0x00, /*!< ETRP Prescaler OFF */ 309 TMR_EXTTRG_PSC_DIV2 = 0x01, /*!< ETRP frequency divided by 2 */ 310 TMR_EXTTRG_PSC_DIV4 = 0x02, /*!< ETRP frequency divided by 4 */ 311 TMR_EXTTRG_PSC_DIV8 = 0x03 /*!< ETRP frequency divided by 8 */ 312 } TMR_EXTTRG_PSC_T; 313 314 /** 315 * @brief TMR Internal Trigger Selection 316 */ 317 typedef enum 318 { 319 TMR_TRIGGER_SOURCE_ITR0 = 0x00, /*!< Internal Trigger 0 */ 320 TMR_TRIGGER_SOURCE_ITR1 = 0x01, /*!< Internal Trigger 1 */ 321 TMR_TRIGGER_SOURCE_ITR2 = 0x02, /*!< Internal Trigger 2 */ 322 TMR_TRIGGER_SOURCE_ITR3 = 0x03, /*!< Internal Trigger 3 */ 323 TMR_TRIGGER_SOURCE_TI1F_ED = 0x04, /*!< TI1 Edge Detector */ 324 TMR_TRIGGER_SOURCE_TI1FP1 = 0x05, /*!< Filtered Timer Input 1 */ 325 TMR_TRIGGER_SOURCE_TI2FP2 = 0x06, /*!< Filtered Timer Input 2 */ 326 TMR_TRIGGER_SOURCE_ETRF = 0x07 /*!< External Trigger input */ 327 } TMR_TRIGGER_SOURCE_T; 328 329 /** 330 * @brief TMR External Trigger Polarity 331 */ 332 typedef enum 333 { 334 TMR_EXTTGR_POL_NONINVERTED, /*!< Active high or rising edge active */ 335 TMR_EXTTRG_POL_INVERTED /*!< Active low or falling edge active */ 336 } TMR_EXTTRG_POL_T; 337 338 /** 339 * @brief TMR Prescaler Reload Mode 340 */ 341 typedef enum 342 { 343 TMR_PSC_RELOAD_UPDATE, /*!< The Prescaler reload at the update event */ 344 TMR_PSC_RELOAD_IMMEDIATE /*!< The Prescaler reload immediately */ 345 } TMR_PSC_RELOAD_T; 346 347 /** 348 * @brief TMR Forced Action 349 */ 350 typedef enum 351 { 352 TMR_FORCED_ACTION_INACTIVE = 0x04, /*!< Force inactive level on OC1REF */ 353 TMR_FORCED_ACTION_ACTIVE = 0x05 /*!< Force active level on OC1REF */ 354 } TMR_FORCED_ACTION_T; 355 356 /** 357 * @brief TMR Encoder Mode 358 */ 359 typedef enum 360 { 361 TMR_ENCODER_MODE_TI1 = 0x01, /*!< Encoder mode 1 */ 362 TMR_ENCODER_MODE_TI2 = 0x02, /*!< Encoder mode 2 */ 363 TMR_ENCODER_MODE_TI12 = 0x03 /*!< Encoder mode 3 */ 364 } TMR_ENCODER_MODE_T; 365 366 /** 367 * @brief TMR event sources 368 */ 369 typedef enum 370 { 371 TMR_EVENT_UPDATE = 0x001, /*!< Timer update Interrupt source */ 372 TMR_EVENT_CH1 = 0x002, /*!< Timer Capture Compare 1 Event source */ 373 TMR_EVENT_CH2 = 0x004, /*!< Timer Capture Compare 1 Event source */ 374 TMR_EVENT_CH3 = 0x008, /*!< Timer Capture Compare 3 Event source */ 375 TMR_EVENT_CH4 = 0x010, /*!< Timer Capture Compare 4 Event source */ 376 TMR_EVENT_COM = 0x020, /*!< Timer Commutation Event source (Only for TMR1 and TMR8) */ 377 TMR_EVENT_TRG = 0x040, /*!< Timer Trigger Event source */ 378 TMR_EVENT_BRK = 0x080 /*!< Timer Break Event source (Only for TMR1 and TMR8) */ 379 } TMR_EVENT_T; 380 381 /** 382 * @brief TMR UpdateSource 383 */ 384 typedef enum 385 { 386 TMR_UPDATE_SOURCE_GLOBAL, /*!< Source of update is 387 - Counter overflow/underflow. 388 - UEG bit of Control event generation register(CEG) is set. 389 - Update generation through the slave mode controller. */ 390 TMR_UPDATE_SOURCE_REGULAR /*!< Source of update is Counter overflow/underflow */ 391 } TMR_UPDATE_SOURCE_T; 392 393 /** 394 * @brief TMR Output Compare Preload State 395 */ 396 typedef enum 397 { 398 TMR_OC_PRELOAD_DISABLE, /*!< Enable preload */ 399 TMR_OC_PRELOAD_ENABLE /*!< Disable preload */ 400 } TMR_OC_PRELOAD_T; 401 402 /** 403 * @brief TMR Output Compare Preload State 404 */ 405 typedef enum 406 { 407 TMR_OC_FAST_DISABLE, /*!< Disable fast output compare */ 408 TMR_OC_FAST_ENABLE /*!< Enable fast output compare */ 409 } TMR_OC_FAST_T; 410 411 /** 412 * @brief TMR Output Compare Preload State 413 */ 414 typedef enum 415 { 416 TMR_OC_CLEAR_DISABLE, /*!< Disable output compare clear */ 417 TMR_OC_CLEAR_ENABLE /*!< Enable output compare clear */ 418 } TMR_OC_CLEAR_T; 419 420 /** 421 * @brief TMR Trigger Output Source 422 */ 423 typedef enum 424 { 425 TMR_TRGO_SOURCE_RESET, /*!< Select reset signal as TRGO source */ 426 TMR_TRGO_SOURCE_ENABLE, /*!< Select enable signal as TRGO source */ 427 TMR_TRGO_SOURCE_UPDATE, /*!< Select update signal as TRGO source */ 428 TMR_TRGO_SOURCE_OC1, /*!< Select OC1 signal as TRGO source */ 429 TMR_TRGO_SOURCE_OC1REF, /*!< Select OC1REF signal as TRGO source */ 430 TMR_TRGO_SOURCE_OC2REF, /*!< Select OC2REF signal as TRGO source */ 431 TMR_TRGO_SOURCE_OC3REF, /*!< Select OC3REF signal as TRGO source */ 432 TMR_TRGO_SOURCE_OC4REF /*!< Select OC4REF signal as TRGO source */ 433 } TMR_TRGO_SOURCE_T; 434 435 /** 436 * @brief TMR Slave Mode 437 */ 438 typedef enum 439 { 440 TMR_SLAVE_MODE_RESET = 0x04, /*!< Reset mode */ 441 TMR_SLAVE_MODE_GATED = 0x05, /*!< Gated mode */ 442 TMR_SLAVE_MODE_TRIGGER = 0x06, /*!< Trigger mode */ 443 TMR_SLAVE_MODE_EXTERNAL1 = 0x07 /*!< External 1 mode */ 444 } TMR_SLAVE_MODE_T; 445 446 /** 447 * @brief TMR Remap 448 */ 449 typedef enum 450 { 451 TMR2_TMR8_TRGO = 0x0000, /*!< TMR2 ITR1 input is connected to TMR8 Trigger output(default) */ 452 TMR2_PTP_TRG = 0x0400, /*!< TMR2 ITR1 input is connected to ETH PTP trigger output */ 453 TMR2_OTG_FSUSB_SOF = 0x0800, /*!< TMR2 ITR1 input is connected to OTG FS SOF */ 454 TMR2_OTG_HSUSB_SOF = 0x0C00, /*!< TMR2 ITR1 input is connected to OTG HS SOF */ 455 TMR5_GPIO = 0x0000, /*!< TMR5 CH4 input is connected to GPIO */ 456 TMR5_LSI = 0x0040, /*!< TMR5 CH4 input is connected to LSI clock */ 457 TMR5_LSE = 0x0080, /*!< TMR5 CH4 input is connected to LSE clock */ 458 TMR5_RTC = 0x00C0, /*!< TMR5 CH4 input is connected to RTC Output event */ 459 TMRx_GPIO = 0x0000, /*!< TMR10/11/13/14 CH1 input is connected to GPIO */ 460 TMRx_RTCCLK = 0x0001, /*!< TMR10/11/13/14 CH1 input is connected to RTC clock */ 461 TMRx_HSECLK = 0x0002, /*!< TMR10/11/13/14 CH1 input is connected to HSE clock/32 */ 462 TMRx_MCO = 0x0003 /*!< TMR10/11/13/14 CH1 input is connected to MCO */ 463 } TMR_REMAP_T; 464 465 /** 466 * @brief TMR Flag 467 */ 468 typedef enum 469 { 470 TMR_FLAG_UPDATE = 0x0001, /*!< Timer update Flag */ 471 TMR_FLAG_CC1 = 0x0002, /*!< Timer Capture Compare 1 Flag */ 472 TMR_FLAG_CC2 = 0x0004, /*!< Timer Capture Compare 2 Flag */ 473 TMR_FLAG_CC3 = 0x0008, /*!< Timer Capture Compare 3 Flag */ 474 TMR_FLAG_CC4 = 0x0010, /*!< Timer Capture Compare 4 Flag */ 475 TMR_FLAG_COM = 0x0020, /*!< Timer Commutation Flag (Only for TMR1 and TMR8) */ 476 TMR_FLAG_TRG = 0x0040, /*!< Timer Trigger Flag */ 477 TMR_FLAG_BRK = 0x0080, /*!< Timer Break Flag (Only for TMR1 and TMR8) */ 478 TMR_FLAG_CC1RC = 0x0200, /*!< Timer Capture Compare 1 Repetition Flag */ 479 TMR_FLAG_CC2RC = 0x0400, /*!< Timer Capture Compare 2 Repetition Flag */ 480 TMR_FLAG_CC3RC = 0x0800, /*!< Timer Capture Compare 3 Repetition Flag */ 481 TMR_FLAG_CC4RC = 0x1000 /*!< Timer Capture Compare 4 Repetition Flag */ 482 } TMR_FLAG_T; 483 484 /** 485 * @brief TMR DMA Burst Length 486 */ 487 typedef enum 488 { 489 TMR_DMA_BURSTLENGTH_1TRANSFER = 0x0000, /*!< Select TMR DMA burst Length 1 */ 490 TMR_DMA_BURSTLENGTH_2TRANSFERS = 0x0100, /*!< Select TMR DMA burst Length 2 */ 491 TMR_DMA_BURSTLENGTH_3TRANSFERS = 0x0200, /*!< Select TMR DMA burst Length 3 */ 492 TMR_DMA_BURSTLENGTH_4TRANSFERS = 0x0300, /*!< Select TMR DMA burst Length 4 */ 493 TMR_DMA_BURSTLENGTH_5TRANSFERS = 0x0400, /*!< Select TMR DMA burst Length 5 */ 494 TMR_DMA_BURSTLENGTH_6TRANSFERS = 0x0500, /*!< Select TMR DMA burst Length 6 */ 495 TMR_DMA_BURSTLENGTH_7TRANSFERS = 0x0600, /*!< Select TMR DMA burst Length 7 */ 496 TMR_DMA_BURSTLENGTH_8TRANSFERS = 0x0700, /*!< Select TMR DMA burst Length 8 */ 497 TMR_DMA_BURSTLENGTH_9TRANSFERS = 0x0800, /*!< Select TMR DMA burst Length 9 */ 498 TMR_DMA_BURSTLENGTH_10TRANSFERS = 0x0900, /*!< Select TMR DMA burst Length 10 */ 499 TMR_DMA_BURSTLENGTH_11TRANSFERS = 0x0A00, /*!< Select TMR DMA burst Length 11 */ 500 TMR_DMA_BURSTLENGTH_12TRANSFERS = 0x0B00, /*!< Select TMR DMA burst Length 12 */ 501 TMR_DMA_BURSTLENGTH_13TRANSFERS = 0x0C00, /*!< Select TMR DMA burst Length 13 */ 502 TMR_DMA_BURSTLENGTH_14TRANSFERS = 0x0D00, /*!< Select TMR DMA burst Length 14 */ 503 TMR_DMA_BURSTLENGTH_15TRANSFERS = 0x0E00, /*!< Select TMR DMA burst Length 15 */ 504 TMR_DMA_BURSTLENGTH_16TRANSFERS = 0x0F00, /*!< Select TMR DMA burst Length 16 */ 505 TMR_DMA_BURSTLENGTH_17TRANSFERS = 0x1000, /*!< Select TMR DMA burst Length 17 */ 506 TMR_DMA_BURSTLENGTH_18TRANSFERS = 0x1100 /*!< Select TMR DMA burst Length 18 */ 507 } TMR_DMA_BURSTLENGTH_T; 508 509 /**@} end of group TMR_Enumerations*/ 510 511 /** @addtogroup TMR_Structure Data Structure 512 @{ 513 */ 514 515 /** 516 * @brief TMR Time Base Init structure definition 517 * @note This structure is used with all TMR except for TMR6 and TMR7. 518 */ 519 typedef struct 520 { 521 TMR_COUNTER_MODE_T countMode; /*!< TMR counter mode selection */ 522 TMR_CLOCK_DIV_T clockDivision; /*!< TMR clock division selection */ 523 uint16_t period; /*!< This must between 0x0000 and 0xFFFF */ 524 uint16_t division; /*!< This must between 0x0000 and 0xFFFF */ 525 uint8_t repetitionCounter; /*!< This must between 0x00 and 0xFF, only for TMR1 and TMR8. */ 526 } TMR_BaseConfig_T; 527 528 /** 529 * @brief TMR Config struct definition 530 */ 531 typedef struct 532 { 533 TMR_OC_MODE_T mode; /*!< TMR Output Compare and PWM modes selection */ 534 TMR_OC_STATE_T outputState; /*!< TMR Output Compare state selection */ 535 TMR_OC_NSTATE_T outputNState; /*!< TMR Output Compare N state selection */ 536 TMR_OC_POLARITY_T polarity; /*!< TMR Output Compare Polarity selection */ 537 TMR_OC_NPOLARITY_T nPolarity; /*!< TMR Output Compare N Polarity selection */ 538 TMR_OC_IDLE_STATE_T idleState; /*!< TMR Output Compare Idle State selection */ 539 TMR_OC_NIDLE_STATE_T nIdleState; /*!< TMR Output Compare N Idle State selection */ 540 uint16_t pulse; /*!< This must between 0x0000 and 0xFFFF */ 541 } TMR_OCConfig_T; 542 543 /** 544 * @brief TMR Input Capture Config struct definition 545 */ 546 typedef struct 547 { 548 TMR_CHANNEL_T channel; /*!< Timer channel selection */ 549 TMR_IC_POLARITY_T polarity; /*!< TMR input capture polarity selection */ 550 TMR_IC_SELECTION_T selection; /*!< TMR Input capture selection */ 551 TMR_IC_PSC_T prescaler; /*!< TMR Input Capture selection */ 552 uint16_t filter; /*!< This must between 0x00 and 0x0F */ 553 } TMR_ICConfig_T; 554 555 /** 556 * @brief TMR BDT structure definition 557 */ 558 typedef struct 559 { 560 TMR_RMOS_STATE_T RMOS; /*!< TMR Specifies the Off-State selection used in Run mode selection */ 561 TMR_IMOS_STATE_T IMOS; /*!< TMR Closed state configuration in idle mode selection */ 562 TMR_LOCK_LEVEL_T lockLevel; /*!< TMR Protect mode configuration values selection */ 563 uint16_t deadTime; /*!< Setup dead time */ 564 TMR_BRK_STATE_T BRKState; /*!< Setup TMR BRK state */ 565 TMR_BRK_POLARITY_T BRKPolarity; /*!< Setup TMR BRK polarity */ 566 TMR_AUTOMATIC_OUTPUT_T automaticOutput; /*!< Setup break input pin polarity */ 567 } TMR_BDTConfig_T; 568 569 /**@} end of group TMR_Structure*/ 570 571 /** @defgroup TMR_Functions 572 @{ 573 */ 574 575 /* Reset and Configuration */ 576 void TMR_Reset(TMR_T* tmr); 577 void TMR_ConfigTimeBase(TMR_T* tmr, TMR_BaseConfig_T* baseConfig); 578 void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T* baseConfig); 579 void TMR_ConfigPrescaler(TMR_T* tmr, uint16_t prescaler, TMR_PSC_RELOAD_T reload); 580 void TMR_ConfigCounterMode(TMR_T* tmr, TMR_COUNTER_MODE_T countMode); 581 void TMR_ConfigCounter(TMR_T* tmr, uint16_t counter); 582 void TMR_ConfigAutoreload(TMR_T* tmr, uint16_t autoReload); 583 uint16_t TMR_ReadCounter(TMR_T* tmr); 584 uint16_t TMR_ReadPrescaler(TMR_T* tmr); 585 void TMR_EnableUpdate(TMR_T* tmr); 586 void TMR_DisableUpdate(TMR_T* tmr); 587 void TMR_ConfigUpdateRequest(TMR_T* tmr, TMR_UPDATE_SOURCE_T updateSource); 588 void TMR_EnableAutoReload(TMR_T* tmr); 589 void TMR_DisableAutoReload(TMR_T* tmr); 590 void TMR_ConfigSinglePulseMode(TMR_T* tmr, TMR_SPM_T singlePulseMode); 591 void TMR_ConfigClockDivision(TMR_T* tmr, TMR_CLOCK_DIV_T clockDivision); 592 void TMR_Enable(TMR_T* tmr); 593 void TMR_Disable(TMR_T* tmr); 594 595 /* Output Compare */ 596 void TMR_ConfigOC1(TMR_T* tmr, TMR_OCConfig_T* OCConfig); 597 void TMR_ConfigOC2(TMR_T* tmr, TMR_OCConfig_T* OCConfig); 598 void TMR_ConfigOC3(TMR_T* tmr, TMR_OCConfig_T* OCConfig); 599 void TMR_ConfigOC4(TMR_T* tmr, TMR_OCConfig_T* OCConfig); 600 void TMR_ConfigOCStructInit(TMR_OCConfig_T* OCConfig); 601 void TMR_SelectOCxMode(TMR_T* tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T mode); 602 void TMR_ConfigCompare1(TMR_T* tmr, uint32_t compare1); 603 void TMR_ConfigCompare2(TMR_T* tmr, uint32_t compare2); 604 void TMR_ConfigCompare3(TMR_T* tmr, uint32_t compare3); 605 void TMR_ConfigCompare4(TMR_T* tmr, uint32_t compare4); 606 void TMR_ConfigForcedOC1(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction); 607 void TMR_ConfigForcedOC2(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction); 608 void TMR_ConfigForcedOC3(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction); 609 void TMR_ConfigForcedOC4(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction); 610 void TMR_ConfigOC1Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload); 611 void TMR_ConfigOC2Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload); 612 void TMR_ConfigOC3Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload); 613 void TMR_ConfigOC4Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload); 614 void TMR_ConfigOC1Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast); 615 void TMR_ConfigOC2Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast); 616 void TMR_ConfigOC3Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast); 617 void TMR_ConfigOC4Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast); 618 void TMR_ClearOC1Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear); 619 void TMR_ClearOC2Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear); 620 void TMR_ClearOC3Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear); 621 void TMR_ClearOC4Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear); 622 void TMR_ConfigOC1Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity); 623 void TMR_ConfigOC1NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity); 624 void TMR_ConfigOC2Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity); 625 void TMR_ConfigOC2NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity); 626 void TMR_ConfigOC3Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity); 627 void TMR_ConfigOC3NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T OCNPolarity); 628 void TMR_ConfigOC4Polarity(TMR_T* tmr, TMR_OC_POLARITY_T OCPolarity); 629 void TMR_EnableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel); 630 void TMR_DisableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel); 631 void TMR_EnableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel); 632 void TMR_DisableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel); 633 634 /* Input Capture */ 635 void TMR_ConfigIC(TMR_T* tmr, TMR_ICConfig_T* ICConfig); 636 void TMR_ConfigICStructInit(TMR_ICConfig_T* ICConfig); 637 void TMR_ConfigPWM(TMR_T* tmr, TMR_ICConfig_T* PWMConfig); 638 uint32_t TMR_ReadCaputer1(TMR_T* tmr); 639 uint32_t TMR_ReadCaputer2(TMR_T* tmr); 640 uint32_t TMR_ReadCaputer3(TMR_T* tmr); 641 uint32_t TMR_ReadCaputer4(TMR_T* tmr); 642 void TMR_ConfigIC1Prescaler(TMR_T* tmr, TMR_IC_PSC_T prescaler); 643 void TMR_ConfigIC2Prescaler(TMR_T* tmr, TMR_IC_PSC_T prescaler); 644 void TMR_ConfigIC3Prescaler(TMR_T* tmr, TMR_IC_PSC_T prescaler); 645 void TMR_ConfigIC4Prescaler(TMR_T* tmr, TMR_IC_PSC_T prescaler); 646 647 /* Advanced-control timers (TMR1 and TMR8) specific features */ 648 void TMR_ConfigBDT(TMR_T* tmr, TMR_BDTConfig_T* BDTConfig); 649 void TMR_ConfigBDTStructInit( TMR_BDTConfig_T* BDTConfig); 650 void TMR_EnablePWMOutputs(TMR_T* tmr); 651 void TMR_DisablePWMOutputs(TMR_T* tmr); 652 void TMR_EnableSelectCOM(TMR_T* tmr); 653 void TMR_DisableSelectCOM(TMR_T* tmr); 654 void TMR_EnableCCPreload(TMR_T* tmr); 655 void TMR_DisableCCPreload(TMR_T* tmr); 656 657 /* DMA management */ 658 void TMR_ConfigDMA(TMR_T* tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength); 659 void TMR_EnableDMASoure(TMR_T* tmr, uint16_t dmaSource); 660 void TMR_DisableDMASoure(TMR_T* tmr, uint16_t dmaSource); 661 void TMR_EnableCCDMA(TMR_T* tmr); 662 void TMR_DisableCCDMA(TMR_T* tmr); 663 664 /* Clocks management */ 665 void TMR_ConfigInternalClock(TMR_T* tmr); 666 void TMR_ConfigIntTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource); 667 void TMR_ConfigTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource, 668 TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter); 669 void TMR_ConfigETRClockMode1(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler, 670 TMR_EXTTRG_POL_T polarity, uint16_t filter); 671 void TMR_ConfigETRClockMode2(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler, 672 TMR_EXTTRG_POL_T polarity, uint16_t filter); 673 674 /* Synchronization management */ 675 void TMR_SelectInputTrigger(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource); 676 void TMR_SelectOutputTrigger(TMR_T* tmr, TMR_TRGO_SOURCE_T TRGOSource); 677 void TMR_SelectSlaveMode(TMR_T* tmr, TMR_SLAVE_MODE_T slaveMode); 678 void TMR_EnableMasterSlaveMode(TMR_T* tmr); 679 void TMR_DisableMasterSlaveMode(TMR_T* tmr); 680 void TMR_ConfigETR(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler, 681 TMR_EXTTRG_POL_T polarity, uint16_t filter); 682 683 /* Interface */ 684 void TMR_ConfigEncodeInterface(TMR_T* tmr, TMR_ENCODER_MODE_T encodeMode, \ 685 TMR_IC_POLARITY_T IC1Polarity,TMR_IC_POLARITY_T IC2Polarity); 686 void TMR_EnableHallSensor(TMR_T* tmr); 687 void TMR_DisableHallSensor(TMR_T* tmr); 688 689 /* Remapping */ 690 void TMR_ConfigRemap(TMR_T* tmr, uint32_t remap); 691 692 /* Interrupts and flags */ 693 void TMR_EnableInterrupt(TMR_T* tmr, uint16_t interrupt); 694 void TMR_DisableInterrupt(TMR_T* tmr, uint16_t interrupt); 695 void TMR_GenerateEvent(TMR_T* tmr, uint16_t eventSources); 696 uint16_t TMR_ReadStatusFlag(TMR_T* tmr, TMR_FLAG_T flag); 697 void TMR_ClearStatusFlag(TMR_T* tmr, uint16_t flag); 698 uint16_t TMR_ReadIntFlag(TMR_T* tmr, TMR_INT_T flag); 699 void TMR_ClearIntFlag(TMR_T* tmr, uint16_t flag); 700 701 #ifdef __cplusplus 702 } 703 #endif 704 705 #endif /*__APM32F4XX_TMR_H */ 706 707 /**@} end of group TMR_Enumerations */ 708 /**@} end of group TMR_Driver */ 709 /**@} end of group APM32F4xx_StdPeriphDriver */ 710