1 /*!
2 * @file apm32f4xx_rcm.c
3 *
4 * @brief This file provides all the RCM firmware functions
5 *
6 * @version V1.0.2
7 *
8 * @date 2022-06-23
9 *
10 * @attention
11 *
12 * Copyright (C) 2021-2022 Geehy Semiconductor
13 *
14 * You may not use this file except in compliance with the
15 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
16 *
17 * The program is only for reference, which is distributed in the hope
18 * that it will be usefull and instructional for customers to develop
19 * their software. Unless required by applicable law or agreed to in
20 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
21 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
23 * and limitations under the License.
24 */
25
26 #include "apm32f4xx_rcm.h"
27
28 /** @addtogroup APM32F4xx_StdPeriphDriver
29 @{
30 */
31
32 /** @defgroup RCM_Driver
33 * @brief RCM driver modules
34 @{
35 */
36
37 /** @defgroup RCM_Functions
38 @{
39 */
40
41 /*!
42 * @brief Resets the clock configuration to the default state
43 *
44 * @param None
45 *
46 * @retval None
47 */
RCM_Reset(void)48 void RCM_Reset(void)
49 {
50 /* Open HSI clock */
51 RCM->CTRL_B.HSIEN = BIT_SET;
52 /* Clear CFG register */
53 RCM->CFG = (uint32_t)0x00000000;
54 /* Reset HSEON, CSSON, PLLON, PLLI2S bits */
55 RCM->CTRL &= (uint32_t)0xEAF6FFFF;
56
57 /* Reset PLL1CFG register */
58 RCM->PLL1CFG = 0x24003010;
59 /* Reset PLL2CFG register */
60 RCM->PLL2CFG = 0x20003000;
61
62 /* Reset HSEBCFG bit */
63 RCM->CTRL_B.HSEBCFG = BIT_RESET;
64
65 /* Disable all interrupts and clear pending bits */
66 RCM->INT = 0x00000000;
67 }
68
69 /*!
70 * @brief Configs the HSE oscillator
71 *
72 * @param state: state of the HSE
73 * This parameter can be one of the following values:
74 * @arg RCM_HSE_CLOSE : Turn off the HSE oscillator
75 * @arg RCM_HSE_OPEN : Turn on the HSE oscillator
76 * @arg RCM_HSE_BYPASS : HSE oscillator bypassed with external clock
77 *
78 * @retval None
79 *
80 * @note When HSE is not used directly or through the PLL as system clock, it can be stopped.
81 */
RCM_ConfigHSE(RCM_HSE_T state)82 void RCM_ConfigHSE(RCM_HSE_T state)
83 {
84 /* Reset HSEEN bit */
85 RCM->CTRL_B.HSEEN = BIT_RESET;
86
87 /* Reset HSEBCFG bit */
88 RCM->CTRL_B.HSEBCFG = BIT_RESET;
89
90 if (state == RCM_HSE_OPEN)
91 {
92 RCM->CTRL_B.HSEEN = BIT_SET;
93 }
94 else if (state == RCM_HSE_BYPASS)
95 {
96 RCM->CTRL_B.HSEBCFG = BIT_SET;
97 RCM->CTRL_B.HSEEN = BIT_SET;
98 }
99 }
100
101 /*!
102 * @brief Waits for HSE to be ready
103 *
104 * @param None
105 *
106 * @retval SUCCESS: HSE oscillator is ready
107 * ERROR : HSE oscillator is not ready
108 */
109
RCM_WaitHSEReady(void)110 uint8_t RCM_WaitHSEReady(void)
111 {
112 __IO uint32_t cnt;
113
114 for (cnt = 0; cnt < HSE_STARTUP_TIMEOUT; cnt++)
115 {
116 if (RCM->CTRL_B.HSERDYFLG == BIT_SET)
117 {
118 return SUCCESS;
119 }
120 }
121
122 return ERROR;
123 }
124
125 /*!
126 * @brief Config HSI trimming value
127 *
128 * @param HSITrim: HSI trimming value
129 * This parameter must be a number between 0 and 0x1F.
130 *
131 * @retval None
132 */
RCM_ConfigHSITrim(uint8_t HSITrim)133 void RCM_ConfigHSITrim(uint8_t HSITrim)
134 {
135 RCM->CTRL_B.HSITRIM = HSITrim;
136 }
137
138 /*!
139 * @brief Enable the HSI
140 *
141 * @param None
142 *
143 * @retval None
144 */
RCM_EnableHSI(void)145 void RCM_EnableHSI(void)
146 {
147 RCM->CTRL_B.HSIEN = BIT_SET;
148 }
149
150 /*!
151 * @brief Disable the HSI
152 *
153 * @param None
154 *
155 * @retval None
156 *
157 * @note When HSI is not used directly or through the PLL as system clock, it can be stopped.
158 */
159
RCM_DisableHSI(void)160 void RCM_DisableHSI(void)
161 {
162 RCM->CTRL_B.HSIEN = BIT_RESET;
163 }
164
165 /*!
166 * @brief Configures the External Low Speed oscillator (LSE)
167 *
168 * @param state : Specifies the new state of the LSE
169 * This parameter can be one of the following values:
170 * @arg RCM_LSE_CLOSE : Close the LSE
171 * @arg RCM_LSE_OPEN : Open the LSE
172 * @arg RCM_LSE_BYPASS : LSE bypass
173 *
174 * @retval None
175 */
RCM_ConfigLSE(RCM_LSE_T state)176 void RCM_ConfigLSE(RCM_LSE_T state)
177 {
178 RCM->BDCTRL_B.LSEEN = BIT_RESET;
179 RCM->BDCTRL_B.LSEBCFG = BIT_RESET;
180
181 if (state == RCM_LSE_OPEN)
182 {
183 RCM->BDCTRL_B.LSEEN = BIT_SET;
184 }
185 else if (state == RCM_LSE_BYPASS)
186 {
187 RCM->BDCTRL_B.LSEBCFG = BIT_SET;
188 RCM->BDCTRL_B.LSEEN = BIT_SET;
189 }
190 }
191
192 /*!
193 * @brief Enables the Internal Low Speed oscillator (LSI)
194 *
195 * @param None
196 *
197 * @retval None
198 */
RCM_EnableLSI(void)199 void RCM_EnableLSI(void)
200 {
201 RCM->CSTS_B.LSIEN = BIT_SET;
202 }
203
204 /*!
205 * @brief Disables the Internal Low Speed oscillator (LSI)
206 *
207 * @param None
208 *
209 * @retval None
210 */
RCM_DisableLSI(void)211 void RCM_DisableLSI(void)
212 {
213 RCM->CSTS_B.LSIEN = BIT_RESET;
214 }
215
216 /*!
217 * @brief Configures the main PLL clock source, multiplication and division factors
218 *
219 * @param pllSelect: PLL entry clock source select
220 * This parameter can be one of the following values:
221 * @arg RCM_PLLSEL_HSI: HSI oscillator clock selected as PLL clock entry
222 * @arg RCM_PLLSEL_HSE: HSE oscillator clock selected as PLL clock entry
223 *
224 * @param inputDiv: specifies the Division factor for PLL VCO input clock
225 * This parameter must be a number between 0 and 63
226 *
227 * @param vcoMul: specifies the Multiplication factor for PLL VCO output clock
228 * This parameter must be a number between 50 and 432
229 *
230 * @param sysDiv: specifies the Division factor for main system clock (SYSCLK)
231 * This parameter can be one of the following values:
232 * @arg RCM_PLL_SYS_DIV_2 : system clock Division factor is 2
233 * @arg RCM_PLL_SYS_DIV_4 : system clock Division factor is 4
234 * @arg RCM_PLL_SYS_DIV_6 : system clock Division factor is 6
235 * @arg RCM_PLL_SYS_DIV_8 : system clock Division factor is 8
236 *
237 * @param appDiv: specifies the Division factor for OTG FS, SDIO and RNG clocks
238 * This parameter must be a number between 4 and 15
239 *
240 * @retval None
241 */
RCM_ConfigPLL1(uint32_t pllSelect,uint32_t inputDiv,uint32_t vcoMul,RCM_PLL_SYS_DIV_T sysDiv,uint32_t appDiv)242 void RCM_ConfigPLL1(uint32_t pllSelect, uint32_t inputDiv, uint32_t vcoMul,
243 RCM_PLL_SYS_DIV_T sysDiv, uint32_t appDiv)
244 {
245 RCM->PLL1CFG_B.PLL1CLKS = pllSelect;
246 RCM->PLL1CFG_B.PLLB = inputDiv;
247 RCM->PLL1CFG_B.PLL1A = vcoMul;
248 RCM->PLL1CFG_B.PLL1C = sysDiv;
249 RCM->PLL1CFG_B.PLLD = appDiv;
250 }
251
252 /*!
253 * @brief Enables the PLL1
254 *
255 * @param None
256 *
257 * @retval None
258 */
RCM_EnablePLL1(void)259 void RCM_EnablePLL1(void)
260 {
261 RCM->CTRL_B.PLL1EN = BIT_SET;
262 }
263
264 /*!
265 * @brief Disable the PLL
266 *
267 * @param None
268 *
269 * @retval None
270 *
271 * @note When PLL1 is not used as system clock, it can be stopped.
272 */
RCM_DisablePLL1(void)273 void RCM_DisablePLL1(void)
274 {
275 RCM->CTRL_B.PLL1EN = BIT_RESET;
276 }
277
278 /*!
279 * @brief Configures the RCM_PLL2CFG register
280 *
281 * @param i2sVcoMul: specifies the multiplication factor for PLLI2S VCO output clock
282 * This parameter must be a number between 50 and 432
283 *
284 * @param i2sDiv: specifies the division factor for I2S clock
285 * This parameter must be a number between 2 and 7
286 *
287 * @retval None
288 */
RCM_ConfigPLL2(uint32_t i2sVcoMul,uint32_t i2sDiv)289 void RCM_ConfigPLL2(uint32_t i2sVcoMul, uint32_t i2sDiv)
290 {
291 RCM->PLL2CFG_B.PLL2A = i2sVcoMul;
292 RCM->PLL2CFG_B.PLL2C = i2sDiv;
293 }
294
295 /*!
296 * @brief Enables the PLL2
297 *
298 * @param None
299 *
300 * @retval None
301 */
RCM_EnablePLL2(void)302 void RCM_EnablePLL2(void)
303 {
304 RCM->CTRL_B.PLL2EN = BIT_SET;
305 }
306
307 /*!
308 * @brief Disable the PLL2
309 *
310 * @param None
311 *
312 * @retval None
313 */
RCM_DisablePLL2(void)314 void RCM_DisablePLL2(void)
315 {
316 RCM->CTRL_B.PLL2EN = BIT_RESET;
317 }
318
319 /*!
320 * @brief Enable the Clock Security System
321 *
322 * @param None
323 *
324 * @retval None
325 */
RCM_EnableCSS(void)326 void RCM_EnableCSS(void)
327 {
328 RCM->CTRL_B.CSSEN = BIT_SET;
329 }
330
331 /*!
332 * @brief Disable the Clock Security System
333 *
334 * @param None
335 *
336 * @retval None
337 */
RCM_DisableCSS(void)338 void RCM_DisableCSS(void)
339 {
340 RCM->CTRL_B.CSSEN = BIT_RESET;
341 }
342
343 /*!
344 * @brief Selects the clock source to output on MCO1 pin
345 *
346 * @param mco1Div: specifies the clock source to output
347 * This parameter can be one of the following values:
348 * @arg RCM_MCO1_SEL_HSICLK : HSI clock selected as MCO1 source
349 * @arg RCM_MCO1_SEL_LSECLK : LSE clock selected as MCO1 source
350 * @arg RCM_MCO1_SEL_HSECLK : HSE clock selected as MCO1 source
351 * @arg RCM_MCO1_SEL_PLLCLK : main PLL clock selected as MCO1 source
352 *
353 * @param mco1Div: specifies the MCO1 prescaler
354 * This parameter can be one of the following values:
355 * @arg RCM_MCO1_DIV_1 : no division applied to MCO1 clock
356 * @arg RCM_MCO1_DIV_2 : division by 2 applied to MCO1 clock
357 * @arg RCM_MCO1_DIV_3 : division by 3 applied to MCO1 clock
358 * @arg RCM_MCO1_DIV_4 : division by 4 applied to MCO1 clock
359 * @arg RCM_MCO1_DIV_5 : division by 5 applied to MCO1 clock
360 *
361 * @retval None
362 */
RCM_ConfigMCO1(RCM_MCO1_SEL_T mco1Select,RCM_MCO1_DIV_T mco1Div)363 void RCM_ConfigMCO1(RCM_MCO1_SEL_T mco1Select, RCM_MCO1_DIV_T mco1Div)
364 {
365 RCM->CFG_B.MCO1SEL = mco1Select;
366 RCM->CFG_B.MCO1PRE = mco1Div;
367 }
368
369 /*!
370 * @brief Selects the clock source to output on MCO2 pin
371 *
372 * @param mco2Select: specifies the clock source to output
373 * This parameter can be one of the following values:
374 * @arg RCM_MCO2_SEL_SYSCLK : SYS clock selected as MCO2 source
375 * @arg RCM_MCO2_SEL_PLL2CLK : PLL2 clock selected as MCO2 source
376 * @arg RCM_MCO2_SEL_HSECLK : HSE clock selected as MCO2 source
377 * @arg RCM_MCO2_SEL_PLLCLK : PLL clock selected as MCO2 source
378 *
379 * @param mco2Div: specifies the MCO2 prescaler
380 * This parameter can be one of the following values:
381 * @arg RCM_MCO2_DIV_1 : no division applied to MCO2 clock
382 * @arg RCM_MCO2_DIV_2 : division by 2 applied to MCO2 clock
383 * @arg RCM_MCO2_DIV_3 : division by 3 applied to MCO2 clock
384 * @arg RCM_MCO2_DIV_4 : division by 4 applied to MCO2 clock
385 * @arg RCM_MCO2_DIV_5 : division by 5 applied to MCO2 clock
386 *
387 * @retval None
388 */
RCM_ConfigMCO2(RCM_MCO2_SEL_T mco2Select,RCM_MCO2_DIV_T mco2Div)389 void RCM_ConfigMCO2(RCM_MCO2_SEL_T mco2Select, RCM_MCO2_DIV_T mco2Div)
390 {
391 RCM->CFG_B.MCO2SEL = mco2Select;
392 RCM->CFG_B.MCO2PRE = mco2Div;
393 }
394
395 /*!
396 * @brief Configures the system clock source
397 *
398 * @param sysClkSelect: specifies the clock source used as system clock
399 * This parameter can be one of the following values:
400 * @arg RCM_SYSCLK_SEL_HSI : HSI is selected as system clock source
401 * @arg RCM_SYSCLK_SEL_HSE : HSE is selected as system clock source
402 * @arg RCM_SYSCLK_SEL_PLL : PLL is selected as system clock source
403 *
404 * @retva None
405 */
RCM_ConfigSYSCLK(RCM_SYSCLK_SEL_T sysClkSelect)406 void RCM_ConfigSYSCLK(RCM_SYSCLK_SEL_T sysClkSelect)
407 {
408 RCM->CFG_B.SCLKSEL = sysClkSelect;
409 }
410
411 /*!
412 * @brief Returns the clock source which is used as system clock
413 *
414 * @param None
415 *
416 * @retval The clock source used as system clock
417 */
RCM_ReadSYSCLKSource(void)418 RCM_SYSCLK_SEL_T RCM_ReadSYSCLKSource(void)
419 {
420 return (RCM_SYSCLK_SEL_T)RCM->CFG_B.SCLKSWSTS;
421 }
422
423 /*!
424 * @brief Configs the AHB clock prescaler.
425 *
426 * @param AHBDiv : Specifies the AHB clock prescaler from the system clock.
427 * This parameter can be one of the following values:
428 * @arg RCM_AHB_DIV_1 : HCLK = SYSCLK
429 * @arg RCM_AHB_DIV_2 : HCLK = SYSCLK / 2
430 * @arg RCM_AHB_DIV_4 : HCLK = SYSCLK / 4
431 * @arg RCM_AHB_DIV_8 : HCLK = SYSCLK / 8
432 * @arg RCM_AHB_DIV_16 : HCLK = SYSCLK / 16
433 * @arg RCM_AHB_DIV_64 : HCLK = SYSCLK / 64
434 * @arg RCM_AHB_DIV_128 : HCLK = SYSCLK / 128
435 * @arg RCM_AHB_DIV_256 : HCLK = SYSCLK / 256
436 * @arg RCM_AHB_DIV_512 : HCLK = SYSCLK / 512
437 *
438 * @retval None
439 */
RCM_ConfigAHB(RCM_AHB_DIV_T AHBDiv)440 void RCM_ConfigAHB(RCM_AHB_DIV_T AHBDiv)
441 {
442 RCM->CFG_B.AHBPSC = AHBDiv;
443 }
444
445 /*!
446 * @brief Configs the APB1 clock prescaler.
447 *
448 * @param APB1Div: Specifies the APB1 clock prescaler from the AHB clock.
449 * This parameter can be one of the following values:
450 * @arg RCM_APB_DIV_1 : PCLK1 = HCLK
451 * @arg RCM_APB_DIV_2 : PCLK1 = HCLK / 2
452 * @arg RCM_APB_DIV_4 : PCLK1 = HCLK / 4
453 * @arg RCM_APB_DIV_8 : PCLK1 = HCLK / 8
454 * @arg RCM_APB_DIV_16 : PCLK1 = HCLK / 16
455 *
456 * @retval None
457 */
RCM_ConfigAPB1(RCM_APB_DIV_T APB1Div)458 void RCM_ConfigAPB1(RCM_APB_DIV_T APB1Div)
459 {
460 RCM->CFG_B.APB1PSC = APB1Div;
461 }
462
463 /*!
464 * @brief Configs the APB2 clock prescaler
465 *
466 * @param APB2Div: Specifies the APB2 clock prescaler from the AHB clock.
467 * This parameter can be one of the following values:
468 * @arg RCM_APB_DIV_1 : PCLK2 = HCLK
469 * @arg RCM_APB_DIV_2 : PCLK2 = HCLK / 2
470 * @arg RCM_APB_DIV_4 : PCLK2 = HCLK / 4
471 * @arg RCM_APB_DIV_8 : PCLK2 = HCLK / 8
472 * @arg RCM_APB_DIV_16 : PCLK2 = HCLK / 16
473 *
474 * @retval None
475 */
RCM_ConfigAPB2(RCM_APB_DIV_T APB2Div)476 void RCM_ConfigAPB2(RCM_APB_DIV_T APB2Div)
477 {
478 RCM->CFG_B.APB2PSC = APB2Div;
479 }
480
481 /*!
482 * @brief Configs the SDRAM clock prescaler
483 *
484 * @param SDRAMDiv: Specifies the SDRAM clock prescaler from the DMC clock.
485 * This parameter can be one of the following values:
486 * @arg RCM_SDRAM_DIV_1 : SDRAM clock = DMC clock
487 * @arg RCM_SDRAM_DIV_2 : SDRAM clock = DMC clock / 2
488 * @arg RCM_SDRAM_DIV_4 : SDRAM clock = DMC clock / 4
489 *
490 * @retval None
491 */
RCM_ConfigSDRAM(RCM_SDRAM_DIV_T SDRAMDiv)492 void RCM_ConfigSDRAM(RCM_SDRAM_DIV_T SDRAMDiv)
493 {
494 RCM->CFG_B.SDRAMPSC = SDRAMDiv;
495 }
496
497 /*!
498 * @brief Reads the frequency of SYSCLK
499 *
500 * @param None
501 *
502 * @retval Return the frequency of SYSCLK
503 */
RCM_ReadSYSCLKFreq(void)504 uint32_t RCM_ReadSYSCLKFreq(void)
505 {
506 uint32_t sysClock, pllMull, pllSource, pllvco;
507
508 /* get sys clock */
509 sysClock = RCM->CFG_B.SCLKSWSTS;
510
511 switch (sysClock)
512 {
513 /* sys clock is HSI */
514 case RCM_SYSCLK_SEL_HSI:
515 sysClock = HSI_VALUE;
516 break;
517
518 /* sys clock is HSE */
519 case RCM_SYSCLK_SEL_HSE:
520 sysClock = HSE_VALUE;
521 break;
522
523 /* sys clock is PLL */
524 case RCM_SYSCLK_SEL_PLL:
525 pllMull = RCM->PLL1CFG_B.PLLB;
526 pllSource = RCM->PLL1CFG_B.PLL1CLKS;
527
528 /* PLL entry clock source is HSE */
529 if (pllSource == BIT_SET)
530 {
531 /* HSE used as PLL clock source */
532 pllvco = (HSE_VALUE / pllMull) * (RCM->PLL1CFG_B.PLL1A);
533 }
534 else
535 {
536 /* HSI used as PLL clock source */
537 pllvco = (HSI_VALUE / pllMull) * (RCM->PLL1CFG_B.PLL1A);
538 }
539
540 sysClock = pllvco / ((RCM->PLL1CFG_B.PLL1C + 1) * 2);
541 break;
542
543 default:
544 sysClock = HSI_VALUE;
545 break;
546 }
547
548 return sysClock;
549 }
550
551 /*!
552 * @brief Reads the frequency of HCLK(AHB)
553 *
554 * @param None
555 *
556 * @retval Return the frequency of HCLK
557 */
RCM_ReadHCLKFreq(void)558 uint32_t RCM_ReadHCLKFreq(void)
559 {
560 uint32_t divider;
561 uint32_t sysClk, hclk;
562 uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
563
564 sysClk = RCM_ReadSYSCLKFreq();
565 divider = AHBPrescTable[RCM->CFG_B.AHBPSC];
566 hclk = sysClk >> divider;
567
568 return hclk;
569 }
570
571 /*!
572 * @brief Reads the frequency of PCLK1 And PCLK2
573 *
574 * @param PCLK1 : Return the frequency of PCLK1
575 *
576 * @param PCLK1 : Return the frequency of PCLK2
577 *
578 * @retval None
579 */
RCM_ReadPCLKFreq(uint32_t * PCLK1,uint32_t * PCLK2)580 void RCM_ReadPCLKFreq(uint32_t *PCLK1, uint32_t *PCLK2)
581 {
582 uint32_t hclk, divider;
583 uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
584
585 hclk = RCM_ReadHCLKFreq();
586
587 if (PCLK1)
588 {
589 divider = APBPrescTable[RCM->CFG_B.APB1PSC];
590 *PCLK1 = hclk >> divider;
591 }
592
593 if (PCLK2)
594 {
595 divider = APBPrescTable[RCM->CFG_B.APB2PSC];
596 *PCLK2 = hclk >> divider;
597 }
598 }
599
600 /*!
601 * @brief Configures the RTC clock source
602 *
603 * @param rtcClkSelect : specifies the RTC clock source.
604 * This parameter can be one of the following values:
605 * @arg RCM_RTCCLK_LSE : RTCCLK = LSE clock
606 * @arg RCM_RTCCLK_LSI : RTCCLK = LSI clock
607 * @arg RCM_RTCCLK_HSE_DIVX : X:[2:31]
608 *
609 * @retval None
610 */
RCM_ConfigRTCCLK(RCM_RTCCLK_T rtcClkSelect)611 void RCM_ConfigRTCCLK(RCM_RTCCLK_T rtcClkSelect)
612 {
613 if (rtcClkSelect <= 1)
614 {
615 RCM->BDCTRL_B.RTCSRCSEL = (rtcClkSelect + 1);
616 }
617
618 else
619 {
620 RCM->BDCTRL_B.RTCSRCSEL = 3;
621 RCM->CFG_B.RTCPSC = rtcClkSelect;
622 }
623 }
624
625 /*!
626 * @brief Enables the RTC clock
627 *
628 * @param None
629 *
630 * @retval None
631 */
RCM_EnableRTCCLK(void)632 void RCM_EnableRTCCLK(void)
633 {
634 RCM->BDCTRL_B.RTCCLKEN = BIT_SET;
635 }
636
637 /*!
638 * @brief Disables the RTC clock
639 *
640 * @param None
641 *
642 * @retval None
643 */
RCM_DisableRTCCLK(void)644 void RCM_DisableRTCCLK(void)
645 {
646 RCM->BDCTRL_B.RTCCLKEN = BIT_RESET;
647 }
648 /*!
649 * @brief Enable the Backup domain reset
650 *
651 * @param None
652 *
653 * @retval None
654 *
655 * @note
656 */
RCM_EnableBackupReset(void)657 void RCM_EnableBackupReset(void)
658 {
659 RCM->BDCTRL_B.BDRST = BIT_SET;
660 }
661
662 /*!
663 * @brief Disable the Backup domain reset
664 *
665 * @param None
666 *
667 * @retval None
668 */
RCM_DisableBackupReset(void)669 void RCM_DisableBackupReset(void)
670 {
671 RCM->BDCTRL_B.BDRST = BIT_RESET;
672 }
673
674 /*!
675 * @brief Configures the I2S clock source (I2SCLK)
676 *
677 * @param i2sClkSource: specifies the I2S clock source
678 * This parameter can be one of the following values:
679 * @arg RCM_I2S_CLK_PLLI2S : PLLI2S is selected as I2S clock source
680 * @arg RCM_I2S_CLK_EXT : EXT is selected as I2S clock source
681 *
682 * @retval None
683 */
RCM_ConfigI2SCLK(RCM_I2S_CLK_T i2sClkSource)684 void RCM_ConfigI2SCLK(RCM_I2S_CLK_T i2sClkSource)
685 {
686 RCM->CFG_B.I2SSEL = i2sClkSource;
687 }
688
689 /*!
690 * @brief Enables AHB1 peripheral clock
691 *
692 * @param AHB1Periph : Enable the specifies clock of AHB peripheral
693 * This parameter can be any combination of the following values:
694 * @arg RCM_AHB1_PERIPH_GPIOA : Enable GPIOA clock
695 * @arg RCM_AHB1_PERIPH_GPIOB : Enable GPIOB clock
696 * @arg RCM_AHB1_PERIPH_GPIOC : Enable GPIOC clock
697 * @arg RCM_AHB1_PERIPH_GPIOD : Enable GPIOD clock
698 * @arg RCM_AHB1_PERIPH_GPIOE : Enable GPIOE clock
699 * @arg RCM_AHB1_PERIPH_GPIOF : Enable GPIOF clock
700 * @arg RCM_AHB1_PERIPH_GPIOG : Enable GPIOG clock
701 * @arg RCM_AHB1_PERIPH_GPIOI : Enable GPIOI clock
702 * @arg RCM_AHB1_PERIPH_CRC : Enable CRC clock
703 * @arg RCM_AHB1_PERIPH_BKPSRAM : Enable BKPSRAM interface clock
704 * @arg RCM_AHB1_PERIPH_CCMDATARAMEN: Enable CCM data RAM interface clock
705 * @arg RCM_AHB1_PERIPH_DMA1 : Enable DMA1 clock
706 * @arg RCM_AHB1_PERIPH_DMA2 : Enable DMA2 clock
707 * @arg RCM_AHB1_PERIPH_ETH_MAC : Enable Ethernet MAC clock
708 * @arg RCM_AHB1_PERIPH_ETH_MAC_Tx : Enable Ethernet Transmission clock
709 * @arg RCM_AHB1_PERIPH_ETH_MAC_Rx : Enable Ethernet Reception clock
710 * @arg RCM_AHB1_PERIPH_ETH_MAC_PTP : Enable Ethernet PTP clock
711 * @arg RCM_AHB1_PERIPH_OTG_HS : Enable USB OTG HS clock
712 * @arg RCM_AHB1_PERIPH_OTG_HS_ULPI : Enable USB OTG HS ULPI clock
713 *
714 * @retval None
715 */
RCM_EnableAHB1PeriphClock(uint32_t AHB1Periph)716 void RCM_EnableAHB1PeriphClock(uint32_t AHB1Periph)
717 {
718 RCM->AHB1CLKEN |= AHB1Periph;
719 }
720
721 /*!
722 * @brief Disable AHB1 peripheral clock
723 *
724 * @param AHB1Periph : Disable the specifies clock of AHB1 peripheral
725 * This parameter can be any combination of the following values:
726 * @arg RCM_AHB1_PERIPH_GPIOA : Disable GPIOA clock
727 * @arg RCM_AHB1_PERIPH_GPIOB : Disable GPIOB clock
728 * @arg RCM_AHB1_PERIPH_GPIOC : Disable GPIOC clock
729 * @arg RCM_AHB1_PERIPH_GPIOD : Disable GPIOD clock
730 * @arg RCM_AHB1_PERIPH_GPIOE : Disable GPIOE clock
731 * @arg RCM_AHB1_PERIPH_GPIOF : Disable GPIOF clock
732 * @arg RCM_AHB1_PERIPH_GPIOG : Disable GPIOG clock
733 * @arg RCM_AHB1_PERIPH_GPIOI : Disable GPIOI clock
734 * @arg RCM_AHB1_PERIPH_CRC : Disable CRC clock
735 * @arg RCM_AHB1_PERIPH_BKPSRAM : Disable BKPSRAM interface clock
736 * @arg RCM_AHB1_PERIPH_CCMDATARAMEN: Disable CCM data RAM interface clock
737 * @arg RCM_AHB1_PERIPH_DMA1 : Disable DMA1 clock
738 * @arg RCM_AHB1_PERIPH_DMA2 : Disable DMA2 clock
739 * @arg RCM_AHB1_PERIPH_ETH_MAC : Disable Ethernet MAC clock
740 * @arg RCM_AHB1_PERIPH_ETH_MAC_Tx : Disable Ethernet Transmission clock
741 * @arg RCM_AHB1_PERIPH_ETH_MAC_Rx : Disable Ethernet Reception clock
742 * @arg RCM_AHB1_PERIPH_ETH_MAC_PTP : Disable Ethernet PTP clock
743 * @arg RCM_AHB1_PERIPH_OTG_HS : Disable USB OTG HS clock
744 * @arg RCM_AHB1_PERIPH_OTG_HS_ULPI : Disable USB OTG HS ULPI clock
745 *
746 * @retval None
747 */
RCM_DisableAHB1PeriphClock(uint32_t AHB1Periph)748 void RCM_DisableAHB1PeriphClock(uint32_t AHB1Periph)
749 {
750 RCM->AHB1CLKEN &= (uint32_t)~AHB1Periph;
751 }
752
753 /*!
754 * @brief Enables AHB2 peripheral clock
755 *
756 * @param AHB2Periph : Enable the specifies clock of AHB2 peripheral
757 * This parameter can be any combination of the following values:
758 * @arg RCM_AHB2_PERIPH_DCI : Enable DCI clock
759 * @arg RCM_AHB2_PERIPH_FPU : Enable FPU clock
760 * @arg RCM_AHB2_PERIPH_BN : Enable BN clock
761 * @arg RCM_AHB2_PERIPH_SM : Enable SM clock
762 * @arg RCM_AHB2_PERIPH_CRYP : Enable CRYP clock
763 * @arg RCM_AHB2_PERIPH_HASH : Enable HASH clock
764 * @arg RCM_AHB2_PERIPH_RNG : Enable RNG clock
765 * @arg RCM_AHB2_PERIPH_OTG_FS : Enable OTG FS clock
766 *
767 * @retval None
768 */
RCM_EnableAHB2PeriphClock(uint32_t AHB2Periph)769 void RCM_EnableAHB2PeriphClock(uint32_t AHB2Periph)
770 {
771 RCM->AHB2CLKEN |= AHB2Periph;
772 }
773
774 /*!
775 * @brief Disable AHB2 peripheral clock
776 *
777 * @param AHB2Periph : Disable the specifies clock of AHB2 peripheral
778 * This parameter can be any combination of the following values:
779 * @arg RCM_AHB2_PERIPH_DCI : Disable DCI clock
780 * @arg RCM_AHB2_PERIPH_FPU : Disable FPU clock
781 * @arg RCM_AHB2_PERIPH_BN : Disable BN clock
782 * @arg RCM_AHB2_PERIPH_SM : Disable SM clock
783 * @arg RCM_AHB2_PERIPH_CRYP : Disable CRYP clock
784 * @arg RCM_AHB2_PERIPH_HASH : Disable HASH clock
785 * @arg RCM_AHB2_PERIPH_RNG : Disable RNG clock
786 * @arg RCM_AHB2_PERIPH_OTG_FS : Disable OTG FS clock
787 *
788 * @retval None
789 */
RCM_DisableAHB2PeriphClock(uint32_t AHB2Periph)790 void RCM_DisableAHB2PeriphClock(uint32_t AHB2Periph)
791 {
792 RCM->AHB2CLKEN &= (uint32_t)~AHB2Periph;
793 }
794
795 /*!
796 * @brief Enable the Low Speed APB (APB1) peripheral clock
797 *
798 * @param APB1Periph : Enable specifies clock of the APB1 peripheral.
799 * This parameter can be any combination of the following values:
800 * @arg RCM_APB1_PERIPH_TMR2 : Enable TMR2 clock
801 * @arg RCM_APB1_PERIPH_TMR3 : Enable TMR3 clock
802 * @arg RCM_APB1_PERIPH_TMR4 : Enable TMR4 clock
803 * @arg RCM_APB1_PERIPH_TMR5 : Enable TMR5 clock
804 * @arg RCM_APB1_PERIPH_TMR6 : Enable TMR6 clock
805 * @arg RCM_APB1_PERIPH_TMR7 : Enable TMR7 clock
806 * @arg RCM_APB1_PERIPH_TMR12 : Enable TMR12 clock
807 * @arg RCM_APB1_PERIPH_TMR13 : Enable TMR13 clock
808 * @arg RCM_APB1_PERIPH_TMR14 : Enable TMR14 clock
809 * @arg RCM_APB1_PERIPH_WWDT : Enable WWDT clock
810 * @arg RCM_APB1_PERIPH_SPI2 : Enable SPI2 clock
811 * @arg RCM_APB1_PERIPH_SPI3 : Enable SPI3 clock
812 * @arg RCM_APB1_PERIPH_USART2 : Enable USART2 clock
813 * @arg RCM_APB1_PERIPH_USART3 : Enable USART3 clock
814 * @arg RCM_APB1_PERIPH_UART4 : Enable UART4 clock
815 * @arg RCM_APB1_PERIPH_UART5 : Enable UART5 clock
816 * @arg RCM_APB1_PERIPH_I2C1 : Enable I2C1 clock
817 * @arg RCM_APB1_PERIPH_I2C2 : Enable I2C2 clock
818 * @arg RCM_APB1_PERIPH_I2C3 : Enable I2C3 clock
819 * @arg RCM_APB1_PERIPH_FMPI2C1: Enable FMPI2C1 clock
820 * @arg RCM_APB1_PERIPH_CAN1 : Enable CAN1 clock
821 * @arg RCM_APB1_PERIPH_CAN2 : Enable CAN2 clock
822 * @arg RCM_APB1_PERIPH_PMU : Enable PMU clock
823 * @arg RCM_APB1_PERIPH_DAC : Enable DAC clock
824 * @arg RCM_APB1_PERIPH_UART7 : Enable UART7 clock
825 * @arg RCM_APB1_PERIPH_UART8 : Enable UART8 clock
826 *
827 * @retval None
828 */
RCM_EnableAPB1PeriphClock(uint32_t APB1Periph)829 void RCM_EnableAPB1PeriphClock(uint32_t APB1Periph)
830 {
831 RCM->APB1CLKEN |= APB1Periph;
832 }
833
834 /*!
835 * @brief Disable the Low Speed APB (APB1) peripheral clock
836 *
837 * @param APB1Periph : Disable specifies clock of the APB1 peripheral.
838 * This parameter can be any combination of the following values:
839 * @arg RCM_APB1_PERIPH_TMR2 : Disable TMR2 clock
840 * @arg RCM_APB1_PERIPH_TMR3 : Disable TMR3 clock
841 * @arg RCM_APB1_PERIPH_TMR4 : Disable TMR4 clock
842 * @arg RCM_APB1_PERIPH_TMR5 : Disable TMR5 clock
843 * @arg RCM_APB1_PERIPH_TMR6 : Disable TMR6 clock
844 * @arg RCM_APB1_PERIPH_TMR7 : Disable TMR7 clock
845 * @arg RCM_APB1_PERIPH_TMR12 : Disable TMR12 clock
846 * @arg RCM_APB1_PERIPH_TMR13 : Disable TMR13 clock
847 * @arg RCM_APB1_PERIPH_TMR14 : Disable TMR14 clock
848 * @arg RCM_APB1_PERIPH_WWDT : Disable WWDT clock
849 * @arg RCM_APB1_PERIPH_SPI2 : Disable SPI2 clock
850 * @arg RCM_APB1_PERIPH_SPI3 : Disable SPI3 clock
851 * @arg RCM_APB1_PERIPH_USART2 : Disable USART2 clock
852 * @arg RCM_APB1_PERIPH_USART3 : Disable USART3 clock
853 * @arg RCM_APB1_PERIPH_UART4 : Disable UART4 clock
854 * @arg RCM_APB1_PERIPH_UART5 : Disable UART5 clock
855 * @arg RCM_APB1_PERIPH_I2C1 : Disable I2C1 clock
856 * @arg RCM_APB1_PERIPH_I2C2 : Disable I2C2 clock
857 * @arg RCM_APB1_PERIPH_I2C3 : Disable I2C3 clock
858 * @arg RCM_APB1_PERIPH_FMPI2C1: Disable FMPI2C1 clock
859 * @arg RCM_APB1_PERIPH_CAN1 : Disable CAN1 clock
860 * @arg RCM_APB1_PERIPH_CAN2 : Disable CAN2 clock
861 * @arg RCM_APB1_PERIPH_PMU : Disable PMU clock
862 * @arg RCM_APB1_PERIPH_DAC : Disable DAC clock
863 * @arg RCM_APB1_PERIPH_UART7 : Disable UART7 clock
864 * @arg RCM_APB1_PERIPH_UART8 : Disable UART8 clock
865 *
866 * @retval None
867 */
RCM_DisableAPB1PeriphClock(uint32_t APB1Periph)868 void RCM_DisableAPB1PeriphClock(uint32_t APB1Periph)
869 {
870 RCM->APB1CLKEN &= (uint32_t)~APB1Periph;
871 }
872
873 /*!
874 * @brief Enable the High Speed APB (APB2) peripheral clock
875 *
876 * @param APB2Periph : Enable specifies clock of the APB2 peripheral.
877 * This parameter can be any combination of the following values:
878 * @arg RCM_APB2_PERIPH_TMR1 : TMR1 clock
879 * @arg RCM_APB2_PERIPH_TMR8 : TMR8 clock
880 * @arg RCM_APB2_PERIPH_USART1 : USART1 clock
881 * @arg RCM_APB2_PERIPH_USART6 : USART6 clock
882 * @arg RCM_APB2_PERIPH_ADC1 : ADC1 clock
883 * @arg RCM_APB2_PERIPH_ADC2 : ADC2 clock
884 * @arg RCM_APB2_PERIPH_ADC3 : ADC3 clock
885 * @arg RCM_APB2_PERIPH_SDIO : SDIO clock
886 * @arg RCM_APB2_PERIPH_SPI1 : SPI1 clock
887 * @arg RCM_APB2_PERIPH_SPI4 : SPI4 clock
888 * @arg RCM_APB2_PERIPH_SYSCFG : SYSCFG clock
889 * @arg RCM_APB2_PERIPH_TMR9 : TMR9 clock
890 * @arg RCM_APB2_PERIPH_TMR10 : TMR10 clock
891 * @arg RCM_APB2_PERIPH_TMR11 : TMR11 clock
892 * @arg RCM_APB2_PERIPH_SPI5 : SPI5 clock
893 * @arg RCM_APB2_PERIPH_SPI6 : SPI6 clock
894 *
895 * @retval None
896 */
RCM_EnableAPB2PeriphClock(uint32_t APB2Periph)897 void RCM_EnableAPB2PeriphClock(uint32_t APB2Periph)
898 {
899 RCM->APB2CLKEN |= APB2Periph;
900 }
901
902 /*!
903 * @brief Disable the High Speed APB (APB2) peripheral clock
904 *
905 * @param APB2Periph : Disable specifies clock of the APB2 peripheral.
906 * This parameter can be any combination of the following values:
907 * @arg RCM_APB2_PERIPH_TMR1 : TMR1 clock
908 * @arg RCM_APB2_PERIPH_TMR8 : TMR8 clock
909 * @arg RCM_APB2_PERIPH_USART1 : USART1 clock
910 * @arg RCM_APB2_PERIPH_USART6 : USART6 clock
911 * @arg RCM_APB2_PERIPH_ADC1 : ADC1 clock
912 * @arg RCM_APB2_PERIPH_ADC2 : ADC2 clock
913 * @arg RCM_APB2_PERIPH_ADC3 : ADC3 clock
914 * @arg RCM_APB2_PERIPH_SDIO : SDIO clock
915 * @arg RCM_APB2_PERIPH_SPI1 : SPI1 clock
916 * @arg RCM_APB2_PERIPH_SPI4 : SPI4 clock
917 * @arg RCM_APB2_PERIPH_SYSCFG : SYSCFG clock
918 * @arg RCM_APB2_PERIPH_TMR9 : TMR9 clock
919 * @arg RCM_APB2_PERIPH_TMR10 : TMR10 clock
920 * @arg RCM_APB2_PERIPH_TMR11 : TMR11 clock
921 * @arg RCM_APB2_PERIPH_SPI5 : SPI5 clock
922 * @arg RCM_APB2_PERIPH_SPI6 : SPI6 clock
923 *
924 * @retval None
925 */
RCM_DisableAPB2PeriphClock(uint32_t APB2Periph)926 void RCM_DisableAPB2PeriphClock(uint32_t APB2Periph)
927 {
928 RCM->APB2CLKEN &= (uint32_t)~APB2Periph;
929 }
930
931 /*!
932 * @brief Enables AHB1 peripheral reset
933 *
934 * @param AHB1Periph : Enable the specifies reset of AHB peripheral
935 * This parameter can be any combination of the following values:
936 * @arg RCM_AHB1_PERIPH_GPIOA : Enable GPIOA reset
937 * @arg RCM_AHB1_PERIPH_GPIOB : Enable GPIOB reset
938 * @arg RCM_AHB1_PERIPH_GPIOC : Enable GPIOC reset
939 * @arg RCM_AHB1_PERIPH_GPIOD : Enable GPIOD reset
940 * @arg RCM_AHB1_PERIPH_GPIOE : Enable GPIOE reset
941 * @arg RCM_AHB1_PERIPH_GPIOF : Enable GPIOF reset
942 * @arg RCM_AHB1_PERIPH_GPIOG : Enable GPIOG reset
943 * @arg RCM_AHB1_PERIPH_GPIOI : Enable GPIOI reset
944 * @arg RCM_AHB1_PERIPH_CRC : Enable CRC reset
945 * @arg RCM_AHB1_PERIPH_BKPSRAM : Enable BKPSRAM interface reset
946 * @arg RCM_AHB1_PERIPH_CCMDATARAMEN: Enable CCM data RAM interface reset
947 * @arg RCM_AHB1_PERIPH_DMA1 : Enable DMA1 reset
948 * @arg RCM_AHB1_PERIPH_DMA2 : Enable DMA2 reset
949 * @arg RCM_AHB1_PERIPH_ETH_MAC : Enable Ethernet MAC reset
950 * @arg RCM_AHB1_PERIPH_ETH_MAC_Tx : Enable Ethernet Transmission reset
951 * @arg RCM_AHB1_PERIPH_ETH_MAC_Rx : Enable Ethernet Reception reset
952 * @arg RCM_AHB1_PERIPH_ETH_MAC_PTP : Enable Ethernet PTP reset
953 * @arg RCM_AHB1_PERIPH_OTG_HS : Enable USB OTG HS reset
954 * @arg RCM_AHB1_PERIPH_OTG_HS_ULPI : Enable USB OTG HS ULPI clock
955 *
956 * @retval None
957 */
RCM_EnableAHB1PeriphReset(uint32_t AHB1Periph)958 void RCM_EnableAHB1PeriphReset(uint32_t AHB1Periph)
959 {
960 RCM->AHB1RST |= AHB1Periph;
961 }
962
963 /*!
964 * @brief Disable AHB1 peripheral reset
965 *
966 * @param AHB1Periph : Disable the specifies reset of AHB1 peripheral
967 * This parameter can be any combination of the following values:
968 * @arg RCM_AHB1_PERIPH_GPIOA : Disable GPIOA reset
969 * @arg RCM_AHB1_PERIPH_GPIOB : Disable GPIOB reset
970 * @arg RCM_AHB1_PERIPH_GPIOC : Disable GPIOC reset
971 * @arg RCM_AHB1_PERIPH_GPIOD : Disable GPIOD reset
972 * @arg RCM_AHB1_PERIPH_GPIOE : Disable GPIOE reset
973 * @arg RCM_AHB1_PERIPH_GPIOF : Disable GPIOF reset
974 * @arg RCM_AHB1_PERIPH_GPIOG : Disable GPIOG reset
975 * @arg RCM_AHB1_PERIPH_GPIOI : Disable GPIOI reset
976 * @arg RCM_AHB1_PERIPH_CRC : Disable CRC reset
977 * @arg RCM_AHB1_PERIPH_BKPSRAM : Disable BKPSRAM interface reset
978 * @arg RCM_AHB1_PERIPH_CCMDATARAMEN: Disable CCM data RAM interface reset
979 * @arg RCM_AHB1_PERIPH_DMA1 : Disable DMA1 reset
980 * @arg RCM_AHB1_PERIPH_DMA2 : Disable DMA2 reset
981 * @arg RCM_AHB1_PERIPH_ETH_MAC : Disable Ethernet MAC reset
982 * @arg RCM_AHB1_PERIPH_ETH_MAC_Tx : Disable Ethernet Transmission reset
983 * @arg RCM_AHB1_PERIPH_ETH_MAC_Rx : Disable Ethernet Reception reset
984 * @arg RCM_AHB1_PERIPH_ETH_MAC_PTP : Disable Ethernet PTP reset
985 * @arg RCM_AHB1_PERIPH_OTG_HS : Disable USB OTG HS reset
986 * @arg RCM_AHB1_PERIPH_OTG_HS_ULPI : Disable USB OTG HS ULPI reset
987 *
988 * @retval None
989 */
RCM_DisableAHB1PeriphReset(uint32_t AHB1Periph)990 void RCM_DisableAHB1PeriphReset(uint32_t AHB1Periph)
991 {
992 RCM->AHB1RST &= (uint32_t)~AHB1Periph;
993 }
994
995 /*!
996 * @brief Enables AHB2 peripheral reset
997 *
998 * @param AHB2Periph : Enable the specifies reset of AHB2 peripheral
999 * This parameter can be any combination of the following values:
1000 * @arg RCM_AHB2_PERIPH_DCI : Enable DCI reset
1001 * @arg RCM_AHB2_PERIPH_FPU : Enable FPU reset
1002 * @arg RCM_AHB2_PERIPH_BN : Enable BN reset
1003 * @arg RCM_AHB2_PERIPH_SM : Enable SM reset
1004 * @arg RCM_AHB2_PERIPH_CRYP : Enable CRYP reset
1005 * @arg RCM_AHB2_PERIPH_HASH : Enable HASH reset
1006 * @arg RCM_AHB2_PERIPH_RNG : Enable RNG reset
1007 * @arg RCM_AHB2_PERIPH_OTG_FS : Enable OTG FS reset
1008 *
1009 * @retval None
1010 */
RCM_EnableAHB2PeriphReset(uint32_t AHB2Periph)1011 void RCM_EnableAHB2PeriphReset(uint32_t AHB2Periph)
1012 {
1013 RCM->AHB2RST |= AHB2Periph;
1014 }
1015
1016 /*!
1017 * @brief Disable AHB2 peripheral reset
1018 *
1019 * @param AHB2Periph : Disable the specifies reset of AHB2 peripheral
1020 * This parameter can be any combination of the following values:
1021 * @arg RCM_AHB2_PERIPH_DCI : Disable DCI reset
1022 * @arg RCM_AHB2_PERIPH_FPU : Disable FPU reset
1023 * @arg RCM_AHB2_PERIPH_BN : Disable BN reset
1024 * @arg RCM_AHB2_PERIPH_SM : Disable SM reset
1025 * @arg RCM_AHB2_PERIPH_CRYP : Disable CRYP reset
1026 * @arg RCM_AHB2_PERIPH_HASH : Disable HASH reset
1027 * @arg RCM_AHB2_PERIPH_RNG : Disable RNG reset
1028 * @arg RCM_AHB2_PERIPH_OTG_FS : Disable OTG FS reset
1029 *
1030 * @retval None
1031 */
RCM_DisableAHB2PeriphReset(uint32_t AHB2Periph)1032 void RCM_DisableAHB2PeriphReset(uint32_t AHB2Periph)
1033 {
1034 RCM->AHB2RST &= (uint32_t)~AHB2Periph;
1035 }
1036
1037 /*!
1038 * @brief Enable the Low Speed APB (APB1) peripheral reset
1039 *
1040 * @param APB1Periph : Enable specifies reset of the APB1 peripheral.
1041 * This parameter can be any combination of the following values:
1042 * @arg RCM_APB1_PERIPH_TMR2 : Enable TMR2 reset
1043 * @arg RCM_APB1_PERIPH_TMR3 : Enable TMR3 reset
1044 * @arg RCM_APB1_PERIPH_TMR4 : Enable TMR4 reset
1045 * @arg RCM_APB1_PERIPH_TMR5 : Enable TMR5 reset
1046 * @arg RCM_APB1_PERIPH_TMR6 : Enable TMR6 reset
1047 * @arg RCM_APB1_PERIPH_TMR7 : Enable TMR7 reset
1048 * @arg RCM_APB1_PERIPH_TMR12 : Enable TMR12 reset
1049 * @arg RCM_APB1_PERIPH_TMR13 : Enable TMR13 reset
1050 * @arg RCM_APB1_PERIPH_TMR14 : Enable TMR14 reset
1051 * @arg RCM_APB1_PERIPH_WWDT : Enable WWDT reset
1052 * @arg RCM_APB1_PERIPH_SPI2 : Enable SPI2 reset
1053 * @arg RCM_APB1_PERIPH_SPI3 : Enable SPI3 reset
1054 * @arg RCM_APB1_PERIPH_USART2 : Enable USART2 reset
1055 * @arg RCM_APB1_PERIPH_USART3 : Enable USART3 reset
1056 * @arg RCM_APB1_PERIPH_UART4 : Enable UART4 reset
1057 * @arg RCM_APB1_PERIPH_UART5 : Enable UART5 reset
1058 * @arg RCM_APB1_PERIPH_I2C1 : Enable I2C1 reset
1059 * @arg RCM_APB1_PERIPH_I2C2 : Enable I2C2 reset
1060 * @arg RCM_APB1_PERIPH_I2C3 : Enable I2C3 reset
1061 * @arg RCM_APB1_PERIPH_FMPI2C1: Enable FMPI2C1 reset
1062 * @arg RCM_APB1_PERIPH_CAN1 : Enable CAN1 reset
1063 * @arg RCM_APB1_PERIPH_CAN2 : Enable CAN2 reset
1064 * @arg RCM_APB1_PERIPH_PMU : Enable PMU reset
1065 * @arg RCM_APB1_PERIPH_DAC : Enable DAC reset
1066 * @arg RCM_APB1_PERIPH_UART7 : Enable UART7 reset
1067 * @arg RCM_APB1_PERIPH_UART8 : Enable UART8 reset
1068 *
1069 * @retval None
1070 */
RCM_EnableAPB1PeriphReset(uint32_t APB1Periph)1071 void RCM_EnableAPB1PeriphReset(uint32_t APB1Periph)
1072 {
1073 RCM->APB1RST |= APB1Periph;
1074 }
1075
1076 /*!
1077 * @brief Disable the Low Speed APB (APB1) peripheral reset
1078 *
1079 * @param APB1Periph : Disable specifies reset of the APB1 peripheral.
1080 * This parameter can be any combination of the following values:
1081 * @arg RCM_APB1_PERIPH_TMR2 : Disable TMR2 reset
1082 * @arg RCM_APB1_PERIPH_TMR3 : Disable TMR3 reset
1083 * @arg RCM_APB1_PERIPH_TMR4 : Disable TMR4 reset
1084 * @arg RCM_APB1_PERIPH_TMR5 : Disable TMR5 reset
1085 * @arg RCM_APB1_PERIPH_TMR6 : Disable TMR6 reset
1086 * @arg RCM_APB1_PERIPH_TMR7 : Disable TMR7 reset
1087 * @arg RCM_APB1_PERIPH_TMR12 : Disable TMR12 reset
1088 * @arg RCM_APB1_PERIPH_TMR13 : Disable TMR13 reset
1089 * @arg RCM_APB1_PERIPH_TMR14 : Disable TMR14 reset
1090 * @arg RCM_APB1_PERIPH_WWDT : Disable WWDT reset
1091 * @arg RCM_APB1_PERIPH_SPI2 : Disable SPI2 reset
1092 * @arg RCM_APB1_PERIPH_SPI3 : Disable SPI3 reset
1093 * @arg RCM_APB1_PERIPH_USART2 : Disable USART2 reset
1094 * @arg RCM_APB1_PERIPH_USART3 : Disable USART3 reset
1095 * @arg RCM_APB1_PERIPH_UART4 : Disable UART4 reset
1096 * @arg RCM_APB1_PERIPH_UART5 : Disable UART5 reset
1097 * @arg RCM_APB1_PERIPH_I2C1 : Disable I2C1 reset
1098 * @arg RCM_APB1_PERIPH_I2C2 : Disable I2C2 reset
1099 * @arg RCM_APB1_PERIPH_I2C3 : Disable I2C3 reset
1100 * @arg RCM_APB1_PERIPH_FMPI2C1: Disable FMPI2C1 reset
1101 * @arg RCM_APB1_PERIPH_CAN1 : Disable CAN1 reset
1102 * @arg RCM_APB1_PERIPH_CAN2 : Disable CAN2 reset
1103 * @arg RCM_APB1_PERIPH_PMU : Disable PMU reset
1104 * @arg RCM_APB1_PERIPH_DAC : Disable DAC reset
1105 * @arg RCM_APB1_PERIPH_UART7 : Disable UART7 reset
1106 * @arg RCM_APB1_PERIPH_UART8 : Disable UART8 reset
1107 *
1108 * @retval None
1109 */
RCM_DisableAPB1PeriphReset(uint32_t APB1Periph)1110 void RCM_DisableAPB1PeriphReset(uint32_t APB1Periph)
1111 {
1112 RCM->APB1RST &= (uint32_t)~APB1Periph;
1113 }
1114
1115 /*!
1116 * @brief Enable the High Speed APB (APB2) peripheral reset
1117 *
1118 * @param APB2Periph : Enable specifies reset of the APB2 peripheral.
1119 * This parameter can be any combination of the following values:
1120 * @arg RCM_APB2_PERIPH_TMR1 : TMR1 reset
1121 * @arg RCM_APB2_PERIPH_TMR8 : TMR8 reset
1122 * @arg RCM_APB2_PERIPH_USART1 : USART1 reset
1123 * @arg RCM_APB2_PERIPH_USART6 : USART6 reset
1124 * @arg RCM_APB2_PERIPH_ADC : All of ADC reset
1125 * @arg RCM_APB2_PERIPH_SDIO : SDIO reset
1126 * @arg RCM_APB2_PERIPH_SPI1 : SPI1 reset
1127 * @arg RCM_APB2_PERIPH_SPI4 : SPI4 reset
1128 * @arg RCM_APB2_PERIPH_SYSCFG : SYSCFG reset
1129 * @arg RCM_APB2_PERIPH_TMR9 : TMR9 reset
1130 * @arg RCM_APB2_PERIPH_TMR10 : TMR10 reset
1131 * @arg RCM_APB2_PERIPH_TMR11 : TMR11 reset
1132 * @arg RCM_APB2_PERIPH_SPI5 : SPI5 reset
1133 * @arg RCM_APB2_PERIPH_SPI6 : SPI6 reset
1134 *
1135 * @retval None
1136 */
RCM_EnableAPB2PeriphReset(uint32_t APB2Periph)1137 void RCM_EnableAPB2PeriphReset(uint32_t APB2Periph)
1138 {
1139 RCM->APB2RST |= APB2Periph;
1140 }
1141
1142 /*!
1143 * @brief Disable the High Speed APB (APB2) peripheral reset
1144 *
1145 * @param APB2Periph : Disable specifies reset of the APB2 peripheral.
1146 * This parameter can be any combination of the following values:
1147 * @arg RCM_APB2_PERIPH_TMR1 : TMR1 reset
1148 * @arg RCM_APB2_PERIPH_TMR8 : TMR8 reset
1149 * @arg RCM_APB2_PERIPH_USART1 : USART1 reset
1150 * @arg RCM_APB2_PERIPH_USART6 : USART6 reset
1151 * @arg RCM_APB2_PERIPH_ADC1 : ADC1 reset
1152 * @arg RCM_APB2_PERIPH_ADC2 : ADC2 reset
1153 * @arg RCM_APB2_PERIPH_ADC3 : ADC3 reset
1154 * @arg RCM_APB2_PERIPH_SDIO : SDIO reset
1155 * @arg RCM_APB2_PERIPH_SPI1 : SPI1 reset
1156 * @arg RCM_APB2_PERIPH_SPI4 : SPI4 reset
1157 * @arg RCM_APB2_PERIPH_SYSCFG : SYSCFG reset
1158 * @arg RCM_APB2_PERIPH_TMR9 : TMR9 reset
1159 * @arg RCM_APB2_PERIPH_TMR10 : TMR10 reset
1160 * @arg RCM_APB2_PERIPH_TMR11 : TMR11 reset
1161 * @arg RCM_APB2_PERIPH_SPI5 : SPI5 reset
1162 * @arg RCM_APB2_PERIPH_SPI6 : SPI6 reset
1163 *
1164 * @retval None
1165 */
RCM_DisableAPB2PeriphReset(uint32_t APB2Periph)1166 void RCM_DisableAPB2PeriphReset(uint32_t APB2Periph)
1167 {
1168 RCM->APB2RST &= (uint32_t)~APB2Periph;
1169 }
1170
1171 /*!
1172 * @brief Enables AHB1 peripheral clock during Low Power (Sleep) mode
1173 *
1174 * @param AHB1Periph : Enable the specifies clock of AHB peripheral
1175 * This parameter can be any combination of the following values:
1176 * @arg RCM_AHB1_PERIPH_GPIOA : Enable GPIOA clock
1177 * @arg RCM_AHB1_PERIPH_GPIOB : Enable GPIOB clock
1178 * @arg RCM_AHB1_PERIPH_GPIOC : Enable GPIOC clock
1179 * @arg RCM_AHB1_PERIPH_GPIOD : Enable GPIOD clock
1180 * @arg RCM_AHB1_PERIPH_GPIOE : Enable GPIOE clock
1181 * @arg RCM_AHB1_PERIPH_GPIOF : Enable GPIOF clock
1182 * @arg RCM_AHB1_PERIPH_GPIOG : Enable GPIOG clock
1183 * @arg RCM_AHB1_PERIPH_GPIOI : Enable GPIOI clock
1184 * @arg RCM_AHB1_PERIPH_CRC : Enable CRC clock
1185 * @arg RCM_AHB1_PERIPH_BKPSRAM : Enable BKPSRAM interface clock
1186 * @arg RCM_AHB1_PERIPH_CCMDATARAMEN: Enable CCM data RAM interface clock
1187 * @arg RCM_AHB1_PERIPH_DMA1 : Enable DMA1 clock
1188 * @arg RCM_AHB1_PERIPH_DMA2 : Enable DMA2 clock
1189 * @arg RCM_AHB1_PERIPH_ETH_MAC : Enable Ethernet MAC clock
1190 * @arg RCM_AHB1_PERIPH_ETH_MAC_Tx : Enable Ethernet Transmission clock
1191 * @arg RCM_AHB1_PERIPH_ETH_MAC_Rx : Enable Ethernet Reception clock
1192 * @arg RCM_AHB1_PERIPH_ETH_MAC_PTP : Enable Ethernet PTP clock
1193 * @arg RCM_AHB1_PERIPH_OTG_HS : Enable USB OTG HS clock
1194 * @arg RCM_AHB1_PERIPH_OTG_HS_ULPI : Enable USB OTG HS ULPI clock
1195 *
1196 * @retval None
1197 */
RCM_EnableAHB1PeriphClockLPMode(uint32_t AHB1Periph)1198 void RCM_EnableAHB1PeriphClockLPMode(uint32_t AHB1Periph)
1199 {
1200 RCM->LPAHB1CLKEN |= AHB1Periph;
1201 }
1202
1203 /*!
1204 * @brief Disable AHB1 peripheral clock during Low Power (Sleep) mode
1205 *
1206 * @param AHB1Periph : Disable the specifies clock of AHB1 peripheral
1207 * This parameter can be any combination of the following values:
1208 * @arg RCM_AHB1_PERIPH_GPIOA : Disable GPIOA clock
1209 * @arg RCM_AHB1_PERIPH_GPIOB : Disable GPIOB clock
1210 * @arg RCM_AHB1_PERIPH_GPIOC : Disable GPIOC clock
1211 * @arg RCM_AHB1_PERIPH_GPIOD : Disable GPIOD clock
1212 * @arg RCM_AHB1_PERIPH_GPIOE : Disable GPIOE clock
1213 * @arg RCM_AHB1_PERIPH_GPIOF : Disable GPIOF clock
1214 * @arg RCM_AHB1_PERIPH_GPIOG : Disable GPIOG clock
1215 * @arg RCM_AHB1_PERIPH_GPIOI : Disable GPIOI clock
1216 * @arg RCM_AHB1_PERIPH_CRC : Disable CRC clock
1217 * @arg RCM_AHB1_PERIPH_BKPSRAM : Disable BKPSRAM interface clock
1218 * @arg RCM_AHB1_PERIPH_CCMDATARAMEN: Disable CCM data RAM interface clock
1219 * @arg RCM_AHB1_PERIPH_DMA1 : Disable DMA1 clock
1220 * @arg RCM_AHB1_PERIPH_DMA2 : Disable DMA2 clock
1221 * @arg RCM_AHB1_PERIPH_ETH_MAC : Disable Ethernet MAC clock
1222 * @arg RCM_AHB1_PERIPH_ETH_MAC_Tx : Disable Ethernet Transmission clock
1223 * @arg RCM_AHB1_PERIPH_ETH_MAC_Rx : Disable Ethernet Reception clock
1224 * @arg RCM_AHB1_PERIPH_ETH_MAC_PTP : Disable Ethernet PTP clock
1225 * @arg RCM_AHB1_PERIPH_OTG_HS : Disable USB OTG HS clock
1226 * @arg RCM_AHB1_PERIPH_OTG_HS_ULPI : Disable USB OTG HS ULPI clock
1227 *
1228 * @retval None
1229 */
RCM_DisableAHB1PeriphClockLPMode(uint32_t AHB1Periph)1230 void RCM_DisableAHB1PeriphClockLPMode(uint32_t AHB1Periph)
1231 {
1232 RCM->LPAHB1CLKEN &= (uint32_t)~AHB1Periph;
1233 }
1234
1235 /*!
1236 * @brief Enables AHB2 peripheral clock during Low Power (Sleep) mode
1237 *
1238 * @param AHB2Periph : Enable the specifies clock of AHB2 peripheral
1239 * This parameter can be any combination of the following values:
1240 * @arg RCM_AHB2_PERIPH_DCI : Enable DCI clock
1241 * @arg RCM_AHB2_PERIPH_FPU : Enable FPU clock
1242 * @arg RCM_AHB2_PERIPH_BN : Enable BN clock
1243 * @arg RCM_AHB2_PERIPH_SM : Enable SM clock
1244 * @arg RCM_AHB2_PERIPH_CRYP : Enable CRYP clock
1245 * @arg RCM_AHB2_PERIPH_HASH : Enable HASH clock
1246 * @arg RCM_AHB2_PERIPH_RNG : Enable RNG clock
1247 * @arg RCM_AHB2_PERIPH_OTG_FS : Enable OTG FS clock
1248 *
1249 * @retval None
1250 */
RCM_EnableAHB2PeriphClockLPMode(uint32_t AHB2Periph)1251 void RCM_EnableAHB2PeriphClockLPMode(uint32_t AHB2Periph)
1252 {
1253 RCM->LPAHB2CLKEN |= AHB2Periph;
1254 }
1255
1256 /*!
1257 * @brief Disable AHB2 peripheral clock during Low Power (Sleep) mode
1258 *
1259 * @param AHB2Periph : Disable the specifies clock of AHB2 peripheral
1260 * This parameter can be any combination of the following values:
1261 * @arg RCM_AHB2_PERIPH_DCI : Disable DCI clock
1262 * @arg RCM_AHB2_PERIPH_FPU : Disable FPU clock
1263 * @arg RCM_AHB2_PERIPH_BN : Disable BN clock
1264 * @arg RCM_AHB2_PERIPH_SM : Disable SM clock
1265 * @arg RCM_AHB2_PERIPH_CRYP : Disable CRYP clock
1266 * @arg RCM_AHB2_PERIPH_HASH : Disable HASH clock
1267 * @arg RCM_AHB2_PERIPH_RNG : Disable RNG clock
1268 * @arg RCM_AHB2_PERIPH_OTG_FS : Disable OTG FS clock
1269 *
1270 * @retval None
1271 */
RCM_DisableAHB2PeriphClockLPMode(uint32_t AHB2Periph)1272 void RCM_DisableAHB2PeriphClockLPMode(uint32_t AHB2Periph)
1273 {
1274 RCM->LPAHB2CLKEN &= (uint32_t)~AHB2Periph;
1275 }
1276
1277 /*!
1278 * @brief Enable the Low Speed APB (APB1) peripheral clock during Low Power (Sleep) mode
1279 *
1280 * @param APB1Periph : Enable specifies clock of the APB1 peripheral.
1281 * This parameter can be any combination of the following values:
1282 * @arg RCM_APB1_PERIPH_TMR2 : Enable TMR2 clock
1283 * @arg RCM_APB1_PERIPH_TMR3 : Enable TMR3 clock
1284 * @arg RCM_APB1_PERIPH_TMR4 : Enable TMR4 clock
1285 * @arg RCM_APB1_PERIPH_TMR5 : Enable TMR5 clock
1286 * @arg RCM_APB1_PERIPH_TMR6 : Enable TMR6 clock
1287 * @arg RCM_APB1_PERIPH_TMR7 : Enable TMR7 clock
1288 * @arg RCM_APB1_PERIPH_TMR12 : Enable TMR12 clock
1289 * @arg RCM_APB1_PERIPH_TMR13 : Enable TMR13 clock
1290 * @arg RCM_APB1_PERIPH_TMR14 : Enable TMR14 clock
1291 * @arg RCM_APB1_PERIPH_WWDT : Enable WWDT clock
1292 * @arg RCM_APB1_PERIPH_SPI2 : Enable SPI2 clock
1293 * @arg RCM_APB1_PERIPH_SPI3 : Enable SPI3 clock
1294 * @arg RCM_APB1_PERIPH_USART2 : Enable USART2 clock
1295 * @arg RCM_APB1_PERIPH_USART3 : Enable USART3 clock
1296 * @arg RCM_APB1_PERIPH_UART4 : Enable UART4 clock
1297 * @arg RCM_APB1_PERIPH_UART5 : Enable UART5 clock
1298 * @arg RCM_APB1_PERIPH_I2C1 : Enable I2C1 clock
1299 * @arg RCM_APB1_PERIPH_I2C2 : Enable I2C2 clock
1300 * @arg RCM_APB1_PERIPH_I2C3 : Enable I2C3 clock
1301 * @arg RCM_APB1_PERIPH_FMPI2C1: Enable FMPI2C1 clock
1302 * @arg RCM_APB1_PERIPH_CAN1 : Enable CAN1 clock
1303 * @arg RCM_APB1_PERIPH_CAN2 : Enable CAN2 clock
1304 * @arg RCM_APB1_PERIPH_PMU : Enable PMU clock
1305 * @arg RCM_APB1_PERIPH_DAC : Enable DAC clock
1306 * @arg RCM_APB1_PERIPH_UART7 : Enable UART7 clock
1307 * @arg RCM_APB1_PERIPH_UART8 : Enable UART8 clock
1308 *
1309 * @retval None
1310 */
RCM_EnableAPB1PeriphClockLPMode(uint32_t APB1Periph)1311 void RCM_EnableAPB1PeriphClockLPMode(uint32_t APB1Periph)
1312 {
1313 RCM->LPAPB1CLKEN |= APB1Periph;
1314 }
1315
1316 /*!
1317 * @brief Disable the Low Speed APB (APB1) peripheral clock during Low Power (Sleep) mode
1318 *
1319 * @param APB1Periph : Disable specifies clock of the APB1 peripheral.
1320 * This parameter can be any combination of the following values:
1321 * @arg RCM_APB1_PERIPH_TMR2 : Disable TMR2 clock
1322 * @arg RCM_APB1_PERIPH_TMR3 : Disable TMR3 clock
1323 * @arg RCM_APB1_PERIPH_TMR4 : Disable TMR4 clock
1324 * @arg RCM_APB1_PERIPH_TMR5 : Disable TMR5 clock
1325 * @arg RCM_APB1_PERIPH_TMR6 : Disable TMR6 clock
1326 * @arg RCM_APB1_PERIPH_TMR7 : Disable TMR7 clock
1327 * @arg RCM_APB1_PERIPH_TMR12 : Disable TMR12 clock
1328 * @arg RCM_APB1_PERIPH_TMR13 : Disable TMR13 clock
1329 * @arg RCM_APB1_PERIPH_TMR14 : Disable TMR14 clock
1330 * @arg RCM_APB1_PERIPH_WWDT : Disable WWDT clock
1331 * @arg RCM_APB1_PERIPH_SPI2 : Disable SPI2 clock
1332 * @arg RCM_APB1_PERIPH_SPI3 : Disable SPI3 clock
1333 * @arg RCM_APB1_PERIPH_USART2 : Disable USART2 clock
1334 * @arg RCM_APB1_PERIPH_USART3 : Disable USART3 clock
1335 * @arg RCM_APB1_PERIPH_UART4 : Disable UART4 clock
1336 * @arg RCM_APB1_PERIPH_UART5 : Disable UART5 clock
1337 * @arg RCM_APB1_PERIPH_I2C1 : Disable I2C1 clock
1338 * @arg RCM_APB1_PERIPH_I2C2 : Disable I2C2 clock
1339 * @arg RCM_APB1_PERIPH_I2C3 : Disable I2C3 clock
1340 * @arg RCM_APB1_PERIPH_FMPI2C1: Disable FMPI2C1 clock
1341 * @arg RCM_APB1_PERIPH_CAN1 : Disable CAN1 clock
1342 * @arg RCM_APB1_PERIPH_CAN2 : Disable CAN2 clock
1343 * @arg RCM_APB1_PERIPH_PMU : Disable PMU clock
1344 * @arg RCM_APB1_PERIPH_DAC : Disable DAC clock
1345 * @arg RCM_APB1_PERIPH_UART7 : Disable UART7 clock
1346 * @arg RCM_APB1_PERIPH_UART8 : Disable UART8 clock
1347 *
1348 * @retval None
1349 */
RCM_DisableAPB1PeriphClockLPMode(uint32_t APB1Periph)1350 void RCM_DisableAPB1PeriphClockLPMode(uint32_t APB1Periph)
1351 {
1352 RCM->LPAPB1CLKEN &= (uint32_t)~APB1Periph;
1353 }
1354
1355 /*!
1356 * @brief Enable the High Speed APB (APB2) peripheral clock during Low Power (Sleep) mode
1357 *
1358 * @param APB2Periph : Enable specifies clock of the APB2 peripheral.
1359 * This parameter can be any combination of the following values:
1360 * @arg RCM_APB2_PERIPH_TMR1 : TMR1 clock
1361 * @arg RCM_APB2_PERIPH_TMR8 : TMR8 clock
1362 * @arg RCM_APB2_PERIPH_USART1 : USART1 clock
1363 * @arg RCM_APB2_PERIPH_USART6 : USART6 clock
1364 * @arg RCM_APB2_PERIPH_ADC1 : ADC1 clock
1365 * @arg RCM_APB2_PERIPH_ADC2 : ADC2 clock
1366 * @arg RCM_APB2_PERIPH_ADC3 : ADC3 clock
1367 * @arg RCM_APB2_PERIPH_SDIO : SDIO clock
1368 * @arg RCM_APB2_PERIPH_SPI1 : SPI1 clock
1369 * @arg RCM_APB2_PERIPH_SPI4 : SPI4 clock
1370 * @arg RCM_APB2_PERIPH_SYSCFG : SYSCFG clock
1371 * @arg RCM_APB2_PERIPH_TMR9 : TMR9 clock
1372 * @arg RCM_APB2_PERIPH_TMR10 : TMR10 clock
1373 * @arg RCM_APB2_PERIPH_TMR11 : TMR11 clock
1374 * @arg RCM_APB2_PERIPH_SPI5 : SPI5 clock
1375 * @arg RCM_APB2_PERIPH_SPI6 : SPI6 clock
1376 *
1377 * @retval None
1378 */
RCM_EnableAPB2PeriphClockLPMode(uint32_t APB2Periph)1379 void RCM_EnableAPB2PeriphClockLPMode(uint32_t APB2Periph)
1380 {
1381 RCM->LPAPB2CLKEN |= APB2Periph;
1382 }
1383
1384 /*!
1385 * @brief Disable the High Speed APB (APB2) peripheral clock during Low Power (Sleep) mode
1386 *
1387 * @param APB2Periph : Disable specifies clock of the APB2 peripheral.
1388 * This parameter can be any combination of the following values:
1389 * @arg RCM_APB2_PERIPH_TMR1 : TMR1 clock
1390 * @arg RCM_APB2_PERIPH_TMR8 : TMR8 clock
1391 * @arg RCM_APB2_PERIPH_USART1 : USART1 clock
1392 * @arg RCM_APB2_PERIPH_USART6 : USART6 clock
1393 * @arg RCM_APB2_PERIPH_ADC1 : ADC1 clock
1394 * @arg RCM_APB2_PERIPH_ADC2 : ADC2 clock
1395 * @arg RCM_APB2_PERIPH_ADC3 : ADC3 clock
1396 * @arg RCM_APB2_PERIPH_SDIO : SDIO clock
1397 * @arg RCM_APB2_PERIPH_SPI1 : SPI1 clock
1398 * @arg RCM_APB2_PERIPH_SPI4 : SPI4 clock
1399 * @arg RCM_APB2_PERIPH_SYSCFG : SYSCFG clock
1400 * @arg RCM_APB2_PERIPH_TMR9 : TMR9 clock
1401 * @arg RCM_APB2_PERIPH_TMR10 : TMR10 clock
1402 * @arg RCM_APB2_PERIPH_TMR11 : TMR11 clock
1403 * @arg RCM_APB2_PERIPH_SPI5 : SPI5 clock
1404 * @arg RCM_APB2_PERIPH_SPI6 : SPI6 clock
1405 *
1406 * @retval None
1407 */
RCM_DisableAPB2PeriphClockLPMode(uint32_t APB2Periph)1408 void RCM_DisableAPB2PeriphClockLPMode(uint32_t APB2Periph)
1409 {
1410 RCM->LPAPB2CLKEN &= (uint32_t)~APB2Periph;
1411 }
1412
1413 /*!
1414 * @brief Enable RCM interrupts
1415 *
1416 * @param interrupt : Enable specifies RCM interrupt sources.
1417 * This parameter can be any combination of the following values:
1418 * @arg RCM_INT_LSIRDY : LSI ready interrupt
1419 * @arg RCM_INT_LSERDY : LSE ready interrupt
1420 * @arg RCM_INT_HSIRDY : HSI ready interrupt
1421 * @arg RCM_INT_HSERDY : HSE ready interrupt
1422 * @arg RCM_INT_PLL1RDY : PLL1 ready interrupt
1423 * @arg RCM_INT_PLL2RDY : PLL2 ready interrupt
1424 *
1425 * @retval None
1426 */
RCM_EnableInterrupt(uint32_t interrupt)1427 void RCM_EnableInterrupt(uint32_t interrupt)
1428 {
1429 uint32_t temp;
1430
1431 temp = interrupt << 8;
1432
1433 RCM->INT |= temp;
1434 }
1435
1436 /*!
1437 * @brief Disable RCM interrupts
1438 *
1439 * @param interrupt : Disable specifies RCM interrupt sources.
1440 * This parameter can be any combination of the following values:
1441 * @arg RCM_INT_LSIRDY : LSI ready interrupt
1442 * @arg RCM_INT_LSERDY : LSE ready interrupt
1443 * @arg RCM_INT_HSIRDY : HSI ready interrupt
1444 * @arg RCM_INT_HSERDY : HSE ready interrupt
1445 * @arg RCM_INT_PLL1RDY : PLL1 ready interrupt
1446 * @arg RCM_INT_PLL2RDY : PLL2 ready interrupt
1447 *
1448 * @retval None
1449 */
RCM_DisableInterrupt(uint32_t interrupt)1450 void RCM_DisableInterrupt(uint32_t interrupt)
1451 {
1452 uint32_t temp;
1453
1454 temp = interrupt << 8;
1455
1456 RCM->INT &= (uint32_t)~temp;
1457 }
1458
1459 /*!
1460 * @brief Read the specified RCM flag status
1461 *
1462 * @param flag : Returns specifies the flag status.
1463 * This parameter can be one of the following values:
1464 * @arg RCM_FLAG_HSIRDY : HSI ready flag
1465 * @arg RCM_FLAG_HSERDY : HSE ready flag
1466 * @arg RCM_FLAG_PLL1RDY : PLL1 ready flag
1467 * @arg RCM_FLAG_PLL2RDY : PLL2 ready flag
1468 * @arg RCM_FLAG_LSERDY : LSE ready flag
1469 * @arg RCM_FLAG_LSIRDY : LSI ready flag
1470 * @arg RCM_FLAG_BORRST : POR/PDR or BOR reset
1471 * @arg RCM_FLAG_PINRST : NRST PIN Reset Occur Flag
1472 * @arg RCM_FLAG_PORRST : POR/PDR Reset Occur Flag
1473 * @arg RCM_FLAG_SWRST : Software Reset Occur Flag
1474 * @arg RCM_FLAG_IWDTRST : Independent Watchdog Reset Occur Flag
1475 * @arg RCM_FLAG_WWDTRST : Window Watchdog Reset Occur Flag
1476 * @arg RCM_FLAG_LPRRST : Low Power Reset Occur Flag
1477 *
1478 * @retval The new state of flag (SET or RESET)
1479 */
RCM_ReadStatusFlag(RCM_FLAG_T flag)1480 uint8_t RCM_ReadStatusFlag(RCM_FLAG_T flag)
1481 {
1482 uint32_t reg, bit;
1483
1484 bit = (uint32_t)(1 << (flag & 0xff));
1485
1486 reg = (flag >> 8) & 0xff;
1487
1488 switch (reg)
1489 {
1490 case 0:
1491 reg = RCM->CTRL;
1492 break;
1493
1494 case 1:
1495 reg = RCM->BDCTRL;
1496 break;
1497
1498 case 2:
1499 reg = RCM->CSTS;
1500 break;
1501
1502 default:
1503 break;
1504 }
1505
1506 if (reg & bit)
1507 {
1508 return SET;
1509 }
1510
1511 return RESET;
1512 }
1513
1514 /*!
1515 * @brief Clears all the RCM reset flags
1516 *
1517 * @param None
1518 *
1519 * @retval None
1520 *
1521 * @note The reset flags are:
1522 * RCM_FLAG_BORRST, RCM_FLAG_PINRST, RCM_FLAG_PWRST, RCM_FLAG_SWRST
1523 * RCM_FLAG_IWDTRST, RCM_FLAG_WWDTRST, RCM_FLAG_LPRRST
1524 */
RCM_ClearStatusFlag(void)1525 void RCM_ClearStatusFlag(void)
1526 {
1527 RCM->CSTS_B.RSTFLGCLR = BIT_SET;
1528 }
1529
1530 /*!
1531 * @brief Reads the specified RCM interrupt Flag
1532 *
1533 * @param flag : Reads specifies RCM interrupt flag.
1534 * This parameter can be one of the following values:
1535 * @arg RCM_INT_LSIRDY : LSI ready interrupt flag
1536 * @arg RCM_INT_LSERDY : LSE ready interrupt flag
1537 * @arg RCM_INT_HSIRDY : HSI ready interrupt flag
1538 * @arg RCM_INT_HSERDY : HSE ready interrupt flag
1539 * @arg RCM_INT_PLL1RDY: PLL1 ready interrupt flag
1540 * @arg RCM_INT_PLL2RDY: PLL2 ready interrupt flag
1541 * @arg RCM_INT_CSS : Clock Security System interrupt flag
1542 *
1543 * @retval The new state of intFlag (SET or RESET)
1544 */
RCM_ReadIntFlag(RCM_INT_T flag)1545 uint8_t RCM_ReadIntFlag(RCM_INT_T flag)
1546 {
1547 return (RCM->INT &flag) ? SET : RESET;
1548 }
1549
1550 /*!
1551 * @brief Clears the interrupt flag
1552 *
1553 * @param flag : Clears specifies interrupt flag.
1554 * @arg RCM_INT_LSIRDY : Clear LSI ready interrupt flag
1555 * @arg RCM_INT_LSERDY : Clear LSE ready interrupt flag
1556 * @arg RCM_INT_HSIRDY : Clear HSI ready interrupt flag
1557 * @arg RCM_INT_HSERDY : Clear HSE ready interrupt flag
1558 * @arg RCM_INT_PLL1RDY: Clear PLL1 ready interrupt flag
1559 * @arg RCM_INT_PLL2RDY: Clear PLL2 ready interrupt flag
1560 * @arg RCM_INT_CSS : Clear Clock Security System interrupt flag
1561 *
1562 * @retval None
1563 */
RCM_ClearIntFlag(uint32_t flag)1564 void RCM_ClearIntFlag(uint32_t flag)
1565 {
1566 uint32_t temp;
1567
1568 temp = flag << 16;
1569 RCM->INT |= temp;
1570 }
1571
1572 /**@} end of group RCM_Functions */
1573 /**@} end of group RCM_Driver */
1574 /**@} end of group APM32F4xx_StdPeriphDriver */
1575