1 /*!
2 * @file apm32f4xx_smc.c
3 *
4 * @brief This file provides all the SMC firmware functions
5 *
6 * @version V1.0.2
7 *
8 * @date 2022-06-23
9 *
10 * @attention
11 *
12 * Copyright (C) 2021-2022 Geehy Semiconductor
13 *
14 * You may not use this file except in compliance with the
15 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
16 *
17 * The program is only for reference, which is distributed in the hope
18 * that it will be usefull and instructional for customers to develop
19 * their software. Unless required by applicable law or agreed to in
20 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
21 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
23 * and limitations under the License.
24 */
25
26 #include "apm32f4xx_smc.h"
27 #include "apm32f4xx_rcm.h"
28
29 /** @addtogroup APM32F4xx_StdPeriphDriver
30 @{
31 */
32
33 /** @defgroup SMC_Driver
34 * @brief SMC driver modules
35 @{
36 */
37
38 /** @defgroup SMC_Functions
39 @{
40 */
41
42 /*!
43 * @brief Rest the SMC NOR/SRAM Banks registers
44 *
45 * @param bank: Selects the SMC Bank.
46 * The parameter can be one of following values:
47 * @arg SMC_BANK1_NORSRAM_1 : SMC Bank1 NOR/SRAM1
48 * @arg SMC_BANK1_NORSRAM_2 : SMC Bank1 NOR/SRAM2
49 * @arg SMC_BANK1_NORSRAM_3 : SMC Bank1 NOR/SRAM3
50 * @arg SMC_BANK1_NORSRAM_4 : SMC Bank1 NOR/SRAM4
51 *
52 * @retval None
53 */
SMC_ResetNORSRAM(SMC_BANK1_NORSRAM_T bank)54 void SMC_ResetNORSRAM(SMC_BANK1_NORSRAM_T bank)
55 {
56 if (bank == SMC_BANK1_NORSRAM_1)
57 {
58 SMC_Bank1->CSCTRL1 = 0x000030DB;
59 SMC_Bank1->CSTIM1 = 0x0FFFFFFF;
60 SMC_Bank1E->WRTTIM1 = 0x0FFFFFFF;
61 }
62 else if (bank == SMC_BANK1_NORSRAM_2)
63 {
64 SMC_Bank1->CSCTRL2 = 0x000030D2;
65 SMC_Bank1->CSTIM2 = 0x0FFFFFFF;
66 SMC_Bank1E->WRTTIM2 = 0x0FFFFFFF;
67 }
68 else if (bank == SMC_BANK1_NORSRAM_3)
69 {
70 SMC_Bank1->CSCTRL3 = 0x000030D2;
71 SMC_Bank1->CSTIM3 = 0x0FFFFFFF;
72 SMC_Bank1E->WRTTIM3 = 0x0FFFFFFF;
73 }
74 else if (bank == SMC_BANK1_NORSRAM_4)
75 {
76 SMC_Bank1->CSCTRL4 = 0x000030D2;
77 SMC_Bank1->CSTIM4 = 0x0FFFFFFF;
78 SMC_Bank1E->WRTTIM4 = 0x0FFFFFFF;
79 }
80 }
81
82 /*!
83 * @brief Rest the SMC NAND Banks registers
84 *
85 * @param bank: Selects the SMC Bank.
86 * The parameter can be one of following values:
87 * @arg SMC_BANK2_NAND : SMC Bank2 NAND
88 * @arg SMC_BANK3_NAND : SMC Bank3 NAND
89 *
90 * @retval None
91 */
SMC_ResetNAND(SMC_BANK_NAND_T bank)92 void SMC_ResetNAND(SMC_BANK_NAND_T bank)
93 {
94 if (bank == SMC_BANK2_NAND)
95 {
96 SMC_Bank2->CTRL2 = 0x00000018;
97 SMC_Bank2->STSINT2 = 0x00000040;
98 SMC_Bank2->CMSTIM2 = 0xFCFCFCFC;
99 SMC_Bank2->AMSTIM2 = 0xFCFCFCFC;
100 }
101 else if (bank == SMC_BANK3_NAND)
102 {
103 SMC_Bank3->CTRL3 = 0x00000018;
104 SMC_Bank3->STSINT3 = 0x00000040;
105 SMC_Bank3->CMSTIM3 = 0xFCFCFCFC;
106 SMC_Bank3->AMSTIM3 = 0xFCFCFCFC;
107 }
108 }
109
110 /*!
111 * @brief Reset the SMC PCCARD Banks registers
112 *
113 * @param None
114 *
115 * @retval None
116 */
SMC_ResetPCCard(void)117 void SMC_ResetPCCard(void)
118 {
119 SMC_Bank4->CTRL4 = 0x00000018;
120 SMC_Bank4->STSINT4 = 0x00000000;
121 SMC_Bank4->CMSTIM4 = 0xFCFCFCFC;
122 SMC_Bank4->AMSTIM4 = 0xFCFCFCFC;
123 SMC_Bank4->IOSTIM4 = 0xFCFCFCFC;
124 }
125
126 /*!
127 * @brief Config the SMC NOR/SRAM Banks according to the specified parameters in the smcNORSRAMConfig.
128 *
129 * @param smcNORSRAMConfig: Point to a SMC_NORSRAMConfig_T structure
130 *
131 * @retval None
132 */
SMC_ConfigNORSRAM(SMC_NORSRAMConfig_T * smcNORSRAMConfig)133 void SMC_ConfigNORSRAM(SMC_NORSRAMConfig_T *smcNORSRAMConfig)
134 {
135 if (smcNORSRAMConfig->bank == SMC_BANK1_NORSRAM_1)
136 {
137 SMC_Bank1->CSCTRL1_B.ADMUXEN = smcNORSRAMConfig->dataAddressMux;
138 SMC_Bank1->CSCTRL1_B.MTYPECFG = smcNORSRAMConfig->memoryType;
139 SMC_Bank1->CSCTRL1_B.MDBWIDCFG = smcNORSRAMConfig->memoryDataWidth;
140 SMC_Bank1->CSCTRL1_B.BURSTEN = smcNORSRAMConfig->burstAcceesMode;
141 SMC_Bank1->CSCTRL1_B.WSASYNCEN = smcNORSRAMConfig->asynchronousWait;
142 SMC_Bank1->CSCTRL1_B.WSPOLCFG = smcNORSRAMConfig->waitSignalPolarity;
143 SMC_Bank1->CSCTRL1_B.WRAPBEN = smcNORSRAMConfig->wrapMode;
144 SMC_Bank1->CSCTRL1_B.WTIMCFG = smcNORSRAMConfig->waitSignalActive;
145 SMC_Bank1->CSCTRL1_B.WREN = smcNORSRAMConfig->writeOperation;
146 SMC_Bank1->CSCTRL1_B.WAITEN = smcNORSRAMConfig->waiteSignal;
147 SMC_Bank1->CSCTRL1_B.EXTMODEEN = smcNORSRAMConfig->extendedMode;
148 SMC_Bank1->CSCTRL1_B.WRBURSTEN = smcNORSRAMConfig->writeBurst;
149
150 if (smcNORSRAMConfig->memoryType == SMC_MEMORY_TYPE_NOR)
151 {
152 SMC_Bank1->CSCTRL1_B.NORFMACCEN = BIT_SET;
153 }
154
155 SMC_Bank1->CSTIM1_B.ADDRSETCFG = \
156 smcNORSRAMConfig->readWriteTimingStruct->addressSetupTime;
157 SMC_Bank1->CSTIM1_B.ADDRHLDCFG = \
158 smcNORSRAMConfig->readWriteTimingStruct->addressHodeTime;
159 SMC_Bank1->CSTIM1_B.DATASETCFG = \
160 smcNORSRAMConfig->readWriteTimingStruct->dataSetupTime;
161 SMC_Bank1->CSTIM1_B.BUSTURNCFG = \
162 smcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime;
163 SMC_Bank1->CSTIM1_B.CLKDIVCFG = \
164 smcNORSRAMConfig->readWriteTimingStruct->clockDivision;
165 SMC_Bank1->CSTIM1_B.DATALATCFG = \
166 smcNORSRAMConfig->readWriteTimingStruct->dataLatency;
167 SMC_Bank1->CSTIM1_B.ASYNCACCCFG = \
168 smcNORSRAMConfig->readWriteTimingStruct->accessMode;
169
170 if (smcNORSRAMConfig->extendedMode == SMC_EXTENDEN_MODE_ENABLE)
171 {
172 SMC_Bank1E->WRTTIM1_B.ADDRSETCFG = \
173 smcNORSRAMConfig->writeTimingStruct->addressSetupTime;
174 SMC_Bank1E->WRTTIM1_B.ADDRHLDCFG = \
175 smcNORSRAMConfig->writeTimingStruct->addressHodeTime;
176 SMC_Bank1E->WRTTIM1_B.DATASETCFG = \
177 smcNORSRAMConfig->writeTimingStruct->dataSetupTime;
178 SMC_Bank1E->WRTTIM1_B.BUSTURNCFG = \
179 smcNORSRAMConfig->writeTimingStruct->busTurnaroundTime;
180 SMC_Bank1E->WRTTIM1_B.ASYNCACCCFG = \
181 smcNORSRAMConfig->writeTimingStruct->accessMode;
182 }
183 else
184 {
185 SMC_Bank1E->WRTTIM1 = 0x0FFFFFFF;
186 }
187 }
188 else if (smcNORSRAMConfig->bank == SMC_BANK1_NORSRAM_2)
189 {
190 SMC_Bank1->CSCTRL2_B.ADMUXEN = smcNORSRAMConfig->dataAddressMux;
191 SMC_Bank1->CSCTRL2_B.MTYPECFG = smcNORSRAMConfig->memoryType;
192 SMC_Bank1->CSCTRL2_B.MDBWIDCFG = smcNORSRAMConfig->memoryDataWidth;
193 SMC_Bank1->CSCTRL2_B.BURSTEN = smcNORSRAMConfig->burstAcceesMode;
194 SMC_Bank1->CSCTRL2_B.WSASYNCEN = smcNORSRAMConfig->asynchronousWait;
195 SMC_Bank1->CSCTRL2_B.WSPOLCFG = smcNORSRAMConfig->waitSignalPolarity;
196 SMC_Bank1->CSCTRL2_B.WRAPBEN = smcNORSRAMConfig->wrapMode;
197 SMC_Bank1->CSCTRL2_B.WTIMCFG = smcNORSRAMConfig->waitSignalActive;
198 SMC_Bank1->CSCTRL2_B.WREN = smcNORSRAMConfig->writeOperation;
199 SMC_Bank1->CSCTRL2_B.WAITEN = smcNORSRAMConfig->waiteSignal;
200 SMC_Bank1->CSCTRL2_B.EXTMODEEN = smcNORSRAMConfig->extendedMode;
201 SMC_Bank1->CSCTRL2_B.WRBURSTEN = smcNORSRAMConfig->writeBurst;
202
203 if (smcNORSRAMConfig->memoryType == SMC_MEMORY_TYPE_NOR)
204 {
205 SMC_Bank1->CSCTRL2_B.NORFMACCEN = BIT_SET;
206 }
207
208 SMC_Bank1->CSTIM2_B.ADDRSETCFG = \
209 smcNORSRAMConfig->readWriteTimingStruct->addressSetupTime;
210 SMC_Bank1->CSTIM2_B.ADDRHLDCFG = \
211 smcNORSRAMConfig->readWriteTimingStruct->addressHodeTime;
212 SMC_Bank1->CSTIM2_B.DATASETCFG = \
213 smcNORSRAMConfig->readWriteTimingStruct->dataSetupTime;
214 SMC_Bank1->CSTIM2_B.BUSTURNCFG = \
215 smcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime;
216 SMC_Bank1->CSTIM2_B.CLKDIVCFG = \
217 smcNORSRAMConfig->readWriteTimingStruct->clockDivision;
218 SMC_Bank1->CSTIM2_B.DATALATCFG = \
219 smcNORSRAMConfig->readWriteTimingStruct->dataLatency;
220 SMC_Bank1->CSTIM2_B.ASYNCACCCFG = \
221 smcNORSRAMConfig->readWriteTimingStruct->accessMode;
222
223 if (smcNORSRAMConfig->extendedMode == SMC_EXTENDEN_MODE_ENABLE)
224 {
225 SMC_Bank1E->WRTTIM2_B.ADDRSETCFG = \
226 smcNORSRAMConfig->writeTimingStruct->addressSetupTime;
227 SMC_Bank1E->WRTTIM2_B.ADDRHLDCFG = \
228 smcNORSRAMConfig->writeTimingStruct->addressHodeTime;
229 SMC_Bank1E->WRTTIM2_B.DATASETCFG = \
230 smcNORSRAMConfig->writeTimingStruct->dataSetupTime;
231 SMC_Bank1E->WRTTIM2_B.BUSTURNCFG = \
232 smcNORSRAMConfig->writeTimingStruct->busTurnaroundTime;
233 SMC_Bank1E->WRTTIM2_B.ASYNCACCCFG = \
234 smcNORSRAMConfig->writeTimingStruct->accessMode;
235 }
236 else
237 {
238 SMC_Bank1E->WRTTIM2 = 0x0FFFFFFF;
239 }
240 }
241 else if (smcNORSRAMConfig->bank == SMC_BANK1_NORSRAM_3)
242 {
243 SMC_Bank1->CSCTRL3_B.ADMUXEN = smcNORSRAMConfig->dataAddressMux;
244 SMC_Bank1->CSCTRL3_B.MTYPECFG = smcNORSRAMConfig->memoryType;
245 SMC_Bank1->CSCTRL3_B.MDBWIDCFG = smcNORSRAMConfig->memoryDataWidth;
246 SMC_Bank1->CSCTRL3_B.BURSTEN = smcNORSRAMConfig->burstAcceesMode;
247 SMC_Bank1->CSCTRL3_B.WSASYNCEN = smcNORSRAMConfig->asynchronousWait;
248 SMC_Bank1->CSCTRL3_B.WSPOLCFG = smcNORSRAMConfig->waitSignalPolarity;
249 SMC_Bank1->CSCTRL3_B.WRAPBEN = smcNORSRAMConfig->wrapMode;
250 SMC_Bank1->CSCTRL3_B.WTIMCFG = smcNORSRAMConfig->waitSignalActive;
251 SMC_Bank1->CSCTRL3_B.WREN = smcNORSRAMConfig->writeOperation;
252 SMC_Bank1->CSCTRL3_B.WAITEN = smcNORSRAMConfig->waiteSignal;
253 SMC_Bank1->CSCTRL3_B.EXTMODEEN = smcNORSRAMConfig->extendedMode;
254 SMC_Bank1->CSCTRL3_B.WRBURSTEN = smcNORSRAMConfig->writeBurst;
255
256 if (smcNORSRAMConfig->memoryType == SMC_MEMORY_TYPE_NOR)
257 {
258 SMC_Bank1->CSCTRL3_B.NORFMACCEN = BIT_SET;
259 }
260
261 SMC_Bank1->CSTIM3_B.ADDRSETCFG = \
262 smcNORSRAMConfig->readWriteTimingStruct->addressSetupTime;
263 SMC_Bank1->CSTIM3_B.ADDRHLDCFG = \
264 smcNORSRAMConfig->readWriteTimingStruct->addressHodeTime;
265 SMC_Bank1->CSTIM3_B.DATASETCFG = \
266 smcNORSRAMConfig->readWriteTimingStruct->dataSetupTime;
267 SMC_Bank1->CSTIM3_B.BUSTURNCFG = \
268 smcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime;
269 SMC_Bank1->CSTIM3_B.CLKDIVCFG = \
270 smcNORSRAMConfig->readWriteTimingStruct->clockDivision;
271 SMC_Bank1->CSTIM3_B.DATALATCFG = \
272 smcNORSRAMConfig->readWriteTimingStruct->dataLatency;
273 SMC_Bank1->CSTIM3_B.ASYNCACCCFG = \
274 smcNORSRAMConfig->readWriteTimingStruct->accessMode;
275
276 if (smcNORSRAMConfig->extendedMode == SMC_EXTENDEN_MODE_ENABLE)
277 {
278 SMC_Bank1E->WRTTIM3_B.ADDRSETCFG = \
279 smcNORSRAMConfig->writeTimingStruct->addressSetupTime;
280 SMC_Bank1E->WRTTIM3_B.ADDRHLDCFG = \
281 smcNORSRAMConfig->writeTimingStruct->addressHodeTime;
282 SMC_Bank1E->WRTTIM3_B.DATASETCFG = \
283 smcNORSRAMConfig->writeTimingStruct->dataSetupTime;
284 SMC_Bank1E->WRTTIM3_B.BUSTURNCFG = \
285 smcNORSRAMConfig->writeTimingStruct->busTurnaroundTime;
286 SMC_Bank1E->WRTTIM3_B.ASYNCACCCFG = \
287 smcNORSRAMConfig->writeTimingStruct->accessMode;
288 }
289 else
290 {
291 SMC_Bank1E->WRTTIM3 = 0x0FFFFFFF;
292 }
293 }
294 else if (smcNORSRAMConfig->bank == SMC_BANK1_NORSRAM_4)
295 {
296 SMC_Bank1->CSCTRL4_B.ADMUXEN = smcNORSRAMConfig->dataAddressMux;
297 SMC_Bank1->CSCTRL4_B.MTYPECFG = smcNORSRAMConfig->memoryType;
298 SMC_Bank1->CSCTRL4_B.MDBWIDCFG = smcNORSRAMConfig->memoryDataWidth;
299 SMC_Bank1->CSCTRL4_B.BURSTEN = smcNORSRAMConfig->burstAcceesMode;
300 SMC_Bank1->CSCTRL4_B.WSASYNCEN = smcNORSRAMConfig->asynchronousWait;
301 SMC_Bank1->CSCTRL4_B.WSPOLCFG = smcNORSRAMConfig->waitSignalPolarity;
302 SMC_Bank1->CSCTRL4_B.WRAPBEN = smcNORSRAMConfig->wrapMode;
303 SMC_Bank1->CSCTRL4_B.WTIMCFG = smcNORSRAMConfig->waitSignalActive;
304 SMC_Bank1->CSCTRL4_B.WREN = smcNORSRAMConfig->writeOperation;
305 SMC_Bank1->CSCTRL4_B.WAITEN = smcNORSRAMConfig->waiteSignal;
306 SMC_Bank1->CSCTRL4_B.EXTMODEEN = smcNORSRAMConfig->extendedMode;
307 SMC_Bank1->CSCTRL4_B.WRBURSTEN = smcNORSRAMConfig->writeBurst;
308
309 if (smcNORSRAMConfig->memoryType == SMC_MEMORY_TYPE_NOR)
310 {
311 SMC_Bank1->CSCTRL4_B.NORFMACCEN = BIT_SET;
312 }
313
314 SMC_Bank1->CSTIM4_B.ADDRSETCFG = \
315 smcNORSRAMConfig->readWriteTimingStruct->addressSetupTime;
316 SMC_Bank1->CSTIM4_B.ADDRHLDCFG = \
317 smcNORSRAMConfig->readWriteTimingStruct->addressHodeTime;
318 SMC_Bank1->CSTIM4_B.DATASETCFG = \
319 smcNORSRAMConfig->readWriteTimingStruct->dataSetupTime;
320 SMC_Bank1->CSTIM4_B.BUSTURNCFG = \
321 smcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime;
322 SMC_Bank1->CSTIM4_B.CLKDIVCFG = \
323 smcNORSRAMConfig->readWriteTimingStruct->clockDivision;
324 SMC_Bank1->CSTIM4_B.DATALATCFG = \
325 smcNORSRAMConfig->readWriteTimingStruct->dataLatency;
326 SMC_Bank1->CSTIM4_B.ASYNCACCCFG = \
327 smcNORSRAMConfig->readWriteTimingStruct->accessMode;
328
329 if (smcNORSRAMConfig->extendedMode == SMC_EXTENDEN_MODE_ENABLE)
330 {
331 SMC_Bank1E->WRTTIM4_B.ADDRSETCFG = \
332 smcNORSRAMConfig->writeTimingStruct->addressSetupTime;
333 SMC_Bank1E->WRTTIM4_B.ADDRHLDCFG = \
334 smcNORSRAMConfig->writeTimingStruct->addressHodeTime;
335 SMC_Bank1E->WRTTIM4_B.DATASETCFG = \
336 smcNORSRAMConfig->writeTimingStruct->dataSetupTime;
337 SMC_Bank1E->WRTTIM4_B.BUSTURNCFG = \
338 smcNORSRAMConfig->writeTimingStruct->busTurnaroundTime;
339 SMC_Bank1E->WRTTIM4_B.ASYNCACCCFG = \
340 smcNORSRAMConfig->writeTimingStruct->accessMode;
341 }
342 else
343 {
344 SMC_Bank1E->WRTTIM4 = 0x0FFFFFFF;
345 }
346 }
347 }
348
349 /*!
350 * @brief Config the SMC NAND Banks according to the specified parameters in the smcNANDConfig.
351 *
352 * @param smcNANDConfig : Point to a SMC_NANDConfig_T structure.
353 *
354 * @retval None
355 */
SMC_ConfigNAND(SMC_NANDConfig_T * smcNANDConfig)356 void SMC_ConfigNAND(SMC_NANDConfig_T *smcNANDConfig)
357 {
358 if (smcNANDConfig->bank == SMC_BANK2_NAND)
359 {
360 SMC_Bank2->CTRL2_B.WAITFEN = smcNANDConfig->waitFeature;
361 SMC_Bank2->CTRL2_B.DBWIDCFG = smcNANDConfig->memoryDataWidth;
362 SMC_Bank2->CTRL2_B.ECCEN = smcNANDConfig->ECC;
363 SMC_Bank2->CTRL2_B.ECCPSCFG = smcNANDConfig->ECCPageSize;
364 SMC_Bank2->CTRL2_B.C2RDCFG = smcNANDConfig->TCLRSetupTime;
365 SMC_Bank2->CTRL2_B.A2RDCFG = smcNANDConfig->TARSetupTime;
366 SMC_Bank2->CTRL2_B.MTYPECFG = BIT_SET;
367
368 SMC_Bank2->CMSTIM2_B.SET2 = \
369 smcNANDConfig->commonSpaceTimingStruct->setupTime;
370 SMC_Bank2->CMSTIM2_B.WAIT2 = \
371 smcNANDConfig->commonSpaceTimingStruct->waitSetupTime;
372 SMC_Bank2->CMSTIM2_B.HLD2 = \
373 smcNANDConfig->commonSpaceTimingStruct->holdSetupTime;
374 SMC_Bank2->CMSTIM2_B.HIZ2 = \
375 smcNANDConfig->commonSpaceTimingStruct->HiZSetupTime;
376
377 SMC_Bank2->AMSTIM2_B.SET2 = \
378 smcNANDConfig->attributeSpaceTimingStruct->setupTime;
379 SMC_Bank2->AMSTIM2_B.WAIT2 = \
380 smcNANDConfig->attributeSpaceTimingStruct->waitSetupTime;
381 SMC_Bank2->AMSTIM2_B.HLD2 = \
382 smcNANDConfig->attributeSpaceTimingStruct->holdSetupTime;
383 SMC_Bank2->AMSTIM2_B.HIZ2 = \
384 smcNANDConfig->attributeSpaceTimingStruct->HiZSetupTime;
385 }
386 else if (smcNANDConfig->bank == SMC_BANK3_NAND)
387 {
388 SMC_Bank3->CTRL3_B.WAITFEN = smcNANDConfig->waitFeature;
389 SMC_Bank3->CTRL3_B.DBWIDCFG = smcNANDConfig->memoryDataWidth;
390 SMC_Bank3->CTRL3_B.ECCEN = smcNANDConfig->ECC;
391 SMC_Bank3->CTRL3_B.ECCPSCFG = smcNANDConfig->ECCPageSize;
392 SMC_Bank3->CTRL3_B.C2RDCFG = smcNANDConfig->TCLRSetupTime;
393 SMC_Bank3->CTRL3_B.A2RDCFG = smcNANDConfig->TARSetupTime;
394 SMC_Bank3->CTRL3_B.MTYPECFG = BIT_SET;
395
396 SMC_Bank3->CMSTIM3_B.SET3 = \
397 smcNANDConfig->commonSpaceTimingStruct->setupTime;
398 SMC_Bank3->CMSTIM3_B.WAIT3 = \
399 smcNANDConfig->commonSpaceTimingStruct->waitSetupTime;
400 SMC_Bank3->CMSTIM3_B.HLD3 = \
401 smcNANDConfig->commonSpaceTimingStruct->holdSetupTime;
402 SMC_Bank3->CMSTIM3_B.HIZ3 = \
403 smcNANDConfig->commonSpaceTimingStruct->HiZSetupTime;
404
405 SMC_Bank3->AMSTIM3_B.SET3 = \
406 smcNANDConfig->attributeSpaceTimingStruct->setupTime;
407 SMC_Bank3->AMSTIM3_B.WAIT3 = \
408 smcNANDConfig->attributeSpaceTimingStruct->waitSetupTime;
409 SMC_Bank3->AMSTIM3_B.HLD3 = \
410 smcNANDConfig->attributeSpaceTimingStruct->holdSetupTime;
411 SMC_Bank3->AMSTIM3_B.HIZ3 = \
412 smcNANDConfig->attributeSpaceTimingStruct->HiZSetupTime;
413 }
414 }
415
416 /*!
417 * @brief Config the SMC PCCARD according to the specified parameters in the smcPCCardConfig.
418 *
419 * @param smcPCCardConfig: Point to a SMC_PCCARDConfig_T structure.
420 *
421 * @retval None
422 */
SMC_ConfigPCCard(SMC_PCCARDConfig_T * smcPCCardConfig)423 void SMC_ConfigPCCard(SMC_PCCARDConfig_T *smcPCCardConfig)
424 {
425 SMC_Bank4->CTRL4_B.WAITFEN = smcPCCardConfig->waitFeature;
426 SMC_Bank4->CTRL4_B.C2RDCFG = smcPCCardConfig->TCLRSetupTime;
427 SMC_Bank4->CTRL4_B.A2RDCFG = smcPCCardConfig->TARSetupTime;
428 SMC_Bank4->CTRL4_B.DBWIDCFG = BIT_SET;
429
430 SMC_Bank4->CMSTIM4_B.SET4 = \
431 smcPCCardConfig->commonSpaceTimingStruct->setupTime;
432 SMC_Bank4->CMSTIM4_B.WAIT4 = \
433 smcPCCardConfig->commonSpaceTimingStruct->waitSetupTime;
434 SMC_Bank4->CMSTIM4_B.HLD4 = \
435 smcPCCardConfig->commonSpaceTimingStruct->holdSetupTime;
436 SMC_Bank4->CMSTIM4_B.HIZ4 = \
437 smcPCCardConfig->commonSpaceTimingStruct->HiZSetupTime;
438
439 SMC_Bank4->AMSTIM4_B.SET4 = \
440 smcPCCardConfig->attributeSpaceTimingStruct->setupTime;
441 SMC_Bank4->AMSTIM4_B.WAIT4 = \
442 smcPCCardConfig->attributeSpaceTimingStruct->waitSetupTime;
443 SMC_Bank4->AMSTIM4_B.HLD4 = \
444 smcPCCardConfig->attributeSpaceTimingStruct->holdSetupTime;
445 SMC_Bank4->AMSTIM4_B.HIZ4 = \
446 smcPCCardConfig->attributeSpaceTimingStruct->HiZSetupTime;
447
448 SMC_Bank4->IOSTIM4_B.SET = \
449 smcPCCardConfig->IOSpaceTimingStruct->setupTime;
450 SMC_Bank4->IOSTIM4_B.WAIT = \
451 smcPCCardConfig->IOSpaceTimingStruct->waitSetupTime;
452 SMC_Bank4->IOSTIM4_B.HLD = \
453 smcPCCardConfig->IOSpaceTimingStruct->holdSetupTime;
454 SMC_Bank4->IOSTIM4_B.HIZ = \
455 smcPCCardConfig->IOSpaceTimingStruct->HiZSetupTime;
456 }
457
458 /*!
459 * @brief Fills each smcNORSRAMConfig member with its default value.
460 *
461 * @param smcNORSRAMConfig : Point to a SMC_NORSRAMConfig_T structure.
462 *
463 * @retval None
464 */
SMC_ConfigNORSRAMStructInit(SMC_NORSRAMConfig_T * smcNORSRAMConfig)465 void SMC_ConfigNORSRAMStructInit(SMC_NORSRAMConfig_T *smcNORSRAMConfig)
466 {
467 smcNORSRAMConfig->bank = SMC_BANK1_NORSRAM_1;
468 smcNORSRAMConfig->dataAddressMux = SMC_DATA_ADDRESS_MUX_ENABLE;
469 smcNORSRAMConfig->memoryType = SMC_MEMORY_TYPE_SRAM;
470 smcNORSRAMConfig->memoryDataWidth = SMC_MEMORY_DATA_WIDTH_8BIT;
471 smcNORSRAMConfig->burstAcceesMode = SMC_BURST_ACCESS_MODE_DISABLE;
472 smcNORSRAMConfig->asynchronousWait = SMC_ASYNCHRONOUS_WAIT_DISABLE;
473 smcNORSRAMConfig->waitSignalPolarity = SMC_WAIT_SIGNAL_POLARITY_LOW;
474 smcNORSRAMConfig->wrapMode = SMC_WRAP_MODE_DISABLE;
475 smcNORSRAMConfig->waitSignalActive = SMC_WAIT_SIGNAL_ACTIVE_BEFORE_WAIT_STATE;
476 smcNORSRAMConfig->writeOperation = SMC_WRITE_OPERATION_ENABLE;
477 smcNORSRAMConfig->waiteSignal = SMC_WAITE_SIGNAL_ENABLE;
478 smcNORSRAMConfig->extendedMode = SMC_EXTENDEN_MODE_DISABLE;
479 smcNORSRAMConfig->writeBurst = SMC_WRITE_BURST_DISABLE;
480 smcNORSRAMConfig->readWriteTimingStruct->addressSetupTime = 0xF;
481 smcNORSRAMConfig->readWriteTimingStruct->addressHodeTime = 0xF;
482 smcNORSRAMConfig->readWriteTimingStruct->dataSetupTime = 0xFF;
483 smcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime = 0xF;
484 smcNORSRAMConfig->readWriteTimingStruct->clockDivision = 0xF;
485 smcNORSRAMConfig->readWriteTimingStruct->dataLatency = 0xF;
486 smcNORSRAMConfig->readWriteTimingStruct->accessMode = SMC_ACCESS_MODE_A;
487 smcNORSRAMConfig->writeTimingStruct->addressSetupTime = 0xF;
488 smcNORSRAMConfig->writeTimingStruct->addressHodeTime = 0xF;
489 smcNORSRAMConfig->writeTimingStruct->dataSetupTime = 0xFF;
490 smcNORSRAMConfig->writeTimingStruct->busTurnaroundTime = 0xF;
491 smcNORSRAMConfig->writeTimingStruct->clockDivision = 0xF;
492 smcNORSRAMConfig->writeTimingStruct->dataLatency = 0xF;
493 smcNORSRAMConfig->writeTimingStruct->accessMode = SMC_ACCESS_MODE_A;
494 }
495
496 /*!
497 * @brief Fills each smcNANDConfig member with its default value.
498 *
499 * @param smcNANDConfig : Point to a SMC_NANDConfig_T structure.
500 *
501 * @retval None
502 */
SMC_ConfigNANDStructInit(SMC_NANDConfig_T * smcNANDConfig)503 void SMC_ConfigNANDStructInit(SMC_NANDConfig_T *smcNANDConfig)
504 {
505 smcNANDConfig->bank = SMC_BANK2_NAND;
506 smcNANDConfig->waitFeature = SMC_WAIT_FEATURE_DISABLE;
507 smcNANDConfig->memoryDataWidth = SMC_MEMORY_DATA_WIDTH_8BIT;
508 smcNANDConfig->ECC = SMC_ECC_DISABLE;
509 smcNANDConfig->ECCPageSize = SMC_ECC_PAGE_SIZE_BYTE_256;
510 smcNANDConfig->TCLRSetupTime = 0x0;
511 smcNANDConfig->TARSetupTime = 0x0;
512 smcNANDConfig->commonSpaceTimingStruct->setupTime = 0xFC;
513 smcNANDConfig->commonSpaceTimingStruct->waitSetupTime = 0xFC;
514 smcNANDConfig->commonSpaceTimingStruct->holdSetupTime = 0xFC;
515 smcNANDConfig->commonSpaceTimingStruct->HiZSetupTime = 0xFC;
516 smcNANDConfig->attributeSpaceTimingStruct->setupTime = 0xFC;
517 smcNANDConfig->attributeSpaceTimingStruct->waitSetupTime = 0xFC;
518 smcNANDConfig->attributeSpaceTimingStruct->holdSetupTime = 0xFC;
519 smcNANDConfig->attributeSpaceTimingStruct->HiZSetupTime = 0xFC;
520 }
521
522 /*!
523 * @brief Fills each smcPCCardConfig member with its default value.
524 *
525 * @param smcPCCardConfig : Point to a SMC_PCCARDConfig_T structure.
526 *
527 * @retval None
528 */
SMC_ConfigPCCardStructInit(SMC_PCCARDConfig_T * smcPCCardConfig)529 void SMC_ConfigPCCardStructInit(SMC_PCCARDConfig_T *smcPCCardConfig)
530 {
531 smcPCCardConfig->waitFeature = SMC_WAIT_FEATURE_DISABLE;
532 smcPCCardConfig->TCLRSetupTime = 0x0;
533 smcPCCardConfig->TARSetupTime = 0x0;
534 smcPCCardConfig->commonSpaceTimingStruct->setupTime = 0xFC;
535 smcPCCardConfig->commonSpaceTimingStruct->waitSetupTime = 0xFC;
536 smcPCCardConfig->commonSpaceTimingStruct->holdSetupTime = 0xFC;
537 smcPCCardConfig->commonSpaceTimingStruct->HiZSetupTime = 0xFC;
538 smcPCCardConfig->attributeSpaceTimingStruct->setupTime = 0xFC;
539 smcPCCardConfig->attributeSpaceTimingStruct->waitSetupTime = 0xFC;
540 smcPCCardConfig->attributeSpaceTimingStruct->holdSetupTime = 0xFC;
541 smcPCCardConfig->attributeSpaceTimingStruct->HiZSetupTime = 0xFC;
542 smcPCCardConfig->IOSpaceTimingStruct->setupTime = 0xFC;
543 smcPCCardConfig->IOSpaceTimingStruct->waitSetupTime = 0xFC;
544 smcPCCardConfig->IOSpaceTimingStruct->holdSetupTime = 0xFC;
545 smcPCCardConfig->IOSpaceTimingStruct->HiZSetupTime = 0xFC;
546 }
547
548 /*!
549 * @brief Enables the specified NOR/SRAM Memory Bank.
550 *
551 * @param bank: Selects the SMC Bank.
552 * The parameter can be one of following values:
553 * @arg SMC_BANK1_NORSRAM_1 : SMC Bank1 NOR/SRAM1
554 * @arg SMC_BANK1_NORSRAM_2 : SMC Bank1 NOR/SRAM2
555 * @arg SMC_BANK1_NORSRAM_3 : SMC Bank1 NOR/SRAM3
556 * @arg SMC_BANK1_NORSRAM_4 : SMC Bank1 NOR/SRAM4
557 *
558 * @retval None
559 */
SMC_EnableNORSRAM(SMC_BANK1_NORSRAM_T bank)560 void SMC_EnableNORSRAM(SMC_BANK1_NORSRAM_T bank)
561 {
562 if (bank == SMC_BANK1_NORSRAM_1)
563 {
564 SMC_Bank1->CSCTRL1_B.MBKEN = BIT_SET;
565 }
566 else if (bank == SMC_BANK1_NORSRAM_2)
567 {
568 SMC_Bank1->CSCTRL2_B.MBKEN = BIT_SET;
569 }
570 else if (bank == SMC_BANK1_NORSRAM_3)
571 {
572 SMC_Bank1->CSCTRL3_B.MBKEN = BIT_SET;
573 }
574 else if (bank == SMC_BANK1_NORSRAM_4)
575 {
576 SMC_Bank1->CSCTRL4_B.MBKEN = BIT_SET;
577 }
578 }
579
580 /*!
581 * @brief Disbles the specified NOR/SRAM Memory Bank.
582 *
583 * @param bank: Selects the SMC Bank.
584 * The parameter can be one of following values:
585 * @arg SMC_BANK1_NORSRAM_1 : SMC Bank1 NOR/SRAM1
586 * @arg SMC_BANK1_NORSRAM_2 : SMC Bank1 NOR/SRAM2
587 * @arg SMC_BANK1_NORSRAM_3 : SMC Bank1 NOR/SRAM3
588 * @arg SMC_BANK1_NORSRAM_4 : SMC Bank1 NOR/SRAM4
589 *
590 * @retval None
591 */
SMC_DisableNORSRAM(SMC_BANK1_NORSRAM_T bank)592 void SMC_DisableNORSRAM(SMC_BANK1_NORSRAM_T bank)
593 {
594 if (bank == SMC_BANK1_NORSRAM_1)
595 {
596 SMC_Bank1->CSCTRL1_B.MBKEN = BIT_RESET;
597 }
598 else if (bank == SMC_BANK1_NORSRAM_2)
599 {
600 SMC_Bank1->CSCTRL2_B.MBKEN = BIT_RESET;
601 }
602 else if (bank == SMC_BANK1_NORSRAM_3)
603 {
604 SMC_Bank1->CSCTRL3_B.MBKEN = BIT_RESET;
605 }
606 else if (bank == SMC_BANK1_NORSRAM_4)
607 {
608 SMC_Bank1->CSCTRL4_B.MBKEN = BIT_RESET;
609 }
610 }
611
612 /*!
613 * @brief Enables the specified NAND Memory Bank.
614 *
615 * @param bank: Selects the SMC Bank.
616 * The parameter can be one of following values:
617 * @arg SMC_BANK2_NAND : SMC Bank2 NAND
618 * @arg SMC_BANK3_NAND : SMC Bank3 NAND
619 *
620 * @retval None
621 */
SMC_EnableNAND(SMC_BANK_NAND_T bank)622 void SMC_EnableNAND(SMC_BANK_NAND_T bank)
623 {
624 if (bank == SMC_BANK2_NAND)
625 {
626 SMC_Bank2->CTRL2_B.MBKEN = BIT_SET;
627 }
628 else if (bank == SMC_BANK3_NAND)
629 {
630 SMC_Bank3->CTRL3_B.MBKEN = BIT_SET;
631 }
632 }
633
634 /*!
635 * @brief Disbles the specified NAND Memory Bank.
636 *
637 * @param bank: Selects the SMC Bank.
638 * The parameter can be one of following values:
639 * @arg SMC_BANK2_NAND : SMC Bank2 NAND
640 * @arg SMC_BANK3_NAND : SMC Bank3 NAND
641 *
642 * @retval None
643 */
SMC_DisableNAND(SMC_BANK_NAND_T bank)644 void SMC_DisableNAND(SMC_BANK_NAND_T bank)
645 {
646 if (bank == SMC_BANK2_NAND)
647 {
648 SMC_Bank2->CTRL2_B.MBKEN = BIT_RESET;
649 }
650 else if (bank == SMC_BANK3_NAND)
651 {
652 SMC_Bank3->CTRL3_B.MBKEN = BIT_RESET;
653 }
654 }
655
656 /*!
657 * @brief Enables the specified PC Card Memory Bank.
658 *
659 * @param None
660 *
661 * @retval None
662 */
SMC_EnablePCCARD(void)663 void SMC_EnablePCCARD(void)
664 {
665 SMC_Bank4->CTRL4_B.MBKEN = BIT_SET;
666 }
667
668 /*!
669 * @brief Disables the specified PC Card Memory Bank.
670 *
671 * @param None
672 *
673 * @retval None
674 */
SMC_DisablePCCARD(void)675 void SMC_DisablePCCARD(void)
676 {
677 SMC_Bank4->CTRL4_B.MBKEN = BIT_RESET;
678 }
679
680 /*!
681 * @brief Enbles the SMC NAND ECC feature.
682 *
683 * @param bank: Selects the SMC Bank.
684 * The parameter can be one of following values:
685 * @arg SMC_BANK2_NAND : SMC Bank2 NAND
686 * @arg SMC_BANK3_NAND : SMC Bank3 NAND
687 *
688 * @retval None
689 */
SMC_EnableNANDECC(SMC_BANK_NAND_T bank)690 void SMC_EnableNANDECC(SMC_BANK_NAND_T bank)
691 {
692 if (bank == SMC_BANK2_NAND)
693 {
694 SMC_Bank2->CTRL2_B.ECCEN = BIT_SET;
695 }
696 else if (bank == SMC_BANK3_NAND)
697 {
698 SMC_Bank3->CTRL3_B.ECCEN = BIT_SET;
699 }
700 }
701
702 /*!
703 * @brief Disbles or disables the SMC NAND ECC feature.
704 *
705 * @param bank: Selects the SMC Bank.
706 * The parameter can be one of following values:
707 * @arg SMC_BANK2_NAND : SMC Bank2 NAND
708 * @arg SMC_BANK3_NAND : SMC Bank3 NAND
709 *
710 * @retval None
711 *
712 * @note
713 */
SMC_DisableNANDECC(SMC_BANK_NAND_T bank)714 void SMC_DisableNANDECC(SMC_BANK_NAND_T bank)
715 {
716 if (bank == SMC_BANK2_NAND)
717 {
718 SMC_Bank2->CTRL2_B.ECCEN = BIT_RESET;
719 }
720 else if (bank == SMC_BANK3_NAND)
721 {
722 SMC_Bank3->CTRL3_B.ECCEN = BIT_RESET;
723 }
724 }
725
726 /*!
727 * @brief Read the error correction code register value.
728 *
729 * @param bank: Selects the SMC Bank.
730 * The parameter can be one of following values:
731 * @arg SMC_BANK2_NAND : SMC Bank2 NAND
732 * @arg SMC_BANK3_NAND : SMC Bank3 NAND
733 *
734 * @retval The value of Error Correction Code (ECC).
735 */
SMC_ReadECC(SMC_BANK_NAND_T bank)736 uint32_t SMC_ReadECC(SMC_BANK_NAND_T bank)
737 {
738 uint32_t eccval = 0x00000000;
739
740 if (bank == SMC_BANK2_NAND)
741 {
742 eccval = SMC_Bank2->ECCRS2;
743 }
744 else if (bank == SMC_BANK3_NAND)
745 {
746 eccval = SMC_Bank3->ECCRS3;
747 }
748
749 return eccval;
750 }
751
752 /*!
753 * @brief Enables the specified SMC interrupts.
754 *
755 * @param bank: Selects the SMC Bank.
756 * The parameter can be one of following values:
757 * @arg SMC_BANK2_NAND : SMC Bank2 NAND
758 * @arg SMC_BANK3_NAND : SMC Bank3 NAND
759 * @arg SMC_BANK4_PCCARD : SMC Bank4 PCCARD
760 *
761 * @param interrupt: Select the SMC interrupt sources.
762 * This parameter can be any combination of the following values:
763 * @arg SMC_INT_EDGE_RISING : Rising edge detection interrupt.
764 * @arg SMC_INT_LEVEL_HIGH : High level detection interrupt.
765 * @arg SMC_INT_EDGE_FALLING : Falling edge detection interrupt.
766 *
767 * @retval None
768 */
SMC_EnableInterrupt(SMC_BANK_NAND_T bank,uint32_t interrupt)769 void SMC_EnableInterrupt(SMC_BANK_NAND_T bank, uint32_t interrupt)
770 {
771 if (bank == SMC_BANK2_NAND)
772 {
773 SMC_Bank2->STSINT2 |= interrupt;
774 }
775 else if (bank == SMC_BANK3_NAND)
776 {
777 SMC_Bank3->STSINT3 |= interrupt;
778 }
779 else
780 {
781 SMC_Bank4->STSINT4 |= interrupt;
782 }
783 }
784
785 /*!
786 * @brief Enables the specified SMC interrupts.
787 *
788 * @param bank: Selects the SMC Bank.
789 * The parameter can be one of following values:
790 * @arg SMC_BANK2_NAND : SMC Bank2 NAND
791 * @arg SMC_BANK3_NAND : SMC Bank3 NAND
792 * @arg SMC_BANK4_PCCARD : SMC Bank4 PCCARD
793 *
794 * @param interrupt: Select the SMC interrupt sources.
795 * This parameter can be any combination of the following values:
796 * @arg SMC_INT_EDGE_RISING : Rising edge detection interrupt.
797 * @arg SMC_INT_LEVEL_HIGH : High level edge detection interrupt.
798 * @arg SMC_INT_EDGE_FALLING : Falling edge detection interrupt.
799 *
800 * @retval None
801 */
SMC_DisableInterrupt(SMC_BANK_NAND_T bank,uint32_t interrupt)802 void SMC_DisableInterrupt(SMC_BANK_NAND_T bank, uint32_t interrupt)
803 {
804 if (bank == SMC_BANK2_NAND)
805 {
806 SMC_Bank2->STSINT2 &= ~interrupt;
807 }
808 else if (bank == SMC_BANK3_NAND)
809 {
810 SMC_Bank3->STSINT3 &= ~interrupt;
811 }
812 else
813 {
814 SMC_Bank4->STSINT4 &= ~interrupt;
815 }
816 }
817
818 /*!
819 * @brief Read the status of specified SMC flag.
820 *
821 * @param bank: Selects the SMC Bank.
822 * The parameter can be one of following values:
823 * @arg SMC_BANK2_NAND : SMC Bank2 NAND
824 * @arg SMC_BANK3_NAND : SMC Bank3 NAND
825 * @arg SMC_BANK4_PCCARD : SMC Bank4 PCCARD
826 *
827 * @param flag: Select the SMC interrupt sources.
828 * This parameter can be one of the following values:
829 * @arg SMC_FLAG_EDGE_RISING : Rising egde detection Flag.
830 * @arg SMC_FLAG_LEVEL_HIGH : High level detection Flag.
831 * @arg SMC_FLAG_EDGE_FALLING : Falling egde detection Flag.
832 * @arg SMC_FLAG_FIFO_EMPTY : FIFO empty Flag.
833 *
834 * @retval SET or RESET
835 *
836 * @note
837 */
SMC_ReadStatusFlag(SMC_BANK_NAND_T bank,SMC_FLAG_T flag)838 uint16_t SMC_ReadStatusFlag(SMC_BANK_NAND_T bank, SMC_FLAG_T flag)
839 {
840 if (bank == SMC_BANK2_NAND)
841 {
842 return (SMC_Bank2->STSINT2 & flag) ? SET : RESET;
843 }
844 else if (bank == SMC_BANK3_NAND)
845 {
846 return (SMC_Bank3->STSINT3 & flag) ? SET : RESET;
847 }
848 else
849 {
850 return (SMC_Bank4->STSINT4 & flag) ? SET : RESET;
851 }
852 }
853
854 /*!
855 * @brief Clears the SMC's pending flags.
856 *
857 * @param bank: Selects the SMC Bank.
858 * The parameter can be one of following values:
859 * @arg SMC_BANK2_NAND : SMC Bank2 NAND
860 * @arg SMC_BANK3_NAND : SMC Bank3 NAND
861 * @arg SMC_BANK4_PCCARD : SMC Bank4 PCCARD
862 *
863 * @param flag: Select the SMC interrupt sources.
864 * This parameter can be any combination of the following values:
865 * @arg SMC_FLAG_EDGE_RISING : Rising egde detection Flag.
866 * @arg SMC_FLAG_LEVEL_HIGH : High level detection Flag.
867 * @arg SMC_FLAG_EDGE_FALLING : Falling egde detection Flag.
868 *
869 * @retval None
870 */
SMC_ClearStatusFlag(SMC_BANK_NAND_T bank,uint32_t flag)871 void SMC_ClearStatusFlag(SMC_BANK_NAND_T bank, uint32_t flag)
872 {
873 if (bank == SMC_BANK2_NAND)
874 {
875 SMC_Bank2->STSINT2 &= ~flag;
876 }
877 else if (bank == SMC_BANK3_NAND)
878 {
879 SMC_Bank3->STSINT3 &= ~flag;
880 }
881 else
882 {
883 SMC_Bank4->STSINT4 &= ~flag;
884 }
885 }
886
887 /*!
888 * @brief Read the specified SMC interrupt has occurred or not.
889 *
890 * @param bank: Selects the SMC Bank.
891 * The parameter can be one of following values:
892 * @arg SMC_BANK2_NAND : SMC Bank2 NAND
893 * @arg SMC_BANK3_NAND : SMC Bank3 NAND
894 * @arg SMC_BANK4_PCCARD : SMC Bank4 PCCARD
895 *
896 * @param flag: Select the SMC interrupt source.
897 * This parameter can be one of the following values:
898 * @arg SMC_INT_EDGE_RISING : Rising edge detection interrupt.
899 * @arg SMC_INT_LEVEL_HIGH : High level edge detection interrupt.
900 * @arg SMC_INT_EDGE_FALLING : Falling edge detection interrupt.
901 *
902 * @retval The status of specified SMC interrupt source.
903 */
SMC_ReadIntFlag(SMC_BANK_NAND_T bank,SMC_INT_T flag)904 uint16_t SMC_ReadIntFlag(SMC_BANK_NAND_T bank, SMC_INT_T flag)
905 {
906 uint32_t tmpStatus = 0x0, itstatus = 0x0, itenable = 0x0;
907
908 if (bank == SMC_BANK2_NAND)
909 {
910 tmpStatus = SMC_Bank2->STSINT2;
911 }
912 else if (bank == SMC_BANK3_NAND)
913 {
914 tmpStatus = SMC_Bank3->STSINT3;
915 }
916 else
917 {
918 tmpStatus = SMC_Bank4->STSINT4;
919 }
920
921 itstatus = tmpStatus & flag;
922 itenable = tmpStatus & (flag >> 3);
923
924 if ((itstatus != RESET) && (itenable != RESET))
925 {
926 return SET;
927 }
928 else
929 {
930 return RESET;
931 }
932 }
933
934 /*!
935 * @brief Clears the SMC's interrupt Flag.
936 *
937 * @param bank: Selects the SMC Bank.
938 * The parameter can be one of following values:
939 * @arg SMC_BANK2_NAND : SMC Bank2 NAND
940 * @arg SMC_BANK3_NAND : SMC Bank3 NAND
941 * @arg SMC_BANK4_PCCARD : SMC Bank4 PCCARD
942 *
943 * @param interrupt: Select the SMC interrupt sources.
944 * This parameter can be any combination of the following values:
945 * @arg SMC_INT_EDGE_RISING : Rising edge detection interrupt.
946 * @arg SMC_INT_LEVEL_HIGH : High level edge detection interrupt.
947 * @arg SMC_INT_EDGE_FALLING : Falling edge detection interrupt.
948 *
949 * @retval None
950 */
SMC_ClearIntFlag(SMC_BANK_NAND_T bank,uint32_t flag)951 void SMC_ClearIntFlag(SMC_BANK_NAND_T bank, uint32_t flag)
952 {
953 if (bank == SMC_BANK2_NAND)
954 {
955 SMC_Bank2->STSINT2 &= ~(flag >> 3);
956 }
957 else if (bank == SMC_BANK3_NAND)
958 {
959 SMC_Bank3->STSINT3 &= ~(flag >> 3);
960 }
961 else
962 {
963 SMC_Bank4->STSINT4 &= ~(flag >> 3);
964 }
965 }
966
967 /**@} end of group SMC_Functions */
968 /**@} end of group SMC_Driver */
969 /**@} end of group APM32F4xx_StdPeriphDriver */
970