1;/*! 2; * @file startup_apm32f40x.s 3; * 4; * @brief CMSIS Cortex-M4 based Core Device Startup File for Device startup_apm32f40x 5; * 6; * @version V1.0.2 7; * 8; * @date 2022-06-23 9; * 10; * @attention 11; * 12; * Copyright (C) 2021-2022 Geehy Semiconductor 13; * 14; * You may not use this file except in compliance with the 15; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). 16; * 17; * The program is only for reference, which is distributed in the hope 18; * that it will be usefull and instructional for customers to develop 19; * their software. Unless required by applicable law or agreed to in 20; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT 21; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. 22; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions 23; * and limitations under the License. 24; */ 25 26; <h> Stack Configuration 27; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 28; </h> 29 30Stack_Size EQU 0x00000400 31 32 AREA STACK, NOINIT, READWRITE, ALIGN=3 33Stack_Mem SPACE Stack_Size 34__initial_sp 35 36; <h> Heap Configuration 37; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 38; </h> 39 40Heap_Size EQU 0x00000200 41 42 AREA HEAP, NOINIT, READWRITE, ALIGN=3 43__heap_base 44Heap_Mem SPACE Heap_Size 45__heap_limit 46 47 PRESERVE8 48 THUMB 49 50; Vector Table Mapped to Address 0 at Reset 51 AREA RESET, DATA, READONLY 52 EXPORT __Vectors 53 EXPORT __Vectors_End 54 EXPORT __Vectors_Size 55 56__Vectors DCD __initial_sp ; Top of Stack 57 DCD Reset_Handler ; Reset Handler 58 DCD NMI_Handler ; NMI Handler 59 DCD HardFault_Handler ; Hard Fault Handler 60 DCD MemManage_Handler ; MPU Fault Handler 61 DCD BusFault_Handler ; Bus Fault Handler 62 DCD UsageFault_Handler ; Usage Fault Handler 63 DCD 0 ; Reserved 64 DCD 0 ; Reserved 65 DCD 0 ; Reserved 66 DCD 0 ; Reserved 67 DCD SVC_Handler ; SVCall Handler 68 DCD DebugMon_Handler ; Debug Monitor Handler 69 DCD 0 ; Reserved 70 DCD PendSV_Handler ; PendSV Handler 71 DCD SysTick_Handler ; SysTick Handler 72 73 ; External Interrupts 74 DCD WWDT_IRQHandler ; Window WatchDog 75 DCD PVD_IRQHandler ; PVD through EINT Line detection 76 DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EINT line 77 DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EINT line 78 DCD FLASH_IRQHandler ; FLASH 79 DCD RCM_IRQHandler ; RCM 80 DCD EINT0_IRQHandler ; EINT Line0 81 DCD EINT1_IRQHandler ; EINT Line1 82 DCD EINT2_IRQHandler ; EINT Line2 83 DCD EINT3_IRQHandler ; EINT Line3 84 DCD EINT4_IRQHandler ; EINT Line4 85 DCD DMA1_STR0_IRQHandler ; DMA1 Stream 0 86 DCD DMA1_STR1_IRQHandler ; DMA1 Stream 1 87 DCD DMA1_STR2_IRQHandler ; DMA1 Stream 2 88 DCD DMA1_STR3_IRQHandler ; DMA1 Stream 3 89 DCD DMA1_STR4_IRQHandler ; DMA1 Stream 4 90 DCD DMA1_STR5_IRQHandler ; DMA1 Stream 5 91 DCD DMA1_STR6_IRQHandler ; DMA1 Stream 6 92 DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s 93 DCD CAN1_TX_IRQHandler ; CAN1 TX 94 DCD CAN1_RX0_IRQHandler ; CAN1 RX0 95 DCD CAN1_RX1_IRQHandler ; CAN1 RX1 96 DCD CAN1_SCE_IRQHandler ; CAN1 SCE 97 DCD EINT9_5_IRQHandler ; External Line[9:5]s 98 DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9 99 DCD TMR1_UP_TMR10_IRQHandler ; TMR1 Update and TMR10 100 DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11 101 DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare 102 DCD TMR2_IRQHandler ; TMR2 103 DCD TMR3_IRQHandler ; TMR3 104 DCD TMR4_IRQHandler ; TMR4 105 DCD I2C1_EV_IRQHandler ; I2C1 Event 106 DCD I2C1_ER_IRQHandler ; I2C1 Error 107 DCD I2C2_EV_IRQHandler ; I2C2 Event 108 DCD I2C2_ER_IRQHandler ; I2C2 Error 109 DCD SPI1_IRQHandler ; SPI1 110 DCD SPI2_IRQHandler ; SPI2 111 DCD USART1_IRQHandler ; USART1 112 DCD USART2_IRQHandler ; USART2 113 DCD USART3_IRQHandler ; USART3 114 DCD EINT15_10_IRQHandler ; External Line[15:10]s 115 DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EINT Line 116 DCD OTG_FS_WKUP_IRQHandler ; OTG_FS Wakeup through EINT line 117 DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12 118 DCD TMR8_UP_TMR13_IRQHandler ; TMR8 Update and TMR13 119 DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14 120 DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare 121 DCD DMA1_STR7_IRQHandler ; DMA1 Stream 7 122 DCD EMMC_IRQHandler ; EMMC 123 DCD SDIO_IRQHandler ; SDIO 124 DCD TMR5_IRQHandler ; TMR5 125 DCD SPI3_IRQHandler ; SPI3 126 DCD UART4_IRQHandler ; UART4 127 DCD UART5_IRQHandler ; UART5 128 DCD TMR6_DAC_IRQHandler ; TMR6 and DAC1&2 underrun errors 129 DCD TMR7_IRQHandler ; TMR7 130 DCD DMA2_STR0_IRQHandler ; DMA2 Stream 0 131 DCD DMA2_STR1_IRQHandler ; DMA2 Stream 1 132 DCD DMA2_STR2_IRQHandler ; DMA2 Stream 2 133 DCD DMA2_STR3_IRQHandler ; DMA2 Stream 3 134 DCD DMA2_STR4_IRQHandler ; DMA2 Stream 4 135 DCD ETH_IRQHandler ; Ethernet 136 DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EINT line 137 DCD CAN2_TX_IRQHandler ; CAN2 TX 138 DCD CAN2_RX0_IRQHandler ; CAN2 RX0 139 DCD CAN2_RX1_IRQHandler ; CAN2 RX1 140 DCD CAN2_SCE_IRQHandler ; CAN2 SCE 141 DCD OTG_FS_IRQHandler ; OTG_FS 142 DCD DMA2_STR5_IRQHandler ; DMA2 Stream 5 143 DCD DMA2_STR6_IRQHandler ; DMA2 Stream 6 144 DCD DMA2_STR7_IRQHandler ; DMA2 Stream 7 145 DCD USART6_IRQHandler ; USART6 146 DCD I2C3_EV_IRQHandler ; I2C3 event 147 DCD I2C3_ER_IRQHandler ; I2C3 error 148 DCD OTG_HS1_EP1_OUT_IRQHandler ; OTG_HS1 End Point 1 Out 149 DCD OTG_HS1_EP1_IN_IRQHandler ; OTG_HS1 End Point 1 In 150 DCD OTG_HS1_WKUP_IRQHandler ; OTG_HS1 Wakeup through EINT 151 DCD OTG_HS1_IRQHandler ; OTG_HS1 152 DCD DCI_IRQHandler ; DCI 153 DCD 0 ; Reserved 154 DCD 0 ; Reserved 155 DCD FPU_IRQHandler ; FPU 156 DCD SM3_IRQHandler ; SM3 157 DCD SM4_IRQHandler ; SM4 158 DCD BN_IRQHandler ; BN 159__Vectors_End 160 161__Vectors_Size EQU __Vectors_End - __Vectors 162 163 AREA |.text|, CODE, READONLY 164 165; Reset handler 166Reset_Handler PROC 167 EXPORT Reset_Handler [WEAK] 168 IMPORT SystemInit 169 IMPORT __main 170 LDR R0, =SystemInit 171 BLX R0 172 LDR R0, =__main 173 BX R0 174 ENDP 175 176; Dummy Exception Handlers (infinite loops which can be modified) 177 178NMI_Handler PROC 179 EXPORT NMI_Handler [WEAK] 180 B . 181 ENDP 182HardFault_Handler\ 183 PROC 184 EXPORT HardFault_Handler [WEAK] 185 B . 186 ENDP 187MemManage_Handler\ 188 PROC 189 EXPORT MemManage_Handler [WEAK] 190 B . 191 ENDP 192BusFault_Handler\ 193 PROC 194 EXPORT BusFault_Handler [WEAK] 195 B . 196 ENDP 197UsageFault_Handler\ 198 PROC 199 EXPORT UsageFault_Handler [WEAK] 200 B . 201 ENDP 202SVC_Handler PROC 203 EXPORT SVC_Handler [WEAK] 204 B . 205 ENDP 206DebugMon_Handler\ 207 PROC 208 EXPORT DebugMon_Handler [WEAK] 209 B . 210 ENDP 211PendSV_Handler PROC 212 EXPORT PendSV_Handler [WEAK] 213 B . 214 ENDP 215SysTick_Handler PROC 216 EXPORT SysTick_Handler [WEAK] 217 B . 218 ENDP 219 220Default_Handler PROC 221 222 EXPORT WWDT_IRQHandler [WEAK] 223 EXPORT PVD_IRQHandler [WEAK] 224 EXPORT TAMP_STAMP_IRQHandler [WEAK] 225 EXPORT RTC_WKUP_IRQHandler [WEAK] 226 EXPORT FLASH_IRQHandler [WEAK] 227 EXPORT RCM_IRQHandler [WEAK] 228 EXPORT EINT0_IRQHandler [WEAK] 229 EXPORT EINT1_IRQHandler [WEAK] 230 EXPORT EINT2_IRQHandler [WEAK] 231 EXPORT EINT3_IRQHandler [WEAK] 232 EXPORT EINT4_IRQHandler [WEAK] 233 EXPORT DMA1_STR0_IRQHandler [WEAK] 234 EXPORT DMA1_STR1_IRQHandler [WEAK] 235 EXPORT DMA1_STR2_IRQHandler [WEAK] 236 EXPORT DMA1_STR3_IRQHandler [WEAK] 237 EXPORT DMA1_STR4_IRQHandler [WEAK] 238 EXPORT DMA1_STR5_IRQHandler [WEAK] 239 EXPORT DMA1_STR6_IRQHandler [WEAK] 240 EXPORT ADC_IRQHandler [WEAK] 241 EXPORT CAN1_TX_IRQHandler [WEAK] 242 EXPORT CAN1_RX0_IRQHandler [WEAK] 243 EXPORT CAN1_RX1_IRQHandler [WEAK] 244 EXPORT CAN1_SCE_IRQHandler [WEAK] 245 EXPORT EINT9_5_IRQHandler [WEAK] 246 EXPORT TMR1_BRK_TMR9_IRQHandler [WEAK] 247 EXPORT TMR1_UP_TMR10_IRQHandler [WEAK] 248 EXPORT TMR1_TRG_COM_TMR11_IRQHandler [WEAK] 249 EXPORT TMR1_CC_IRQHandler [WEAK] 250 EXPORT TMR2_IRQHandler [WEAK] 251 EXPORT TMR3_IRQHandler [WEAK] 252 EXPORT TMR4_IRQHandler [WEAK] 253 EXPORT I2C1_EV_IRQHandler [WEAK] 254 EXPORT I2C1_ER_IRQHandler [WEAK] 255 EXPORT I2C2_EV_IRQHandler [WEAK] 256 EXPORT I2C2_ER_IRQHandler [WEAK] 257 EXPORT SPI1_IRQHandler [WEAK] 258 EXPORT SPI2_IRQHandler [WEAK] 259 EXPORT USART1_IRQHandler [WEAK] 260 EXPORT USART2_IRQHandler [WEAK] 261 EXPORT USART3_IRQHandler [WEAK] 262 EXPORT EINT15_10_IRQHandler [WEAK] 263 EXPORT RTC_Alarm_IRQHandler [WEAK] 264 EXPORT OTG_FS_WKUP_IRQHandler [WEAK] 265 EXPORT TMR8_BRK_TMR12_IRQHandler [WEAK] 266 EXPORT TMR8_UP_TMR13_IRQHandler [WEAK] 267 EXPORT TMR8_TRG_COM_TMR14_IRQHandler [WEAK] 268 EXPORT TMR8_CC_IRQHandler [WEAK] 269 EXPORT DMA1_STR7_IRQHandler [WEAK] 270 EXPORT EMMC_IRQHandler [WEAK] 271 EXPORT SDIO_IRQHandler [WEAK] 272 EXPORT TMR5_IRQHandler [WEAK] 273 EXPORT SPI3_IRQHandler [WEAK] 274 EXPORT UART4_IRQHandler [WEAK] 275 EXPORT UART5_IRQHandler [WEAK] 276 EXPORT TMR6_DAC_IRQHandler [WEAK] 277 EXPORT TMR7_IRQHandler [WEAK] 278 EXPORT DMA2_STR0_IRQHandler [WEAK] 279 EXPORT DMA2_STR1_IRQHandler [WEAK] 280 EXPORT DMA2_STR2_IRQHandler [WEAK] 281 EXPORT DMA2_STR3_IRQHandler [WEAK] 282 EXPORT DMA2_STR4_IRQHandler [WEAK] 283 EXPORT ETH_IRQHandler [WEAK] 284 EXPORT ETH_WKUP_IRQHandler [WEAK] 285 EXPORT CAN2_TX_IRQHandler [WEAK] 286 EXPORT CAN2_RX0_IRQHandler [WEAK] 287 EXPORT CAN2_RX1_IRQHandler [WEAK] 288 EXPORT CAN2_SCE_IRQHandler [WEAK] 289 EXPORT OTG_FS_IRQHandler [WEAK] 290 EXPORT DMA2_STR5_IRQHandler [WEAK] 291 EXPORT DMA2_STR6_IRQHandler [WEAK] 292 EXPORT DMA2_STR7_IRQHandler [WEAK] 293 EXPORT USART6_IRQHandler [WEAK] 294 EXPORT I2C3_EV_IRQHandler [WEAK] 295 EXPORT I2C3_ER_IRQHandler [WEAK] 296 EXPORT OTG_HS1_EP1_OUT_IRQHandler [WEAK] 297 EXPORT OTG_HS1_EP1_IN_IRQHandler [WEAK] 298 EXPORT OTG_HS1_WKUP_IRQHandler [WEAK] 299 EXPORT OTG_HS1_IRQHandler [WEAK] 300 EXPORT DCI_IRQHandler [WEAK] 301 EXPORT FPU_IRQHandler [WEAK] 302 EXPORT SM3_IRQHandler [WEAK] 303 EXPORT SM4_IRQHandler [WEAK] 304 EXPORT BN_IRQHandler [WEAK] 305 306WWDT_IRQHandler 307PVD_IRQHandler 308TAMP_STAMP_IRQHandler 309RTC_WKUP_IRQHandler 310FLASH_IRQHandler 311RCM_IRQHandler 312EINT0_IRQHandler 313EINT1_IRQHandler 314EINT2_IRQHandler 315EINT3_IRQHandler 316EINT4_IRQHandler 317DMA1_STR0_IRQHandler 318DMA1_STR1_IRQHandler 319DMA1_STR2_IRQHandler 320DMA1_STR3_IRQHandler 321DMA1_STR4_IRQHandler 322DMA1_STR5_IRQHandler 323DMA1_STR6_IRQHandler 324ADC_IRQHandler 325CAN1_TX_IRQHandler 326CAN1_RX0_IRQHandler 327CAN1_RX1_IRQHandler 328CAN1_SCE_IRQHandler 329EINT9_5_IRQHandler 330TMR1_BRK_TMR9_IRQHandler 331TMR1_UP_TMR10_IRQHandler 332TMR1_TRG_COM_TMR11_IRQHandler 333TMR1_CC_IRQHandler 334TMR2_IRQHandler 335TMR3_IRQHandler 336TMR4_IRQHandler 337I2C1_EV_IRQHandler 338I2C1_ER_IRQHandler 339I2C2_EV_IRQHandler 340I2C2_ER_IRQHandler 341SPI1_IRQHandler 342SPI2_IRQHandler 343USART1_IRQHandler 344USART2_IRQHandler 345USART3_IRQHandler 346EINT15_10_IRQHandler 347RTC_Alarm_IRQHandler 348OTG_FS_WKUP_IRQHandler 349TMR8_BRK_TMR12_IRQHandler 350TMR8_UP_TMR13_IRQHandler 351TMR8_TRG_COM_TMR14_IRQHandler 352TMR8_CC_IRQHandler 353DMA1_STR7_IRQHandler 354EMMC_IRQHandler 355SDIO_IRQHandler 356TMR5_IRQHandler 357SPI3_IRQHandler 358UART4_IRQHandler 359UART5_IRQHandler 360TMR6_DAC_IRQHandler 361TMR7_IRQHandler 362DMA2_STR0_IRQHandler 363DMA2_STR1_IRQHandler 364DMA2_STR2_IRQHandler 365DMA2_STR3_IRQHandler 366DMA2_STR4_IRQHandler 367ETH_IRQHandler 368ETH_WKUP_IRQHandler 369CAN2_TX_IRQHandler 370CAN2_RX0_IRQHandler 371CAN2_RX1_IRQHandler 372CAN2_SCE_IRQHandler 373OTG_FS_IRQHandler 374DMA2_STR5_IRQHandler 375DMA2_STR6_IRQHandler 376DMA2_STR7_IRQHandler 377USART6_IRQHandler 378I2C3_EV_IRQHandler 379I2C3_ER_IRQHandler 380OTG_HS1_EP1_OUT_IRQHandler 381OTG_HS1_EP1_IN_IRQHandler 382OTG_HS1_WKUP_IRQHandler 383OTG_HS1_IRQHandler 384DCI_IRQHandler 385FPU_IRQHandler 386SM3_IRQHandler 387SM4_IRQHandler 388BN_IRQHandler 389 390 B . 391 392 ENDP 393 394 ALIGN 395 396;******************************************************************************* 397; User Stack and Heap initialization 398;******************************************************************************* 399 IF :DEF:__MICROLIB 400 401 EXPORT __initial_sp 402 EXPORT __heap_base 403 EXPORT __heap_limit 404 405 ELSE 406 407 IMPORT __use_two_region_memory 408 EXPORT __user_initial_stackheap 409 410__user_initial_stackheap 411 412 LDR R0, = Heap_Mem 413 LDR R1, =(Stack_Mem + Stack_Size) 414 LDR R2, = (Heap_Mem + Heap_Size) 415 LDR R3, = Stack_Mem 416 BX LR 417 418 ALIGN 419 420 ENDIF 421 422 END 423 424;************************ (C) COPYRIGHT Geehy Semiconductor Co.,Ltd *****END OF FILE***** 425