1;/*! 2; * @file startup_apm32f40x.s 3; * 4; * @brief CMSIS Cortex-M4 based Core Device Startup File for Device startup_apm32f40x 5; * 6; * @version V1.0.2 7; * 8; * @date 2022-06-23 9; * 10; * @attention 11; * 12; * Copyright (C) 2021-2022 Geehy Semiconductor 13; * 14; * You may not use this file except in compliance with the 15; * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). 16; * 17; * The program is only for reference, which is distributed in the hope 18; * that it will be usefull and instructional for customers to develop 19; * their software. Unless required by applicable law or agreed to in 20; * writing, the program is distributed on an "AS IS" BASIS, WITHOUT 21; * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. 22; * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions 23; * and limitations under the License. 24; */ 25 26 .syntax unified 27 .cpu cortex-m4 28 .fpu softvfp 29 .thumb 30 31.global g_pfnVectors 32.global Default_Handler 33 34/* start address for the initialization values of the .data section. 35defined in linker script */ 36.word _sidata 37/* start address for the .data section. defined in linker script */ 38.word _sdata 39/* end address for the .data section. defined in linker script */ 40.word _edata 41/* start address for the .bss section. defined in linker script */ 42.word _sbss 43/* end address for the .bss section. defined in linker script */ 44.word _ebss 45/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ 46 47/** 48 * @brief This is the code that gets called when the processor first 49 * starts execution following a reset event. Only the absolutely 50 * necessary set is performed, after which the application 51 * supplied main() routine is called. 52 * @param None 53 * @retval : None 54*/ 55 56 .section .text.Reset_Handler 57 .weak Reset_Handler 58 .type Reset_Handler, %function 59Reset_Handler: 60 ldr sp, =_estack /* set stack pointer */ 61 62/* Copy the data segment initializers from flash to SRAM */ 63 movs r1, #0 64 b LoopCopyDataInit 65 66CopyDataInit: 67 ldr r3, =_sidata 68 ldr r3, [r3, r1] 69 str r3, [r0, r1] 70 adds r1, r1, #4 71 72LoopCopyDataInit: 73 ldr r0, =_sdata 74 ldr r3, =_edata 75 adds r2, r0, r1 76 cmp r2, r3 77 bcc CopyDataInit 78 ldr r2, =_sbss 79 b LoopFillZerobss 80/* Zero fill the bss segment. */ 81FillZerobss: 82 movs r3, #0 83 str r3, [r2], #4 84 85LoopFillZerobss: 86 ldr r3, = _ebss 87 cmp r2, r3 88 bcc FillZerobss 89 90/* Call the clock system intitialization function.*/ 91 bl SystemInit 92/* Call static constructors */ 93 /* bl __libc_init_array */ 94/* Call the application's entry point.*/ 95 bl entry 96 bx lr 97.size Reset_Handler, .-Reset_Handler 98 99/** 100 * @brief This is the code that gets called when the processor receives an 101 * unexpected interrupt. This simply enters an infinite loop, preserving 102 * the system state for examination by a debugger. 103 * @param None 104 * @retval None 105*/ 106 .section .text.Default_Handler,"ax",%progbits 107Default_Handler: 108Infinite_Loop: 109 b Infinite_Loop 110 .size Default_Handler, .-Default_Handler 111/****************************************************************************** 112* 113* The minimal vector table for a Cortex M4. Note that the proper constructs 114* must be placed on this to ensure that it ends up at physical address 115* 0x0000.0000. 116* 117*******************************************************************************/ 118 .section .isr_vector,"a",%progbits 119 .type g_pfnVectors, %object 120 .size g_pfnVectors, .-g_pfnVectors 121 122 123g_pfnVectors: 124 .word _estack 125 .word Reset_Handler 126 .word NMI_Handler 127 .word HardFault_Handler 128 .word MemManage_Handler 129 .word BusFault_Handler 130 .word UsageFault_Handler 131 .word 0 132 .word 0 133 .word 0 134 .word 0 135 .word SVC_Handler 136 .word DebugMon_Handler 137 .word 0 138 .word PendSV_Handler 139 .word SysTick_Handler 140 141 /* External Interrupts */ 142 .word WWDT_IRQHandler /* Window WatchDog */ 143 .word PVD_IRQHandler /* PVD through EINT Line detection */ 144 .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EINT line */ 145 .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EINT line */ 146 .word FLASH_IRQHandler /* FLASH */ 147 .word RCM_IRQHandler /* RCC */ 148 .word EINT0_IRQHandler /* EINT Line0 */ 149 .word EINT1_IRQHandler /* EINT Line1 */ 150 .word EINT2_IRQHandler /* EINT Line2 */ 151 .word EINT3_IRQHandler /* EINT Line3 */ 152 .word EINT4_IRQHandler /* EINT Line4 */ 153 .word DMA1_STR0_IRQHandler /* DMA1 Stream 0 */ 154 .word DMA1_STR1_IRQHandler /* DMA1 Stream 1 */ 155 .word DMA1_STR2_IRQHandler /* DMA1 Stream 2 */ 156 .word DMA1_STR3_IRQHandler /* DMA1 Stream 3 */ 157 .word DMA1_STR4_IRQHandler /* DMA1 Stream 4 */ 158 .word DMA1_STR5_IRQHandler /* DMA1 Stream 5 */ 159 .word DMA1_STR6_IRQHandler /* DMA1 Stream 6 */ 160 .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ 161 .word CAN1_TX_IRQHandler /* CAN1 TX */ 162 .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ 163 .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ 164 .word CAN1_SCE_IRQHandler /* CAN1 SCE */ 165 .word EINT9_5_IRQHandler /* External Line[9:5]s */ 166 .word TMR1_BRK_TMR9_IRQHandler /* TMR1 Break and TMR9 */ 167 .word TMR1_UP_TMR10_IRQHandler /* TMR1 Update and TMR10 */ 168 .word TMR1_TRG_COM_TMR11_IRQHandler /* TMR1 Trigger and Commutation and TMR11 */ 169 .word TMR1_CC_IRQHandler /* TMR1 Capture Compare */ 170 .word TMR2_IRQHandler /* TMR2 */ 171 .word TMR3_IRQHandler /* TMR3 */ 172 .word TMR4_IRQHandler /* TMR4 */ 173 .word I2C1_EV_IRQHandler /* I2C1 Event */ 174 .word I2C1_ER_IRQHandler /* I2C1 Error */ 175 .word I2C2_EV_IRQHandler /* I2C2 Event */ 176 .word I2C2_ER_IRQHandler /* I2C2 Error */ 177 .word SPI1_IRQHandler /* SPI1 */ 178 .word SPI2_IRQHandler /* SPI2 */ 179 .word USART1_IRQHandler /* USART1 */ 180 .word USART2_IRQHandler /* USART2 */ 181 .word USART3_IRQHandler /* USART3 */ 182 .word EINT15_10_IRQHandler /* External Line[15:10]s */ 183 .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EINT Line */ 184 .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EINT line */ 185 .word TMR8_BRK_TMR12_IRQHandler /* TMR8 Break and TMR12 */ 186 .word TMR8_UP_TMR13_IRQHandler /* TMR8 Update and TMR13 */ 187 .word TMR8_TRG_COM_TMR14_IRQHandler /* TMR8 Trigger and Commutation and TMR14 */ 188 .word TMR8_CC_IRQHandler /* TMR8 Capture Compare */ 189 .word DMA1_STR7_IRQHandler /* DMA1 Stream7 */ 190 .word EMMC_IRQHandler /* EMMC */ 191 .word SDIO_IRQHandler /* SDIO */ 192 .word TMR5_IRQHandler /* TMR5 */ 193 .word SPI3_IRQHandler /* SPI3 */ 194 .word UART4_IRQHandler /* UART4 */ 195 .word UART5_IRQHandler /* UART5 */ 196 .word TMR6_DAC_IRQHandler /* TMR6 and DAC1&2 underrun errors */ 197 .word TMR7_IRQHandler /* TMR7 */ 198 .word DMA2_STR0_IRQHandler /* DMA2 Stream 0 */ 199 .word DMA2_STR1_IRQHandler /* DMA2 Stream 1 */ 200 .word DMA2_STR2_IRQHandler /* DMA2 Stream 2 */ 201 .word DMA2_STR3_IRQHandler /* DMA2 Stream 3 */ 202 .word DMA2_STR4_IRQHandler /* DMA2 Stream 4 */ 203 .word ETH_IRQHandler /* Ethernet */ 204 .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EINT line */ 205 .word CAN2_TX_IRQHandler /* CAN2 TX */ 206 .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ 207 .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ 208 .word CAN2_SCE_IRQHandler /* CAN2 SCE */ 209 .word OTG_FS_IRQHandler /* USB OTG FS */ 210 .word DMA2_STR5_IRQHandler /* DMA2 Stream 5 */ 211 .word DMA2_STR6_IRQHandler /* DMA2 Stream 6 */ 212 .word DMA2_STR7_IRQHandler /* DMA2 Stream 7 */ 213 .word USART6_IRQHandler /* USART6 */ 214 .word I2C3_EV_IRQHandler /* I2C3 event */ 215 .word I2C3_ER_IRQHandler /* I2C3 error */ 216 .word OTG_HS1_EP1_OUT_IRQHandler /* USB OTG HS1 End Point 1 Out */ 217 .word OTG_HS1_EP1_IN_IRQHandler /* USB OTG HS1 End Point 1 In */ 218 .word OTG_HS1_WKUP_IRQHandler /* USB OTG HS1 Wakeup through EINT */ 219 .word OTG_HS1_IRQHandler /* USB OTG HS1 */ 220 .word DCI_IRQHandler /* DCI */ 221 .word 0 /* Reserved */ 222 .word 0 /* Reserved */ 223 .word FPU_IRQHandler /* FPU */ 224 .word SM3_IRQHandler /* SM3 */ 225 .word SM4_IRQHandler /* SM4 */ 226 .word BN_IRQHandler /* BN */ 227 228/******************************************************************************* 229* 230* Provide weak aliases for each Exception handler to the Default_Handler. 231* As they are weak aliases, any function with the same name will override 232* this definition. 233* 234*******************************************************************************/ 235 .weak NMI_Handler 236 .thumb_set NMI_Handler,Default_Handler 237 238 .weak HardFault_Handler 239 .thumb_set HardFault_Handler,Default_Handler 240 241 .weak MemManage_Handler 242 .thumb_set MemManage_Handler,Default_Handler 243 244 .weak BusFault_Handler 245 .thumb_set BusFault_Handler,Default_Handler 246 247 .weak UsageFault_Handler 248 .thumb_set UsageFault_Handler,Default_Handler 249 250 .weak SVC_Handler 251 .thumb_set SVC_Handler,Default_Handler 252 253 .weak DebugMon_Handler 254 .thumb_set DebugMon_Handler,Default_Handler 255 256 .weak PendSV_Handler 257 .thumb_set PendSV_Handler,Default_Handler 258 259 .weak SysTick_Handler 260 .thumb_set SysTick_Handler,Default_Handler 261 262 .weak WWDT_IRQHandler 263 .thumb_set WWDT_IRQHandler,Default_Handler 264 265 .weak PVD_IRQHandler 266 .thumb_set PVD_IRQHandler,Default_Handler 267 268 .weak TAMP_STAMP_IRQHandler 269 .thumb_set TAMP_STAMP_IRQHandler,Default_Handler 270 271 .weak RTC_WKUP_IRQHandler 272 .thumb_set RTC_WKUP_IRQHandler,Default_Handler 273 274 .weak FLASH_IRQHandler 275 .thumb_set FLASH_IRQHandler,Default_Handler 276 277 .weak RCM_IRQHandler 278 .thumb_set RCM_IRQHandler,Default_Handler 279 280 .weak EINT0_IRQHandler 281 .thumb_set EINT0_IRQHandler,Default_Handler 282 283 .weak EINT1_IRQHandler 284 .thumb_set EINT1_IRQHandler,Default_Handler 285 286 .weak EINT2_IRQHandler 287 .thumb_set EINT2_IRQHandler,Default_Handler 288 289 .weak EINT3_IRQHandler 290 .thumb_set EINT3_IRQHandler,Default_Handler 291 292 .weak EINT4_IRQHandler 293 .thumb_set EINT4_IRQHandler,Default_Handler 294 295 .weak DMA1_STR0_IRQHandler 296 .thumb_set DMA1_STR0_IRQHandler,Default_Handler 297 298 .weak DMA1_STR1_IRQHandler 299 .thumb_set DMA1_STR1_IRQHandler,Default_Handler 300 301 .weak DMA1_STR2_IRQHandler 302 .thumb_set DMA1_STR2_IRQHandler,Default_Handler 303 304 .weak DMA1_STR3_IRQHandler 305 .thumb_set DMA1_STR3_IRQHandler,Default_Handler 306 307 .weak DMA1_STR4_IRQHandler 308 .thumb_set DMA1_STR4_IRQHandler,Default_Handler 309 310 .weak DMA1_STR5_IRQHandler 311 .thumb_set DMA1_STR5_IRQHandler,Default_Handler 312 313 .weak DMA1_STR6_IRQHandler 314 .thumb_set DMA1_STR6_IRQHandler,Default_Handler 315 316 .weak ADC_IRQHandler 317 .thumb_set ADC_IRQHandler,Default_Handler 318 319 .weak CAN1_TX_IRQHandler 320 .thumb_set CAN1_TX_IRQHandler,Default_Handler 321 322 .weak CAN1_RX0_IRQHandler 323 .thumb_set CAN1_RX0_IRQHandler,Default_Handler 324 325 .weak CAN1_RX1_IRQHandler 326 .thumb_set CAN1_RX1_IRQHandler,Default_Handler 327 328 .weak CAN1_SCE_IRQHandler 329 .thumb_set CAN1_SCE_IRQHandler,Default_Handler 330 331 .weak EINT9_5_IRQHandler 332 .thumb_set EINT9_5_IRQHandler,Default_Handler 333 334 .weak TMR1_BRK_TMR9_IRQHandler 335 .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler 336 337 .weak TMR1_UP_TMR10_IRQHandler 338 .thumb_set TMR1_UP_TMR10_IRQHandler,Default_Handler 339 340 .weak TMR1_TRG_COM_TMR11_IRQHandler 341 .thumb_set TMR1_TRG_COM_TMR11_IRQHandler,Default_Handler 342 343 .weak TMR1_CC_IRQHandler 344 .thumb_set TMR1_CC_IRQHandler,Default_Handler 345 346 .weak TMR2_IRQHandler 347 .thumb_set TMR2_IRQHandler,Default_Handler 348 349 .weak TMR3_IRQHandler 350 .thumb_set TMR3_IRQHandler,Default_Handler 351 352 .weak TMR4_IRQHandler 353 .thumb_set TMR4_IRQHandler,Default_Handler 354 355 .weak I2C1_EV_IRQHandler 356 .thumb_set I2C1_EV_IRQHandler,Default_Handler 357 358 .weak I2C1_ER_IRQHandler 359 .thumb_set I2C1_ER_IRQHandler,Default_Handler 360 361 .weak I2C2_EV_IRQHandler 362 .thumb_set I2C2_EV_IRQHandler,Default_Handler 363 364 .weak I2C2_ER_IRQHandler 365 .thumb_set I2C2_ER_IRQHandler,Default_Handler 366 367 .weak SPI1_IRQHandler 368 .thumb_set SPI1_IRQHandler,Default_Handler 369 370 .weak SPI2_IRQHandler 371 .thumb_set SPI2_IRQHandler,Default_Handler 372 373 .weak USART1_IRQHandler 374 .thumb_set USART1_IRQHandler,Default_Handler 375 376 .weak USART2_IRQHandler 377 .thumb_set USART2_IRQHandler,Default_Handler 378 379 .weak USART3_IRQHandler 380 .thumb_set USART3_IRQHandler,Default_Handler 381 382 .weak EINT15_10_IRQHandler 383 .thumb_set EINT15_10_IRQHandler,Default_Handler 384 385 .weak RTC_Alarm_IRQHandler 386 .thumb_set RTC_Alarm_IRQHandler,Default_Handler 387 388 .weak OTG_FS_WKUP_IRQHandler 389 .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler 390 391 .weak TMR8_BRK_TMR12_IRQHandler 392 .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler 393 394 .weak TMR8_UP_TMR13_IRQHandler 395 .thumb_set TMR8_UP_TMR13_IRQHandler,Default_Handler 396 397 .weak TMR8_TRG_COM_TMR14_IRQHandler 398 .thumb_set TMR8_TRG_COM_TMR14_IRQHandler,Default_Handler 399 400 .weak TMR8_CC_IRQHandler 401 .thumb_set TMR8_CC_IRQHandler,Default_Handler 402 403 .weak DMA1_STR7_IRQHandler 404 .thumb_set DMA1_STR7_IRQHandler,Default_Handler 405 406 .weak EMMC_IRQHandler 407 .thumb_set EMMC_IRQHandler,Default_Handler 408 409 .weak SDIO_IRQHandler 410 .thumb_set SDIO_IRQHandler,Default_Handler 411 412 .weak TMR5_IRQHandler 413 .thumb_set TMR5_IRQHandler,Default_Handler 414 415 .weak SPI3_IRQHandler 416 .thumb_set SPI3_IRQHandler,Default_Handler 417 418 .weak UART4_IRQHandler 419 .thumb_set UART4_IRQHandler,Default_Handler 420 421 .weak UART5_IRQHandler 422 .thumb_set UART5_IRQHandler,Default_Handler 423 424 .weak TMR6_DAC_IRQHandler 425 .thumb_set TMR6_DAC_IRQHandler,Default_Handler 426 427 .weak TMR7_IRQHandler 428 .thumb_set TMR7_IRQHandler,Default_Handler 429 430 .weak DMA2_STR0_IRQHandler 431 .thumb_set DMA2_STR0_IRQHandler,Default_Handler 432 433 .weak DMA2_STR1_IRQHandler 434 .thumb_set DMA2_STR1_IRQHandler,Default_Handler 435 436 .weak DMA2_STR2_IRQHandler 437 .thumb_set DMA2_STR2_IRQHandler,Default_Handler 438 439 .weak DMA2_STR3_IRQHandler 440 .thumb_set DMA2_STR3_IRQHandler,Default_Handler 441 442 .weak DMA2_STR4_IRQHandler 443 .thumb_set DMA2_STR4_IRQHandler,Default_Handler 444 445 .weak ETH_IRQHandler 446 .thumb_set ETH_IRQHandler,Default_Handler 447 448 .weak ETH_WKUP_IRQHandler 449 .thumb_set ETH_WKUP_IRQHandler,Default_Handler 450 451 .weak CAN2_TX_IRQHandler 452 .thumb_set CAN2_TX_IRQHandler,Default_Handler 453 454 .weak CAN2_RX0_IRQHandler 455 .thumb_set CAN2_RX0_IRQHandler,Default_Handler 456 457 .weak CAN2_RX1_IRQHandler 458 .thumb_set CAN2_RX1_IRQHandler,Default_Handler 459 460 .weak CAN2_SCE_IRQHandler 461 .thumb_set CAN2_SCE_IRQHandler,Default_Handler 462 463 .weak OTG_FS_IRQHandler 464 .thumb_set OTG_FS_IRQHandler,Default_Handler 465 466 .weak DMA2_STR5_IRQHandler 467 .thumb_set DMA2_STR5_IRQHandler,Default_Handler 468 469 .weak DMA2_STR6_IRQHandler 470 .thumb_set DMA2_STR6_IRQHandler,Default_Handler 471 472 .weak DMA2_STR7_IRQHandler 473 .thumb_set DMA2_STR7_IRQHandler,Default_Handler 474 475 .weak USART6_IRQHandler 476 .thumb_set USART6_IRQHandler,Default_Handler 477 478 .weak I2C3_EV_IRQHandler 479 .thumb_set I2C3_EV_IRQHandler,Default_Handler 480 481 .weak I2C3_ER_IRQHandler 482 .thumb_set I2C3_ER_IRQHandler,Default_Handler 483 484 .weak OTG_HS1_EP1_OUT_IRQHandler 485 .thumb_set OTG_HS1_EP1_OUT_IRQHandler,Default_Handler 486 487 .weak OTG_HS1_EP1_IN_IRQHandler 488 .thumb_set OTG_HS1_EP1_IN_IRQHandler,Default_Handler 489 490 .weak OTG_HS1_WKUP_IRQHandler 491 .thumb_set OTG_HS1_WKUP_IRQHandler,Default_Handler 492 493 .weak OTG_HS1_IRQHandler 494 .thumb_set OTG_HS1_IRQHandler,Default_Handler 495 496 .weak DCI_IRQHandler 497 .thumb_set DCI_IRQHandler,Default_Handler 498 499 .weak FPU_IRQHandler 500 .thumb_set FPU_IRQHandler,Default_Handler 501 502 .weak SM3_IRQHandler 503 .thumb_set SM3_IRQHandler,Default_Handler 504 505 .weak SM4_IRQHandler 506 .thumb_set SM4_IRQHandler,Default_Handler 507 508 .weak BN_IRQHandler 509 .thumb_set BN_IRQHandler,Default_Handler 510 511