1 /*! 2 * @file apm32s10x_qspi.h 3 * 4 * @brief This file contains all the prototypes,enumeration and macros for the QSPI peripheral 5 * 6 * @version V1.0.1 7 * 8 * @date 2022-12-31 9 * 10 * @attention 11 * 12 * Copyright (C) 2022-2023 Geehy Semiconductor 13 * 14 * You may not use this file except in compliance with the 15 * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE). 16 * 17 * The program is only for reference, which is distributed in the hope 18 * that it will be usefull and instructional for customers to develop 19 * their software. Unless required by applicable law or agreed to in 20 * writing, the program is distributed on an "AS IS" BASIS, WITHOUT 21 * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions 23 * and limitations under the License. 24 */ 25 26 /* Define to prevent recursive inclusion */ 27 #ifndef __APM32S10X_QSPI_H 28 #define __APM32S10X_QSPI_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #include "apm32s10x.h" 35 36 /** @addtogroup APM32S10x_StdPeriphDriver 37 @{ 38 */ 39 40 /** @addtogroup QSPI_Driver QSPI Driver 41 @{ 42 */ 43 44 /** @defgroup QSPI_Macros Macros 45 @{ 46 */ 47 48 /* CTRL1 register reset value */ 49 #define QSPI_CTRL1_RESET_VALUE ((uint32_t)0x4007) 50 /* CTRL2 register reset value */ 51 #define QSPI_CTRL2_RESET_VALUE ((uint32_t)0x00) 52 /* SSIEN register reset value */ 53 #define QSPI_SSIEN_RESET_VALUE ((uint32_t)0x00) 54 /* SLAEN register reset value */ 55 #define QSPI_SLAEN_RESET_VALUE ((uint32_t)0x00) 56 /* BR register reset value */ 57 #define QSPI_BR_RESET_VALUE ((uint32_t)0x00) 58 /* TFTL register reset value */ 59 #define QSPI_TFTL_RESET_VALUE ((uint32_t)0x00) 60 /* RFTL register reset value */ 61 #define QSPI_RFTL_RESET_VALUE ((uint32_t)0x00) 62 /* TFL register reset value */ 63 #define QSPI_TFL_RESET_VALUE ((uint32_t)0x00) 64 /* RFL register reset value */ 65 #define QSPI_RFL_RESET_VALUE ((uint32_t)0x00) 66 /* STS register reset value */ 67 #define QSPI_STS_RESET_VALUE ((uint32_t)0x06) 68 /* INTEN register reset value */ 69 #define QSPI_INTEN_RESET_VALUE ((uint32_t)0x7F) 70 /* RSD register reset value */ 71 #define QSPI_RSD_RESET_VALUE ((uint32_t)0x00) 72 /* CTRL3 register reset value */ 73 #define QSPI_CTRL3_RESET_VALUE ((uint32_t)0x200) 74 /* IOSW register reset value */ 75 #define QSPI_IOSW_RESET_VALUE ((uint32_t)0x00) 76 77 /**@} end of group QSPI_Macros */ 78 79 /** @defgroup QSPI_Enumerations Enumerations 80 @{ 81 */ 82 83 /** 84 * @brief Frame format 85 */ 86 typedef enum 87 { 88 QSPI_FRF_STANDARD, /*!< Standard mode */ 89 QSPI_FRF_DUAL, /*!< Dual SPI */ 90 QSPI_FRF_QUAD /*!< QUAD SPI */ 91 } QSPI_FRF_T; 92 93 /** 94 * @brief Transmission mode 95 */ 96 typedef enum 97 { 98 QSPI_TRANS_MODE_TX_RX, /*!< TX and RX mode */ 99 QSPI_TRANS_MODE_TX, /*!< TX mode only */ 100 QSPI_TRANS_MODE_RX, /*!< RX mode only */ 101 QSPI_TRANS_MODE_EEPROM_READ /*!< EEPROM read mode */ 102 } QSPI_TRANS_MODE_T; 103 104 /** 105 * @brief Clock polarity 106 */ 107 typedef enum 108 { 109 QSPI_CLKPOL_LOW, 110 QSPI_CLKPOL_HIGH 111 } QSPI_CLKPOL_T; 112 113 /** 114 * @brief Clock phase 115 */ 116 typedef enum 117 { 118 QSPI_CLKPHA_1EDGE, 119 QSPI_CLKPHA_2EDGE 120 } QSPI_CLKPHA_T; 121 122 /** 123 * @brief Data format size 124 */ 125 typedef enum 126 { 127 QSPI_DFS_4BIT = 3, 128 QSPI_DFS_5BIT, 129 QSPI_DFS_6BIT, 130 QSPI_DFS_7BIT, 131 QSPI_DFS_8BIT, 132 QSPI_DFS_9BIT, 133 QSPI_DFS_10BIT, 134 QSPI_DFS_11BIT, 135 QSPI_DFS_12BIT, 136 QSPI_DFS_13BIT, 137 QSPI_DFS_14BIT, 138 QSPI_DFS_15BIT, 139 QSPI_DFS_16BIT, 140 QSPI_DFS_17BIT, 141 QSPI_DFS_18BIT, 142 QSPI_DFS_19BIT, 143 QSPI_DFS_20BIT, 144 QSPI_DFS_21BIT, 145 QSPI_DFS_22BIT, 146 QSPI_DFS_23BIT, 147 QSPI_DFS_24BIT, 148 QSPI_DFS_25BIT, 149 QSPI_DFS_26BIT, 150 QSPI_DFS_27BIT, 151 QSPI_DFS_28BIT, 152 QSPI_DFS_29BIT, 153 QSPI_DFS_30BIT, 154 QSPI_DFS_31BIT, 155 QSPI_DFS_32BIT 156 } QSPI_DFS_T; 157 158 /** 159 * @brief QSPI flag 160 */ 161 typedef enum 162 { 163 QSPI_FLAG_BUSY = BIT0, /*!< Busy flag */ 164 QSPI_FLAG_TFNF = BIT1, /*!< TX FIFO not full flag */ 165 QSPI_FLAG_TFE = BIT2, /*!< TX FIFO empty flag */ 166 QSPI_FLAG_RFNE = BIT3, /*!< RX FIFO not empty flag */ 167 QSPI_FLAG_RFF = BIT4, /*!< RX FIFO full flag */ 168 QSPI_FLAG_DCE = BIT6 /*!< Data collision error */ 169 } QSPI_FLAG_T; 170 171 /** 172 * @brief QSPI interrupt source 173 */ 174 typedef enum 175 { 176 QSPI_INT_TFE = BIT0, /*!< TX FIFO empty interrupt */ 177 QSPI_INT_TFO = BIT1, /*!< TX FIFO overflow interrupt */ 178 QSPI_INT_RFU = BIT2, /*!< RX FIFO underflow interrupt */ 179 QSPI_INT_RFO = BIT3, /*!< RX FIFO overflow interrupt */ 180 QSPI_INT_RFF = BIT4, /*!< RX FIFO full interrupt */ 181 QSPI_INT_MST = BIT5 /*!< Master interrupt */ 182 } QSPI_INT_T; 183 184 /** 185 * @brief QSPI interrupt flag 186 */ 187 typedef enum 188 { 189 QSPI_INT_FLAG_TFE = BIT0, /*!< TX FIFO empty interrupt flag */ 190 QSPI_INT_FLAG_TFO = BIT1, /*!< TX FIFO overflow interrupt flag */ 191 QSPI_INT_FLAG_RFU = BIT2, /*!< RX FIFO underflow interrupt flag */ 192 QSPI_INT_FLAG_RFO = BIT3, /*!< RX FIFO overflow interrupt flag */ 193 QSPI_INT_FLAG_RFF = BIT4, /*!< RX FIFO full interrupt flag */ 194 QSPI_INT_FLAG_MST = BIT5 /*!< Master interrupt flag */ 195 } QSPI_INT_FLAG_T; 196 197 /** 198 * @brief Reception sample edge 199 */ 200 typedef enum 201 { 202 QSPI_RSE_RISING, 203 QSPI_RSE_FALLING 204 } QSPI_RSE_T; 205 206 /** 207 * @brief Instruction length 208 */ 209 typedef enum 210 { 211 QSPI_INST_LEN_0, 212 QSPI_INST_LEN_4BIT, 213 QSPI_INST_LEN_8BIT, 214 QSPI_INST_LEN_16BIT 215 } QSPI_INST_LEN_T; 216 217 /** 218 * @brief QSPI address length 219 */ 220 typedef enum 221 { 222 QSPI_ADDR_LEN_0, 223 QSPI_ADDR_LEN_4BIT, 224 QSPI_ADDR_LEN_8BIT, 225 QSPI_ADDR_LEN_12BIT, 226 QSPI_ADDR_LEN_16BIT, 227 QSPI_ADDR_LEN_20BIT, 228 QSPI_ADDR_LEN_24BIT, 229 QSPI_ADDR_LEN_28BIT, 230 QSPI_ADDR_LEN_32BIT, 231 QSPI_ADDR_LEN_36BIT, 232 QSPI_ADDR_LEN_40BIT, 233 QSPI_ADDR_LEN_44BIT, 234 QSPI_ADDR_LEN_48BIT, 235 QSPI_ADDR_LEN_52BIT, 236 QSPI_ADDR_LEN_56BIT, 237 QSPI_ADDR_LEN_60BIT 238 } QSPI_ADDR_LEN_T; 239 240 /** 241 * @brief Instruction and address transmission mode 242 */ 243 typedef enum 244 { 245 QSPI_INST_ADDR_TYPE_STANDARD, 246 QSPI_INST_TYPE_STANDARD, 247 QSPI_INST_ADDR_TYPE_FRF 248 } QSPI_INST_ADDR_TYPE_T; 249 250 /** 251 * @brief Slave Select Toggle 252 */ 253 typedef enum 254 { 255 QSPI_SST_DISABLE, 256 QSPI_SST_ENABLE 257 } QSPI_SST_T; 258 259 /**@} end of group QSPI_Enumerations */ 260 261 /** @defgroup QSPI_Structures Structures 262 @{ 263 */ 264 typedef struct 265 { 266 QSPI_SST_T selectSlaveToggle; /*!< Slave Select Toggle */ 267 QSPI_FRF_T frameFormat; /*!< Frame format */ 268 uint16_t clockDiv; /*!< Clock divider */ 269 QSPI_CLKPOL_T clockPolarity; /*!< Clock polarity */ 270 QSPI_CLKPHA_T clockPhase; /*!< Clock phase */ 271 QSPI_DFS_T dataFrameSize; /*!< Data frame size */ 272 } QSPI_Config_T; 273 274 /**@} end of group QSPI_Structures */ 275 276 /** @defgroup QSPI_Functions Functions 277 @{ 278 */ 279 280 /* Reset */ 281 void QSPI_Reset(void); 282 283 /* Configuration */ 284 void QSPI_Config(QSPI_Config_T* qspiConfig); 285 void QSPI_ConfigStructInit(QSPI_Config_T* qspiConfig); 286 287 /* Data frame size, frame number, frame format */ 288 void QSPI_ConfigFrameNum(uint16_t num); 289 void QSPI_ConfigDataFrameSize(QSPI_DFS_T dfs); 290 void QSPI_ConfigFrameFormat(QSPI_FRF_T frameFormat); 291 292 /* Disable or Enable */ 293 void QSPI_Enable(void); 294 void QSPI_Disable(void); 295 296 /* TX and RX FIFO */ 297 uint8_t QSPI_ReadTxFifoDataNum(void); 298 uint8_t QSPI_ReadRxFifoDataNum(void); 299 void QSPI_ConfigRxFifoThreshold(uint8_t threshold); 300 void QSPI_ConfigTxFifoThreshold(uint8_t threshold); 301 void QSPI_ConfigTxFifoEmptyThreshold(uint8_t threshold); 302 303 /* RX Sample */ 304 void QSPI_ConfigRxSampleEdge(QSPI_RSE_T rse); 305 void QSPI_ConfigRxSampleDelay(uint8_t delay); 306 307 /* Clock stretch */ 308 void QSPI_EnableClockStretch(void); 309 void QSPI_DisableClockStretch(void); 310 311 /* Instruction, address, Wait cycle */ 312 void QSPI_ConfigInstLen(QSPI_INST_LEN_T len); 313 void QSPI_ConfigAddrLen(QSPI_ADDR_LEN_T len); 314 void QSPI_ConfigInstAddrType(QSPI_INST_ADDR_TYPE_T type); 315 void QSPI_ConfigWaitCycle(uint8_t cycle); 316 317 /* IO */ 318 void QSPI_OpenIO(void); 319 void QSPI_CloseIO(void); 320 321 /* Transmission mode */ 322 void QSPI_ConfigTansMode(QSPI_TRANS_MODE_T mode); 323 324 /* Rx and Tx data */ 325 uint32_t QSPI_RxData(void); 326 void QSPI_TxData(uint32_t data); 327 328 /* Slave */ 329 void QSPI_EnableSlave(void); 330 void QSPI_DisableSlave(void); 331 332 /* Interrupt */ 333 void QSPI_EnableInterrupt(uint32_t interrupt); 334 void QSPI_DisableInterrupt(uint32_t interrupt); 335 336 /* Flag */ 337 uint8_t QSPI_ReadStatusFlag(QSPI_FLAG_T flag); 338 void QSPI_ClearStatusFlag(void); 339 uint8_t QSPI_ReadIntFlag(QSPI_INT_FLAG_T flag); 340 void QSPI_ClearIntFlag(uint32_t flag); 341 342 /**@} end of group QSPI_Functions */ 343 /**@} end of group QSPI_Driver */ 344 /**@} end of group APM32S10x_StdPeriphDriver */ 345 346 #ifdef __cplusplus 347 } 348 #endif 349 350 #endif /* __APM32S10X_QSPI_H_ */ 351