1 /* 2 * Copyright (c) 2006-2023, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2022-10-20 luobeihai first version 9 */ 10 11 #ifndef __DRV_ETH_H__ 12 #define __DRV_ETH_H__ 13 14 #include <rtthread.h> 15 #include <rthw.h> 16 #include <rtdevice.h> 17 #include <board.h> 18 19 /* The PHY ID one register */ 20 #define PHY_ID1_REG 0x02U 21 22 23 #ifdef PHY_USING_LAN8720A 24 /* The PHY interrupt source flag register. */ 25 #define PHY_INTERRUPT_FLAG_REG 0x1DU 26 /* The PHY interrupt mask register. */ 27 #define PHY_INTERRUPT_MASK_REG 0x1EU 28 #define PHY_LINK_DOWN_MASK (1<<4) 29 #define PHY_AUTO_NEGO_COMPLETE_MASK (1<<6) 30 31 /* The PHY status register. */ 32 #define PHY_Status_REG 0x1FU 33 #define PHY_10M_MASK (1<<2) 34 #define PHY_100M_MASK (1<<3) 35 #define PHY_FULL_DUPLEX_MASK (1<<4) 36 #define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK) 37 #define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK) 38 #define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK) 39 40 #elif defined(PHY_USING_DM9161CEP) 41 #define PHY_Status_REG 0x11U 42 #define PHY_10M_MASK ((1<<12) || (1<<13)) 43 #define PHY_100M_MASK ((1<<14) || (1<<15)) 44 #define PHY_FULL_DUPLEX_MASK ((1<<15) || (1<<13)) 45 #define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK) 46 #define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK) 47 #define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK) 48 /* The PHY interrupt source flag register. */ 49 #define PHY_INTERRUPT_FLAG_REG 0x15U 50 /* The PHY interrupt mask register. */ 51 #define PHY_INTERRUPT_MASK_REG 0x15U 52 #define PHY_LINK_CHANGE_FLAG (1<<2) 53 #define PHY_LINK_CHANGE_MASK (1<<9) 54 #define PHY_INT_MASK 0 55 56 #elif defined(PHY_USING_DP83848C) 57 #define PHY_Status_REG 0x10U 58 #define PHY_10M_MASK (1<<1) 59 #define PHY_FULL_DUPLEX_MASK (1<<2) 60 #define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK) 61 #define PHY_Status_SPEED_100M(sr) (!PHY_Status_SPEED_10M(sr)) 62 #define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK) 63 /* The PHY interrupt source flag register. */ 64 #define PHY_INTERRUPT_FLAG_REG 0x12U 65 #define PHY_LINK_CHANGE_FLAG (1<<13) 66 /* The PHY interrupt control register. */ 67 #define PHY_INTERRUPT_CTRL_REG 0x11U 68 #define PHY_INTERRUPT_EN ((1<<0)|(1<<1)) 69 /* The PHY interrupt mask register. */ 70 #define PHY_INTERRUPT_MASK_REG 0x12U 71 #define PHY_INT_MASK (1<<5) 72 #endif 73 74 #ifdef PHY_USING_LAN8742A 75 /* The PHY interrupt source flag register. */ 76 #define PHY_INTERRUPT_FLAG_REG 0x1DU 77 /* The PHY interrupt mask register. */ 78 #define PHY_INTERRUPT_MASK_REG 0x1EU 79 #define PHY_LINK_DOWN_MASK (1<<4) 80 #define PHY_AUTO_NEGO_COMPLETE_MASK (1<<6) 81 82 /* The PHY status register. */ 83 #define PHY_Status_REG 0x1FU 84 #define PHY_10M_MASK (1<<2) 85 #define PHY_100M_MASK (1<<3) 86 #define PHY_FULL_DUPLEX_MASK (1<<4) 87 #define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK) 88 #define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK) 89 #define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK) 90 #endif /* PHY_USING_LAN8742A */ 91 92 #endif /* __DRV_ETH_H__ */ 93