1 /*
2 * Copyright (c) 2006-2023, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2020-08-20 Abbcc first version
9 * 2022-07-15 Aligagago add apm32F4 series MCU support
10 * 2022-12-26 luobeihai add apm32F0 series MCU support
11 * 2022-03-18 luobeihai fix warning about incompatible function pointer types
12 * 2023-03-27 luobeihai add APM32E1/S1 series MCU support
13 */
14
15 #include <board.h>
16 #include "drv_gpio.h"
17
18 #ifdef RT_USING_PIN
19
20 #define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu)))
21 #define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu))
22 #define PIN_NO(pin) ((uint8_t)((pin) & 0xFu))
23
24 #define PIN_APMPORT(pin) ((GPIO_T *)(GPIOA_BASE + (0x400u * PIN_PORT(pin))))
25 #define PIN_APMPIN(pin) ((uint16_t)(1u << PIN_NO(pin)))
26
27 #if defined(GPIOZ)
28 #define __APM32_PORT_MAX 12u
29 #elif defined(GPIOK)
30 #define __APM32_PORT_MAX 11u
31 #elif defined(GPIOJ)
32 #define __APM32_PORT_MAX 10u
33 #elif defined(GPIOI)
34 #define __APM32_PORT_MAX 9u
35 #elif defined(GPIOH)
36 #define __APM32_PORT_MAX 8u
37 #elif defined(GPIOG)
38 #define __APM32_PORT_MAX 7u
39 #elif defined(GPIOF)
40 #define __APM32_PORT_MAX 6u
41 #elif defined(GPIOE)
42 #define __APM32_PORT_MAX 5u
43 #elif defined(GPIOD)
44 #define __APM32_PORT_MAX 4u
45 #elif defined(GPIOC)
46 #define __APM32_PORT_MAX 3u
47 #elif defined(GPIOB)
48 #define __APM32_PORT_MAX 2u
49 #elif defined(GPIOA)
50 #define __APM32_PORT_MAX 1u
51 #else
52 #define __APM32_PORT_MAX 0u
53 #error Unsupported APM32 GPIO peripheral.
54 #endif
55
56 #define PIN_APMPORT_MAX __APM32_PORT_MAX
57
58 static const struct pin_irq_map pin_irq_map[] =
59 {
60 #if defined(SOC_SERIES_APM32F0)
61 {GPIO_PIN_0, EINT0_1_IRQn},
62 {GPIO_PIN_1, EINT0_1_IRQn},
63 {GPIO_PIN_2, EINT2_3_IRQn},
64 {GPIO_PIN_3, EINT2_3_IRQn},
65 {GPIO_PIN_4, EINT4_15_IRQn},
66 {GPIO_PIN_5, EINT4_15_IRQn},
67 {GPIO_PIN_6, EINT4_15_IRQn},
68 {GPIO_PIN_7, EINT4_15_IRQn},
69 {GPIO_PIN_8, EINT4_15_IRQn},
70 {GPIO_PIN_9, EINT4_15_IRQn},
71 {GPIO_PIN_10, EINT4_15_IRQn},
72 {GPIO_PIN_11, EINT4_15_IRQn},
73 {GPIO_PIN_12, EINT4_15_IRQn},
74 {GPIO_PIN_13, EINT4_15_IRQn},
75 {GPIO_PIN_14, EINT4_15_IRQn},
76 {GPIO_PIN_15, EINT4_15_IRQn},
77 #elif defined(SOC_SERIES_APM32F1) || defined(SOC_SERIES_APM32E1) || defined(SOC_SERIES_APM32S1) \
78 || defined(SOC_SERIES_APM32F4)
79 {GPIO_PIN_0, EINT0_IRQn},
80 {GPIO_PIN_1, EINT1_IRQn},
81 {GPIO_PIN_2, EINT2_IRQn},
82 {GPIO_PIN_3, EINT3_IRQn},
83 {GPIO_PIN_4, EINT4_IRQn},
84 {GPIO_PIN_5, EINT9_5_IRQn},
85 {GPIO_PIN_6, EINT9_5_IRQn},
86 {GPIO_PIN_7, EINT9_5_IRQn},
87 {GPIO_PIN_8, EINT9_5_IRQn},
88 {GPIO_PIN_9, EINT9_5_IRQn},
89 {GPIO_PIN_10, EINT15_10_IRQn},
90 {GPIO_PIN_11, EINT15_10_IRQn},
91 {GPIO_PIN_12, EINT15_10_IRQn},
92 {GPIO_PIN_13, EINT15_10_IRQn},
93 {GPIO_PIN_14, EINT15_10_IRQn},
94 {GPIO_PIN_15, EINT15_10_IRQn},
95 #endif /* SOC_SERIES_APM32F0 */
96 };
97
98 static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
99 {
100 {-1, 0, RT_NULL, RT_NULL},
101 {-1, 0, RT_NULL, RT_NULL},
102 {-1, 0, RT_NULL, RT_NULL},
103 {-1, 0, RT_NULL, RT_NULL},
104 {-1, 0, RT_NULL, RT_NULL},
105 {-1, 0, RT_NULL, RT_NULL},
106 {-1, 0, RT_NULL, RT_NULL},
107 {-1, 0, RT_NULL, RT_NULL},
108 {-1, 0, RT_NULL, RT_NULL},
109 {-1, 0, RT_NULL, RT_NULL},
110 {-1, 0, RT_NULL, RT_NULL},
111 {-1, 0, RT_NULL, RT_NULL},
112 {-1, 0, RT_NULL, RT_NULL},
113 {-1, 0, RT_NULL, RT_NULL},
114 {-1, 0, RT_NULL, RT_NULL},
115 {-1, 0, RT_NULL, RT_NULL},
116 };
117 static uint32_t pin_irq_enable_mask = 0;
118
119 #define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
120
apm32_pin_get(const char * name)121 static rt_base_t apm32_pin_get(const char *name)
122 {
123 rt_base_t pin = 0;
124 int hw_port_num, hw_pin_num = 0;
125 int i, name_len;
126
127 name_len = rt_strlen(name);
128
129 if ((name_len < 4) || (name_len >= 6))
130 {
131 return -RT_EINVAL;
132 }
133 if ((name[0] != 'P') || (name[2] != '.'))
134 {
135 return -RT_EINVAL;
136 }
137
138 if ((name[1] >= 'A') && (name[1] <= 'Z'))
139 {
140 hw_port_num = (int)(name[1] - 'A');
141 }
142 else
143 {
144 return -RT_EINVAL;
145 }
146
147 for (i = 3; i < name_len; i++)
148 {
149 hw_pin_num *= 10;
150 hw_pin_num += name[i] - '0';
151 }
152
153 pin = PIN_NUM(hw_port_num, hw_pin_num);
154
155 return pin;
156 }
157
apm32_pin_write(rt_device_t dev,rt_base_t pin,rt_uint8_t value)158 static void apm32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
159 {
160 GPIO_T *gpio_port;
161 uint16_t gpio_pin;
162
163 if (PIN_PORT(pin) < PIN_APMPORT_MAX)
164 {
165 gpio_port = PIN_APMPORT(pin);
166 gpio_pin = PIN_APMPIN(pin);
167 #if defined(SOC_SERIES_APM32F0)
168 GPIO_WriteBitValue(gpio_port, gpio_pin, (GPIO_BSRET_T)value);
169 #elif defined(SOC_SERIES_APM32F1) || defined(SOC_SERIES_APM32E1) || defined(SOC_SERIES_APM32S1) \
170 || defined(SOC_SERIES_APM32F4)
171 GPIO_WriteBitValue(gpio_port, gpio_pin, (uint8_t)value);
172 #endif
173 }
174 }
175
apm32_pin_read(rt_device_t dev,rt_base_t pin)176 static rt_ssize_t apm32_pin_read(rt_device_t dev, rt_base_t pin)
177 {
178 GPIO_T *gpio_port;
179 uint16_t gpio_pin;
180 int value = PIN_LOW;
181
182 if (PIN_PORT(pin) < PIN_APMPORT_MAX)
183 {
184 gpio_port = PIN_APMPORT(pin);
185 gpio_pin = PIN_APMPIN(pin);
186 value = GPIO_ReadInputBit(gpio_port, gpio_pin);
187 }
188 else
189 {
190 return -RT_EINVAL;
191 }
192
193 return value;
194 }
195
apm32_pin_mode(rt_device_t dev,rt_base_t pin,rt_uint8_t mode)196 static void apm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
197 {
198 GPIO_Config_T gpioConfig;
199
200 if (PIN_PORT(pin) >= PIN_APMPORT_MAX)
201 {
202 return;
203 }
204
205 /* Configure gpioConfigure */
206 #if defined(SOC_SERIES_APM32F1) || defined(SOC_SERIES_APM32E1) || defined(SOC_SERIES_APM32S1)
207 gpioConfig.pin = PIN_APMPIN(pin);
208 gpioConfig.mode = GPIO_MODE_OUT_PP;
209 gpioConfig.speed = GPIO_SPEED_50MHz;
210
211 if (mode == PIN_MODE_OUTPUT)
212 {
213 /* output setting */
214 gpioConfig.mode = GPIO_MODE_OUT_PP;
215 }
216 else if (mode == PIN_MODE_INPUT)
217 {
218 /* input setting: not pull. */
219 gpioConfig.mode = GPIO_MODE_IN_PU;
220 }
221 else if (mode == PIN_MODE_INPUT_PULLUP)
222 {
223 /* input setting: pull up. */
224 gpioConfig.mode = GPIO_MODE_IN_PU;
225 }
226 else if (mode == PIN_MODE_INPUT_PULLDOWN)
227 {
228 /* input setting: pull down. */
229 gpioConfig.mode = GPIO_MODE_IN_PD;
230 }
231 else if (mode == PIN_MODE_OUTPUT_OD)
232 {
233 /* output setting: od. */
234 gpioConfig.mode = GPIO_MODE_OUT_OD;
235 }
236 #elif defined(SOC_SERIES_APM32F4)
237 gpioConfig.pin = PIN_APMPIN(pin);
238 gpioConfig.mode = GPIO_MODE_OUT;
239 gpioConfig.otype = GPIO_OTYPE_PP;
240 gpioConfig.speed = GPIO_SPEED_50MHz;
241
242 if (mode == PIN_MODE_OUTPUT)
243 {
244 /* output setting */
245 gpioConfig.mode = GPIO_MODE_OUT;
246 gpioConfig.otype = GPIO_OTYPE_PP;
247 }
248 else if (mode == PIN_MODE_INPUT)
249 {
250 /* input setting: not pull. */
251 gpioConfig.mode = GPIO_MODE_IN;
252 gpioConfig.pupd = GPIO_PUPD_NOPULL;
253 }
254 else if (mode == PIN_MODE_INPUT_PULLUP)
255 {
256 /* input setting: pull up. */
257 gpioConfig.mode = GPIO_MODE_IN;
258 gpioConfig.pupd = GPIO_PUPD_UP;
259 }
260 else if (mode == PIN_MODE_INPUT_PULLDOWN)
261 {
262 /* input setting: pull down. */
263 gpioConfig.mode = GPIO_MODE_IN;
264 gpioConfig.pupd = GPIO_PUPD_DOWN;
265 }
266 else if (mode == PIN_MODE_OUTPUT_OD)
267 {
268 /* output setting: od. */
269 gpioConfig.mode = GPIO_MODE_OUT;
270 gpioConfig.otype = GPIO_OTYPE_OD;
271 }
272 #elif defined(SOC_SERIES_APM32F0)
273 gpioConfig.pin = PIN_APMPIN(pin);
274 gpioConfig.mode = GPIO_MODE_OUT;
275 gpioConfig.outtype = GPIO_OUT_TYPE_PP;
276 gpioConfig.pupd = GPIO_PUPD_NO;
277 gpioConfig.speed = GPIO_SPEED_50MHz;
278
279 if (mode == PIN_MODE_OUTPUT)
280 {
281 /* output setting */
282 gpioConfig.mode = GPIO_MODE_OUT;
283 gpioConfig.outtype = GPIO_OUT_TYPE_PP;
284 }
285 else if (mode == PIN_MODE_INPUT)
286 {
287 /* input setting: not pull. */
288 gpioConfig.mode = GPIO_MODE_IN;
289 gpioConfig.pupd = GPIO_PUPD_NO;
290 }
291 else if (mode == PIN_MODE_INPUT_PULLUP)
292 {
293 /* input setting: pull up. */
294 gpioConfig.mode = GPIO_MODE_IN;
295 gpioConfig.pupd = GPIO_PUPD_PU;
296 }
297 else if (mode == PIN_MODE_INPUT_PULLDOWN)
298 {
299 /* input setting: pull down. */
300 gpioConfig.mode = GPIO_MODE_IN;
301 gpioConfig.pupd = GPIO_PUPD_PD;
302 }
303 else if (mode == PIN_MODE_OUTPUT_OD)
304 {
305 /* output setting: od. */
306 gpioConfig.mode = GPIO_MODE_OUT;
307 gpioConfig.outtype = GPIO_OUT_TYPE_OD;
308 }
309 #endif
310 GPIO_Config(PIN_APMPORT(pin), &gpioConfig);
311 }
312
bit2bitno(rt_uint32_t bit)313 rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
314 {
315 int i;
316 for (i = 0; i < 32; i++)
317 {
318 if ((0x01 << i) == bit)
319 {
320 return i;
321 }
322 }
323 return -1;
324 }
325
get_pin_irq_map(uint32_t pinbit)326 rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
327 {
328 rt_int32_t mapindex = bit2bitno(pinbit);
329 if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
330 {
331 return RT_NULL;
332 }
333 return &pin_irq_map[mapindex];
334 };
335
apm32_pin_attach_irq(struct rt_device * device,rt_base_t pin,rt_uint8_t mode,void (* hdr)(void * args),void * args)336 static rt_err_t apm32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
337 rt_uint8_t mode, void (*hdr)(void *args), void *args)
338 {
339 rt_base_t level;
340 rt_int32_t irqindex = -1;
341
342 if (PIN_PORT(pin) >= PIN_APMPORT_MAX)
343 {
344 return -RT_ENOSYS;
345 }
346
347 irqindex = bit2bitno(PIN_APMPIN(pin));
348 if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
349 {
350 return -RT_ENOSYS;
351 }
352
353 level = rt_hw_interrupt_disable();
354 if (pin_irq_hdr_tab[irqindex].pin == pin &&
355 pin_irq_hdr_tab[irqindex].hdr == hdr &&
356 pin_irq_hdr_tab[irqindex].mode == mode &&
357 pin_irq_hdr_tab[irqindex].args == args)
358 {
359 rt_hw_interrupt_enable(level);
360 return RT_EOK;
361 }
362 if (pin_irq_hdr_tab[irqindex].pin != -1)
363 {
364 rt_hw_interrupt_enable(level);
365 return -RT_EBUSY;
366 }
367 pin_irq_hdr_tab[irqindex].pin = pin;
368 pin_irq_hdr_tab[irqindex].hdr = hdr;
369 pin_irq_hdr_tab[irqindex].mode = mode;
370 pin_irq_hdr_tab[irqindex].args = args;
371 rt_hw_interrupt_enable(level);
372
373 return RT_EOK;
374 }
375
apm32_pin_dettach_irq(struct rt_device * device,rt_base_t pin)376 static rt_err_t apm32_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
377 {
378 rt_base_t level;
379 rt_int32_t irqindex = -1;
380
381 if (PIN_PORT(pin) >= PIN_APMPORT_MAX)
382 {
383 return -RT_ENOSYS;
384 }
385
386 irqindex = bit2bitno(PIN_APMPIN(pin));
387 if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
388 {
389 return -RT_ENOSYS;
390 }
391
392 level = rt_hw_interrupt_disable();
393 if (pin_irq_hdr_tab[irqindex].pin == -1)
394 {
395 rt_hw_interrupt_enable(level);
396 return RT_EOK;
397 }
398 pin_irq_hdr_tab[irqindex].pin = -1;
399 pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
400 pin_irq_hdr_tab[irqindex].mode = 0;
401 pin_irq_hdr_tab[irqindex].args = RT_NULL;
402 rt_hw_interrupt_enable(level);
403
404 return RT_EOK;
405 }
406
apm32_pin_irq_enable(struct rt_device * device,rt_base_t pin,rt_uint8_t enabled)407 static rt_err_t apm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
408 rt_uint8_t enabled)
409 {
410 const struct pin_irq_map *irqmap;
411 rt_base_t level;
412 rt_int32_t irqindex = -1;
413 GPIO_Config_T gpioConfig;
414 EINT_Config_T eintConfig;
415
416 if (PIN_PORT(pin) >= PIN_APMPORT_MAX)
417 {
418 return -RT_ENOSYS;
419 }
420
421 if (enabled == PIN_IRQ_ENABLE)
422 {
423 irqindex = bit2bitno(PIN_APMPIN(pin));
424 if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
425 {
426 return -RT_ENOSYS;
427 }
428
429 level = rt_hw_interrupt_disable();
430
431 if (pin_irq_hdr_tab[irqindex].pin == -1)
432 {
433 rt_hw_interrupt_enable(level);
434 return -RT_ENOSYS;
435 }
436
437 irqmap = &pin_irq_map[irqindex];
438
439 /* Configure gpioConfigure */
440 gpioConfig.pin = PIN_APMPIN(pin);
441 gpioConfig.speed = GPIO_SPEED_50MHz;
442 switch (pin_irq_hdr_tab[irqindex].mode)
443 {
444 #if defined(SOC_SERIES_APM32F0)
445 case PIN_IRQ_MODE_RISING:
446 gpioConfig.mode = GPIO_MODE_IN;
447 gpioConfig.pupd = GPIO_PUPD_PD;
448 eintConfig.trigger = EINT_TRIGGER_RISING;
449 break;
450 case PIN_IRQ_MODE_FALLING:
451 gpioConfig.mode = GPIO_MODE_IN;
452 gpioConfig.pupd = GPIO_PUPD_PU;
453 eintConfig.trigger = EINT_TRIGGER_FALLING;
454 break;
455 case PIN_IRQ_MODE_RISING_FALLING:
456 gpioConfig.mode = GPIO_MODE_IN;
457 gpioConfig.pupd = GPIO_PUPD_NO;
458 eintConfig.trigger = EINT_TRIGGER_ALL;
459 break;
460 #elif defined(SOC_SERIES_APM32F1) || defined(SOC_SERIES_APM32E1) || defined(SOC_SERIES_APM32S1)
461 case PIN_IRQ_MODE_RISING:
462 gpioConfig.mode = GPIO_MODE_IN_PD;
463 eintConfig.trigger = EINT_TRIGGER_RISING;
464 break;
465 case PIN_IRQ_MODE_FALLING:
466 gpioConfig.mode = GPIO_MODE_IN_PU;
467 eintConfig.trigger = EINT_TRIGGER_FALLING;
468 break;
469 case PIN_IRQ_MODE_RISING_FALLING:
470 gpioConfig.mode = GPIO_MODE_IN_FLOATING;
471 eintConfig.trigger = EINT_TRIGGER_RISING_FALLING;
472 break;
473 #elif defined(SOC_SERIES_APM32F4)
474 case PIN_IRQ_MODE_RISING:
475 gpioConfig.mode = GPIO_MODE_IN;
476 gpioConfig.pupd = GPIO_PUPD_DOWN;
477 eintConfig.trigger = EINT_TRIGGER_RISING;
478 break;
479 case PIN_IRQ_MODE_FALLING:
480 gpioConfig.mode = GPIO_MODE_IN;
481 gpioConfig.pupd = GPIO_PUPD_UP;
482 eintConfig.trigger = EINT_TRIGGER_FALLING;
483 break;
484 case PIN_IRQ_MODE_RISING_FALLING:
485 gpioConfig.mode = GPIO_MODE_IN;
486 gpioConfig.pupd = GPIO_PUPD_NOPULL;
487 eintConfig.trigger = EINT_TRIGGER_RISING_FALLING;
488 break;
489 #endif
490 }
491 GPIO_Config(PIN_APMPORT(pin), &gpioConfig);
492
493 #if defined(SOC_SERIES_APM32F0)
494 RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_SYSCFG);
495 SYSCFG_EINTLine((SYSCFG_PORT_T)(((pin) >> 4) & 0xFu), (SYSCFG_PIN_T)irqindex);
496 #elif defined(SOC_SERIES_APM32F1) || defined(SOC_SERIES_APM32E1) || defined(SOC_SERIES_APM32S1)
497 RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_AFIO);
498 GPIO_ConfigEINTLine((GPIO_PORT_SOURCE_T)(((pin) >> 4) & 0xFu), (GPIO_PIN_SOURCE_T)irqindex);
499 #elif defined(SOC_SERIES_APM32F4)
500 RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_SYSCFG);
501 SYSCFG_ConfigEINTLine((SYSCFG_PORT_T)(((pin) >> 4) & 0xFu), (SYSCFG_PIN_T)irqindex);
502 #endif
503 eintConfig.line = (EINT_LINE_T)(1u << PIN_NO(pin));
504 eintConfig.mode = EINT_MODE_INTERRUPT;
505 eintConfig.lineCmd = ENABLE;
506 EINT_Config(&eintConfig);
507
508 #if defined(SOC_SERIES_APM32F0)
509 NVIC_EnableIRQRequest(irqmap->irqno, 5);
510 #elif defined(SOC_SERIES_APM32F1) || defined(SOC_SERIES_APM32E1) || defined(SOC_SERIES_APM32S1) \
511 || defined(SOC_SERIES_APM32F4)
512 NVIC_EnableIRQRequest(irqmap->irqno, 5, 0);
513 #endif
514 pin_irq_enable_mask |= irqmap->pinbit;
515
516 rt_hw_interrupt_enable(level);
517 }
518 else if (enabled == PIN_IRQ_DISABLE)
519 {
520 irqmap = get_pin_irq_map(PIN_APMPIN(pin));
521 if (irqmap == RT_NULL)
522 {
523 return -RT_ENOSYS;
524 }
525
526 level = rt_hw_interrupt_disable();
527
528 pin_irq_enable_mask &= ~irqmap->pinbit;
529
530 #if defined(SOC_SERIES_APM32F0)
531 if ((irqmap->pinbit >= GPIO_PIN_0) && (irqmap->pinbit <= GPIO_PIN_1))
532 {
533 if (!(pin_irq_enable_mask & (GPIO_PIN_0 | GPIO_PIN_1)))
534 {
535 NVIC_DisableIRQRequest(irqmap->irqno);
536 }
537 }
538 else if ((irqmap->pinbit >= GPIO_PIN_2) && (irqmap->pinbit <= GPIO_PIN_3))
539 {
540 if (!(pin_irq_enable_mask & (GPIO_PIN_2 | GPIO_PIN_3)))
541 {
542 NVIC_DisableIRQRequest(irqmap->irqno);
543 }
544 }
545 else if ((irqmap->pinbit >= GPIO_PIN_4) && (irqmap->pinbit <= GPIO_PIN_15))
546 {
547 if (!(pin_irq_enable_mask & (GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 |
548 GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15)))
549 {
550 NVIC_DisableIRQRequest(irqmap->irqno);
551 }
552 }
553 else
554 {
555 NVIC_DisableIRQRequest(irqmap->irqno);
556 }
557 #elif defined(SOC_SERIES_APM32F1) || defined(SOC_SERIES_APM32E1) || defined(SOC_SERIES_APM32S1) \
558 || defined(SOC_SERIES_APM32F4)
559 if ((irqmap->pinbit >= GPIO_PIN_5) && (irqmap->pinbit <= GPIO_PIN_9))
560 {
561 if (!(pin_irq_enable_mask & (GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9)))
562 {
563 NVIC_DisableIRQRequest(irqmap->irqno);
564 }
565 }
566 else if ((irqmap->pinbit >= GPIO_PIN_10) && (irqmap->pinbit <= GPIO_PIN_15))
567 {
568 if (!(pin_irq_enable_mask & (GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15)))
569 {
570 NVIC_DisableIRQRequest(irqmap->irqno);
571 }
572 }
573 else
574 {
575 NVIC_DisableIRQRequest(irqmap->irqno);
576 }
577 #endif /* SOC_SERIES_APM32F0 */
578 rt_hw_interrupt_enable(level);
579 }
580 else
581 {
582 return -RT_ENOSYS;
583 }
584
585 return RT_EOK;
586 }
587
588 const static struct rt_pin_ops apm32_pin_ops =
589 {
590 apm32_pin_mode,
591 apm32_pin_write,
592 apm32_pin_read,
593 apm32_pin_attach_irq,
594 apm32_pin_dettach_irq,
595 apm32_pin_irq_enable,
596 apm32_pin_get,
597 };
598
pin_irq_hdr(int irqno)599 rt_inline void pin_irq_hdr(int irqno)
600 {
601 if (pin_irq_hdr_tab[irqno].hdr)
602 {
603 pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
604 }
605 }
606
GPIO_EXTI_IRQHandler(uint8_t exti_line)607 void GPIO_EXTI_IRQHandler(uint8_t exti_line)
608 {
609 #if defined(SOC_SERIES_APM32F0)
610 if (EINT_ReadIntFlag(1U << exti_line) != RESET)
611 #elif defined(SOC_SERIES_APM32F1) || defined(SOC_SERIES_APM32E1) || defined(SOC_SERIES_APM32S1) \
612 || defined(SOC_SERIES_APM32F4)
613 if (EINT_ReadIntFlag((EINT_LINE_T)(1U << exti_line)) != RESET)
614 #endif
615 {
616 EINT_ClearIntFlag(1U << exti_line);
617 pin_irq_hdr(exti_line);
618 }
619 }
620
621 #if defined(SOC_SERIES_APM32F0)
EINT0_1_IRQHandler(void)622 void EINT0_1_IRQHandler(void)
623 {
624 rt_interrupt_enter();
625 GPIO_EXTI_IRQHandler(0);
626 GPIO_EXTI_IRQHandler(1);
627 rt_interrupt_leave();
628 }
629
EINT2_3_IRQHandler(void)630 void EINT2_3_IRQHandler(void)
631 {
632 rt_interrupt_enter();
633 GPIO_EXTI_IRQHandler(2);
634 GPIO_EXTI_IRQHandler(3);
635 rt_interrupt_leave();
636 }
EINT4_15_IRQHandler(void)637 void EINT4_15_IRQHandler(void)
638 {
639 rt_interrupt_enter();
640 GPIO_EXTI_IRQHandler(4);
641 GPIO_EXTI_IRQHandler(5);
642 GPIO_EXTI_IRQHandler(6);
643 GPIO_EXTI_IRQHandler(7);
644 GPIO_EXTI_IRQHandler(8);
645 GPIO_EXTI_IRQHandler(9);
646 GPIO_EXTI_IRQHandler(10);
647 GPIO_EXTI_IRQHandler(11);
648 GPIO_EXTI_IRQHandler(12);
649 GPIO_EXTI_IRQHandler(13);
650 GPIO_EXTI_IRQHandler(14);
651 GPIO_EXTI_IRQHandler(15);
652 rt_interrupt_leave();
653 }
654 #elif defined(SOC_SERIES_APM32F1) || defined(SOC_SERIES_APM32E1) || defined(SOC_SERIES_APM32S1) \
655 || defined(SOC_SERIES_APM32F4)
EINT0_IRQHandler(void)656 void EINT0_IRQHandler(void)
657 {
658 rt_interrupt_enter();
659 GPIO_EXTI_IRQHandler(0);
660 rt_interrupt_leave();
661 }
662
EINT1_IRQHandler(void)663 void EINT1_IRQHandler(void)
664 {
665 rt_interrupt_enter();
666 GPIO_EXTI_IRQHandler(1);
667 rt_interrupt_leave();
668 }
669
EINT2_IRQHandler(void)670 void EINT2_IRQHandler(void)
671 {
672 rt_interrupt_enter();
673 GPIO_EXTI_IRQHandler(2);
674 rt_interrupt_leave();
675 }
676
EINT3_IRQHandler(void)677 void EINT3_IRQHandler(void)
678 {
679 rt_interrupt_enter();
680 GPIO_EXTI_IRQHandler(3);
681 rt_interrupt_leave();
682 }
683
EINT4_IRQHandler(void)684 void EINT4_IRQHandler(void)
685 {
686 rt_interrupt_enter();
687 GPIO_EXTI_IRQHandler(4);
688 rt_interrupt_leave();
689 }
690
EINT9_5_IRQHandler(void)691 void EINT9_5_IRQHandler(void)
692 {
693 rt_interrupt_enter();
694 GPIO_EXTI_IRQHandler(5);
695 GPIO_EXTI_IRQHandler(6);
696 GPIO_EXTI_IRQHandler(7);
697 GPIO_EXTI_IRQHandler(8);
698 GPIO_EXTI_IRQHandler(9);
699 rt_interrupt_leave();
700 }
701
EINT15_10_IRQHandler(void)702 void EINT15_10_IRQHandler(void)
703 {
704 rt_interrupt_enter();
705 GPIO_EXTI_IRQHandler(10);
706 GPIO_EXTI_IRQHandler(11);
707 GPIO_EXTI_IRQHandler(12);
708 GPIO_EXTI_IRQHandler(13);
709 GPIO_EXTI_IRQHandler(14);
710 GPIO_EXTI_IRQHandler(15);
711 rt_interrupt_leave();
712 }
713 #endif
714
rt_hw_pin_init(void)715 int rt_hw_pin_init(void)
716 {
717 #if defined(SOC_SERIES_APM32F1) || defined(SOC_SERIES_APM32E1) || defined(SOC_SERIES_APM32S1)
718 #ifdef GPIOA
719 RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOA);
720 #endif
721 #ifdef GPIOB
722 RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOB);
723 #endif
724 #ifdef GPIOC
725 RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOC);
726 #endif
727 #ifdef GPIOD
728 RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOD);
729 #endif
730 #ifdef GPIOE
731 RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOE);
732 #endif
733 #ifdef GPIOF
734 RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOF);
735 #endif
736 #ifdef GPIOG
737 RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOG);
738 #endif
739 RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_AFIO);
740 #elif defined(SOC_SERIES_APM32F4)
741 #ifdef GPIOA
742 RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOA);
743 #endif
744 #ifdef GPIOB
745 RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOB);
746 #endif
747 #ifdef GPIOC
748 RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOC);
749 #endif
750 #ifdef GPIOD
751 RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOD);
752 #endif
753 #ifdef GPIOE
754 RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOE);
755 #endif
756 #ifdef GPIOF
757 RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOF);
758 #endif
759 #ifdef GPIOG
760 RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOG);
761 #endif
762 #ifdef GPIOH
763 RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOH);
764 #endif
765 #ifdef GPIOI
766 RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOI);
767 #endif
768 #ifdef GPIOJ
769 RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOJ);
770 #endif
771 #ifdef GPIOK
772 RCM_EnableAHB1PeriphClock(RCM_AHB1_PERIPH_GPIOK);
773 #endif
774
775 #elif defined(SOC_SERIES_APM32F0)
776 #ifdef GPIOA
777 RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_GPIOA);
778 #endif
779 #ifdef GPIOB
780 RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_GPIOB);
781 #endif
782 #ifdef GPIOC
783 RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_GPIOC);
784 #endif
785 #ifdef GPIOD
786 RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_GPIOD);
787 #endif
788 #ifdef GPIOE
789 RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_GPIOE);
790 #endif
791 #ifdef GPIOF
792 RCM_EnableAHBPeriphClock(RCM_AHB_PERIPH_GPIOF);
793 #endif
794
795 #endif /* SOC_SERIES_APM32F0 */
796
797 return rt_device_pin_register("pin", &apm32_pin_ops, RT_NULL);
798 }
799
800 #endif /* RT_USING_PIN */
801